JPS60254480A - Bubble memory controller - Google Patents

Abstract

PURPOSE:To shorten the occupation time of a host computer by providing the 1st and the 2nd FiFo means and a counting means for bits. CONSTITUTION:A circulating circuit system for data has the 1st FiFo means 1A and the 2nd FiFo means 1B, a bit counting circuit system ouputs a signal when outputs of the 1st and the 2nd registers 5A and 5B coincide with outputs of the 1st and the 2nd counting means 6A and 6B, thereby performing the switching of an MPX. For example, data of every page is divided into three blocks; the 1st block is stored in the 2nd FiFo means, only the 2nd block is outputted to the host computer 4, and the 3rd block is stored in the 1st FiFo means. Consequently, an optional number of bits at an optional location are specified and read out, and also rewritten, so that the occupation time of the host computer is shortened.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a control device for controlling the writing and reading of information to and from a magnetic bubble device constituted by a plurality of memory loops, and particularly relates to a bubble memory control device and a host device. The present invention relates to a control means that is located between computers and controls the flow of information.

A magnetic bubble device that stores and transfers information by controlling magnetic bubbles is composed of one major loop and 256 or 512 memory loops that engage with it. Information is generally written and output to a bubble device in units of bits (referred to as one page) corresponding to 256 or 512 minor loops engaged in one major loop. Therefore, even when writing or reading one byte of information, it is necessary to write or read one page one after another, which causes an inconvenient problem in that the host computer is tied up and processing of other information stops. There is.

Therefore, it is desired to develop a bubble memory control device that can shorten the host computer's time commitment by decomposing the contents of one page and writing and reading only the minimum necessary number of bits.

(bl Conventional technology Fig. 2 shows a conventional control means, fat in Fig. 2 is a block diagram,
Figure 2 (bl is a data flow diagram during writing, Figure 2 tc+
is a data flow diagram during continuous output.

As shown in FIG. 2 (al), this control means is a storage means (hereinafter referred to as F
It consists of a multiplexer (hereinafter referred to as MPX) 2^, 2B, and 2C that switches the flow of information, and is located between the bubble memory control device 3 and the host computer 4 and controls the flow of information. .

The data flow when writing information to the magnetic bubble device is shown in Figure 2 (bl). Data input from the host computer 4 is sent to the F via MPX 2A and 2B.
It is temporarily stored in the iFo means 1, and when a write start signal is issued from the host computer 4, the MPX is stored from the FiFo means 1.
It is output to the bubble memory control device 3 via 2C.

On the other hand, the data flow when reading information from the magnetic couple device is as shown in FIG. When a signal to start reading is issued from the host computer 4, the data is outputted from the FiFo means 1 to the host computer 4 via the MPX 2^.

In addition, when rewriting part of the information, first read out one page of information according to the data flow shown in Figure 2 (C1),
After rewriting part of the information, information is written according to the data flow shown in FIG. 2(b).

(cl) Problems that the invention seeks to solve The conventional control means shown in Figure 2 (al) has an
Since there is only one O means and it does not have the function of dividing the arranged bit string or the editing function of replacing some bits/nodes, it is difficult to transfer data from the host computer 4 to the bubble memory control device 3. Transfer or data transfer from the bubble memory control device 3 to the postcomputer 4 is always performed in units of one page.

Tdl Means for Solving Problems Box 1, a second PiFo means, an MPX provided between the FiFo means, first and second configurable registers, and successive steps from the first FiFo means. a first counting means for counting the number of bits written to the second PiFo means; a second counting means for counting the number of bits written to the second PiFo means; The above-mentioned problem is solved by a bubble memory control device including a comparison circuit for comparing the outputs of the second counting means.

(el) By using the above means provided with the first and second FiFo means and bit counting means, for example, one page of data can be
Divide into blocks, store the first block in the second FiFo means, output only the second block to the host computer 4, and store the third block in the first FiFo means. is possible.

Therefore, it becomes possible to designate and read any number of bits at any position and to designate and rewrite any number of bits at any position, thereby reducing the host combinator's constraint time.

(fl Example The present invention will be explained in detail below with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the control means according to the present invention.
+ is a block diagram of the control means, Fig. 1(b) to Fig. 1Te
1 is a data flow diagram when writing and rewriting specified arbitrary data, Figure 1 if) and Figure 1 (g) are data flow diagrams when writing and reading all data for one page, Figure 1 Figure (hl) and Figure 1 (11 are timing charts).

In FIG. 1 (al), the control means according to the present invention is composed of a data distribution circuit system and a bit counting circuit system.
It consists of an iFo means IB and MPX 28, 2B, 2C and 2D, the MPX being installed between a bubble memory controller, two Pico means for temporarily storing information, and a host computer. , each switches the information distribution route.

Further, the bit counting circuit system includes a first register 5^ for setting the position of the first bit of the data to be read, a second register 5B for setting the position of the last bit of the data to be read, and the first FiFo means. a first counting means 6A for counting the number of vias read out from the first register 5^; a second counting means 6B for counting the number of bits written to the second FiFo means; The output of the second register 5B, the first counting means 68 and the second counting means 6B
If the outputs of the first register 58 and the second register 5B match the outputs of the first counting means 6A and the second counting means 6B, A signal is issued to switch the MPX.

The reading and rewriting of specified data in this control means is performed by specifying the position N1 of the first bit of the data to be read into the first register 5A and the position N2 of the last bit of the data to be read into the second register 5B, and then issuing a command. Input data and start rewriting.

That is, the output to the first counting means 6 is the same as the output to the second counting means 6.
The output of B is n2.If the total number of bits and nodes of one page is N, the data input from the bubble memory control device 3 is MPX
First FiF via 2C and 2B.

It is temporarily stored in means 18, and in the range of 0≦old<N+, O≦n2<N+,
The data read from the Fo means 1^ is shown in FIG.
As shown in FIG. 2, the data is temporarily stored in the second (7) FiFo means IB via the MPX2D.

Next, when n+=N+, a match signal is generated from the comparator circuit 7, MPX 2D and 2^ are switched, and N1≦old≦
In the range of N2, N+ ≦n2≦N2, the first FiFo
The data read from the means 18 is output to the host computer 4 via the MPX 2D and 2A as shown in FIG. is Figure 1 +
It is temporarily stored in the second FiFo means IB via the path shown in d), ie, MPX 2A and 2D.

Furthermore, when n+ = N2 in the case of data reading, and when n2 = N2 in the case of data rewriting, a match signal is generated from the comparator circuit 7, MPX 2D and 28 are switched, and N2 < n+ ≦N, N2 < nz≦ In the range of N, the data read from the first FiFo means 18 is
Again, as shown in FIG. 1 (bl), the data is temporarily stored in the 20th FiFo means IB via the MPX 2D.

Further, the data temporarily stored in the second FiFo means IB is output to the bubble memory control device 3 via the MPX 2C, as shown in FIG.

Figure 1 (h) shows data movement when reading arbitrary data (b), and Figure 1 (i) shows data movement when reading arbitrary data (b) and rewriting it to It is a timing chart showing movement.

By setting NI=0 and N2=N in this control means, it is possible to read and write in units of one page.

However, as shown in FIG. 1(f), the bubble memory control device 3
The input data is temporarily stored in the first FiFo means 8 via MPX 2C and 2B, and
The data read from the Fo means IA is temporarily stored in the second FiFo means IB via MPX 2D, and further stored in the second FiFo means IB.
By configuring the data read from the FiFo means IB to be output to the host computer 4 via 2A, the data can be output one page at a time in the same way as before, and two pages at a time. It is possible to obtain a control means that can temporarily store data for minutes.

In addition, as shown in FIG. 1 (phantom), data input from the host computer 4 is temporarily stored in the first FiFo means 1^ via MPX 2A and 2B, and data read from the first FiFo means IA is Temporarily stored in the second PiFo means IB via MPX 2D, and further stored in the second PiFo means IB.
By configuring the data read from the Fo means IB to be output to the bubble memory control device 3 via the MPX 2C, it is possible to write in units of 1 page in the same way as the subordinate tree, and moreover, in 2-page units. It is possible to obtain a control means that can temporarily store data for minutes.

According to the bubble memory control device equipped with the control means according to the present invention, only the data in the specified range is output to the host computer 4, and only the data in the specified range is rewritten by the host computer 4. , and other data can all be processed within the bubble memory control device, reducing the time required for the host computer.

(gl) Effects of the Invention As described above, according to the present invention, it is possible to provide a bubble memory control device that can shorten the time that a host computer is restricted.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the control means according to the present invention, and FIG. 2 shows a conventional control means. In the figure, j71, IB is FiFo means, 28, 2B, 2c, 2D
is MPχ, 3 is a bubble memory control device, 4 is a host computer, 5^ and 5B are registers, 68 and 6B are counting means, and 7 is a comparison circuit, respectively. Sheet 1 diagram (b> Hayabusa 1 director (c) Stem 1 diagram (cl) 111 diagram and e) $lp (su) Leather 1 diagram (9-) Command゛Write 111 pi 1 and k)

Claims (1)

[Scope of Claims] A control device that controls writing and reading of information to and from a magnetic bubble device constituted by a plurality of storage loops, comprising: first and second FiFo means; a multiplexer provided between the FiFo means; , first and second configurable registers, first counting means for counting the number of bits read from said first FiFo means, and said second FiFo means.
a second counting means for counting the number of bits written in the o means; and a comparison circuit for comparing the outputs of the first and second registers with the outputs of the first and second stitch count means. A bubble memory control device characterized by: