JP4769020B2 - Interface circuit and optical disk apparatus - Google Patents

Description

  The present invention relates to an interface circuit that performs data transfer processing.

  When transferring data between circuits having different clock frequencies, an interface circuit that performs data transfer via FIFO (First In First Out) in order to absorb differences in data transfer speeds and transfer protocols between circuits. Used.

  In this interface circuit, it is determined whether the FIFO is composed of a RAM or a register depending on the required depth of the FIFO. In the case where the number of FIFO stages is small, the FIFO is constituted by registers that are superior in circuit scale. In an interface circuit that transfers data via a FIFO constituted by this register, it is required to operate at high speed and to simplify the circuit configuration, and many inventions have been made (for example, Patent Document 1). .

  The configuration of such an interface circuit in the prior art will be described. FIG. 19 is a block diagram showing a configuration of an interface circuit in the prior art. The interface circuit 31 shown in the prior art includes a shift register 310, an input pointer control circuit 311, an output data selector 312, an output pointer control circuit 313, and a shift operation control circuit 314.

  The process flow of the interface circuit in the prior art will be briefly described. The shift register 310 receives input data from the data write circuit 300. At this time, when the input data unit is a data amount corresponding to a plurality of registers constituting the shift register 310, the data is sequentially input to the registers in the shift register 310 based on a signal from the input pointer control circuit 311.

  After that, the shift register 310 performs a shift process on the input data. In response to the data read request signal from the data read circuit 320, the output pointer control circuit 313 instructs to output data from the shift register 310 to the data read circuit 320 in order for each output data unit previously input in the shift register 310. The control signal to be output is output to the output data selector 312.

  When a signal is input from the output pointer control circuit 313, the output data selector 312 receives data from a register corresponding to the signal in the shift register 310 and outputs the data to the data read circuit 32. By repeating this for the number of output data units, data is output.

  By using the shift register in this manner, it is possible to limit the registers that perform input / output. Therefore, the input pointer control circuit 311 can be compared with the case where data is input / output by designating registers from all the registers included in the shift register. This makes it possible to simplify the circuit configuration. However, when the input / output is a burst transfer performed in units of a capacity of a plurality of registers provided in the shift register, although not from all the registers provided in the shift register, to which register the data is input to the shift register, A pointer control circuit that performs a process of designating from the number of registers corresponding to the data input / output unit is required. Further, since the output pointer control circuit 313 selects a register that outputs data from all the registers that constitute the shift register 310, the output pointer control circuit 313 has a circuit configuration when the number of registers that constitute the shift register 310 increases. It gets bigger.

Furthermore, in the case of the configuration shown in the prior art, when the operation clock frequencies of the data write circuit 300 and the data read circuit 32 are different, a synchronization circuit for controlling the timing is required, and the circuit configuration becomes complicated.
JP 2001-43672 A

  Thus, the conventional interface circuit has a problem that the circuit configuration becomes complicated. In addition, in order to input / output data to / from circuits having different clocks, timing control is required, and further, the circuit configuration becomes large and complicated.

  The interface circuit according to the present invention is an interface circuit for interfacing data transfer between different circuits, and includes a plurality of registers, and the transfer data inputted between the different circuits is sequentially transferred between the registers. A register and a register storage state data holding circuit for holding data indicating whether or not the stored data of each of the plurality of registers is valid; With such a configuration, the circuit configuration of the interface circuit can be made small and simple.

  An interface circuit according to the present invention is an interface circuit for interfacing data transfer between a first circuit and a second circuit, and is composed of a plurality of data holding elements. Data transfer between the second circuit and the shift register that sequentially transfers data between the first circuit and the second circuit, temporarily stores the transfer data, and the shift And a buffer connected to a part of the data holding element of the register and transferring the data to and from the connected data holding element.

  Another interface circuit according to the present invention is an interface circuit that performs interface processing of data transfer between a first circuit and a second circuit, and includes a plurality of registers, and sequentially receives input data between the registers. The shift register is connected to a shift register and a plurality of registers that are part of the shift register, and includes a sub-buffer that transfers data to and from the second circuit. With such a configuration, data can be input / output with a circuit having a different clock.

  According to the present invention, the circuit configuration of the interface circuit can be configured more simply and with a reduced scale.

Embodiment 1 of the Invention
FIG. 1 is a diagram illustrating a configuration example of a DVD device using an interface circuit according to Embodiment 1 of the present invention. The DVD device 1 includes a control circuit 10, an interface circuit 11, an SDRAM 12, and a DVD reading circuit 13. Other circuit configurations are omitted here.

  The control circuit 10 is an arithmetic device that controls the DVD device 1 and includes a CPU (Central Processing Unit) and the like. The control circuit 10 performs output control of data to be written to the SDRAM 12, input of data output from the SDRAM 12, and input / output control of data output from the DVD reading circuit 13. Data input / output between the control circuit 10, the SDRAM 12, and the DVD reading circuit 13 is performed via the interface circuit 11.

  The interface circuit 11 is an interface circuit through which data is input / output among the control circuit 10, SDRAM 12, and DVD reading circuit 13. The configuration of the interface circuit 11 will be described in detail later.

  The SDRAM 12 is a memory that stores data. When the DVD device 1 operates, the SDRAM 12 inputs data output from the DVD reading circuit 13 according to a command from the control circuit 10. Here, the SDRAM 12 is used as a buffer that absorbs a difference in data transfer speed between the control circuit 10 and the DVD reading circuit 13 and a difference in transfer protocol. Further, the SDRAM 12 here includes a read circuit that outputs data input from the interface circuit 11 and a signal requesting data output to the interface circuit 11.

  The DVD reading circuit 13 reads data from a DVD. The data read by the DVD reading circuit 13 is finally output to the control circuit 10 and processed by the control circuit 10. However, the DVD reading circuit 13 first outputs the read data to the SDRAM 12 serving as a buffer via the interface circuit 11.

  Next, the configuration of the interface circuit 11 will be described using the block diagram shown in FIG. The interface circuit 11 in FIG. 2 has an interface circuit configuration in which writing to the interface circuit 11 is performed in units of one word and output to the data reading circuit is performed in units of a plurality of words. The interface circuit 11 includes a shift register 110, a flag bit shift register 111, and a sub buffer 112.

  The shift register 110 includes a plurality of registers that are data holding elements, and data is sequentially transferred between the registers. The shift register here is a shift register that transfers data in units of words. That is, one register stores one word of data. The shift register 110 is connected to the data reading circuit 100 and can write data.

  The flag bit shift register 111 is composed of a plurality of flag bit registers, and data is sequentially transferred between the flag bits. Each bit of the flag bit shift register 111 corresponds to each register of the shift register 110, and represents whether or not the data stored in the corresponding register is valid.

  The sub-buffer 112 is a buffer for outputting data in units of a plurality of words to the reading side, and stores the data accumulated in the shift register 110. The data stored in the sub-buffer 112 is output to the data read circuit 120 according to the interface protocol with the read circuit.

  Next, the configuration of the shift register 110, flag bit shift register 111, and sub-buffer 112 will be described in detail. FIG. 3 is a diagram showing the configuration of the shift register 110, flag bit shift register 111, and sub-buffer 112 in the present invention.

  Here, a case where one word is 4 bits and data is output in units of 4 words will be described. That is, one register of the shift register 110 stores 1 word, that is, 4-bit data. The shift register can store 32 words of data. In this case, the shift register 110 includes 32 registers R0 to R31. Here, for the sake of explanation, the lower number is called the lower level and the higher number is called the higher level. In the present embodiment, the shift register 110 and the flag bit shift register 111 transfer data from lower to higher.

  The flag bit shift register 111 stores 32-bit flag bits from F0 to F31. Each bit F0 to F31 of the flag bit shift register 111 indicates whether or not valid data is stored in the registers R0 to R31. Here, it is assumed that valid data is 1 and invalid data is 0.

  The sub-buffer 112 can store 4 words of data. The reason why the data is 4 words is that the data output is in units of 4 words, and the data capacity of the sub-buffer 112 is determined by the data output unit.

  The sub-buffer 112 stores the data of the highest register of the shift register 110. In this embodiment, the sub-buffer has a 4-word size, and stores data in the registers R28 to R31 which are the highest level of the shift register.

  Next, the process flow of the interface circuit 11 will be described. FIG. 4 is a flowchart showing a processing flow of the interface circuit 11 in the present invention.

  First, the shift register 110 checks whether or not there is a data write request from the data write circuit 100 (S10). If there is a write request as a result of the confirmation, the data is stored in the register R0. Therefore, whether the data can be written to the register R0 of the shift register 110 is confirmed by the fact that F0 of the flag bit shift register 111 is 0. (S11). If F0 is not 0, writing is impossible and error processing is performed (S12). The content of the error processing is not particularly limited. For example, a signal that cannot be written is output to the control circuit 10.

  When F0 of the flag bit shift register 111 is 1, the shift register 110 inputs data from the control circuit 10 and writes input data to the register R0 (S13). The flag bit shift register 111 sets F0 of the flag bit shift register 111 to 1 to indicate that data has been stored because data has been written to the register R0 (S14).

  The shift register 110 and the flag bit shift register 111 perform shift processing (S15). Even when there is no data write request from the data write circuit 100, the shift register 110 and the flag bit shift register 111 perform shift processing (S16).

  The contents of the shift process will be specifically described. First, the flag bit shift register 111 stores the flag bit and data stored in the one higher register for the flag bit shift register lower than the highest register whose flag bit is 0 and all the corresponding shift registers. shift. Whether or not to shift under this condition is determined by ANDing the flag bits of all registers existing on the upper side of each register. If the result is 0, the stored flag bit and data are shifted to the next higher register. For example, when F28 to F31 of the flag bit shift register 111 are 1 and F27 is 0, the highest-order register whose flag bit is 0 is F27. In this case, the data of F0 to F26 of the flag bit shift register 111 and the data of R0 to R26 of the shift register 110 are transferred to the upper register.

  This transfer is performed at a predetermined timing such as an input clock. In this way, data can be transferred from the least significant register to the most significant register without any gap. When there is no data write request from the data write circuit 100, F0 of the flag bit shift register 111 is set to 0 (S17).

  Further, the shift register 110 determines whether or not valid data is stored in the upper 4 words, that is, all registers 28 to 31 (S18). The determination at this time is made by determining that all the flag bit shift registers 111 are set to 1.

  As a result of the determination, if valid data is stored in the upper 4 word register, the free space in the sub-buffer 112 is confirmed (S19). If there is an empty space in the sub-buffer 112, the data of the upper 4 words register is stored in the sub-buffer 112 (S20). Further, the registers of the flag bit shift register 111 corresponding to the upper 4 word registers, that is, F28 to F31 are set to 0.

  When data is stored in the sub-buffer 112, data can be output to the data reading circuit 120. Therefore, the sub-buffer 112 outputs a signal indicating that data can be output to the data reading circuit 120. To do. When a signal indicating that the sub-buffer 112 can output data is input, the data reading circuit 120 outputs a signal requesting data output to the sub-buffer 112 as necessary. Operations in this shift processing such as data transfer to the upper register, data write, and transfer to the sub-buffer 112 are all performed at the same timing.

  The sub-buffer 112 outputs the data stored in the sub-buffer 112 to the reading side in response to the input of a signal requested from the data reading circuit 12 on the reading side. Since the shift register 110 checks whether or not the sub-buffer 112 is free and outputs data only when there is a free space, the data output timing of the sub-buffer 112 is synchronized with the shift register 110. There is no need to take. However, at this time, when the data read circuit 12 and the interface circuit 11 are asynchronous, a clock transfer circuit (not shown) is required to cope with different clock frequencies. The clock transfer circuit may be provided inside the interface circuit 11 or may be provided outside.

  A specific example will be described. FIG. 5 is a diagram illustrating an example of data in the shift register 110 and the flag bit shift register 111 when the interface circuit is operating. First, the state when data is written to R0 is as shown in (a). The data written here is 4 bits a0 to a3, and a0 to a3 are 0 or 1 bit data, respectively. At the same time as writing, the flag bit F0 corresponding to R0 is set to 1 to indicate that valid data is stored in R0.

  Next, shift processing of the shift register 110 and the flag bit shift register 111 is performed. The state after the shift process is performed once is as shown in (b). Furthermore, the state after the shift process is performed again is as shown in (c). Thereafter, when no new data is input, this operation is repeated.

  FIG. 6 is a diagram illustrating a data state of the shift register 110 and the flag bit shift register 111 when new data is input. When the data of a0 to a3 are stored in R4, the state when b0 to b3 are newly input to R0 is as shown in (a).

  Thereafter, shift processing of the shift register 110 and the flag bit shift register 111 is performed. The state after the shift process is performed once is as shown in (b). Furthermore, the state after the shift process is performed again is as shown in (c). Thereafter, when no new data is input, this operation is repeated.

  In this way, the shift process and data input are repeated. FIG. 7 is a diagram showing the data arrangement of the shift register 110 and the flag bit shift register 111 when the data a0 to a3 are shifted to R31. Assume that the result (a) of the shift process and data input is repeated.

  When the shift process is performed in this state, the register R31 holds the data a0 to a3 as it is without inputting new data. Other data is shifted to the next higher register. The result of the shift process is as shown in (b).

  After this, the shift process and data input are repeated, and each data is packed in the most significant register. FIG. 8 is a diagram illustrating an example of data states of the shift register 110 and the flag bit shift register 111 when data is stored in R28 to R31. Assume that the result (a) of the shift process and data input is repeated.

  At this time, since data is stored in all of R28 to R31, the sub-buffer 112 stores the data of R28 to R31 when the sub-buffer 112 is empty. When the sub-buffer 112 completes the data storage, the bits F28 to F31 of the flag bit shift register 111 become 0. The state at this time is as shown in (b).

  In the subsequent shift processing, since the bits F28 to F31 are 0, the data in the registers R28 to R31 are handled as empty. That is, the data states of the shift register 110 and the flag bit shift register 111 after the shift process is performed once more are updated with the shifted data as shown in FIG. .

  Next, a configuration when writing to the interface circuit is written in a plurality of words will be described. A circuit configuration in this case is shown in FIG. The interface circuit 11 in FIG. 18 has an interface circuit configuration in which writing to the interface circuit 11 is performed in units of a plurality of words and output to the data reading circuit is performed in units of one word. In order to cope with writing in a plurality of words, unlike the circuit configuration of FIG. 2, a sub-buffer 112 is prepared on the writing side. Here, for the sake of explanation, the configuration of the shift register and flag bit shift register is assumed to be as shown in FIG. 11, and the smaller number is called the lower level and the higher number is called the higher level.

  Note that the interface circuit 11 can also cope with writing in a plurality of words and reading in a plurality of words. In that case, subbuffers corresponding to the number of words to be written and the number of words to be read are prepared, respectively, and the others can be performed by performing the same circuit configuration and processing flow as in FIGS.

  Further, it is possible to prepare an interface circuit for transferring data in both directions, or to prepare an interface circuit for transferring data in the opposite direction separately from the interface circuit 11.

  FIG. 10 is a flowchart showing a processing flow of the interface circuit 11 in the present invention.

  First, the sub buffer 112 confirms the availability of the sub buffer 112 (S30). As a result of the confirmation, if there is an empty space in the sub-buffer 112, it is confirmed whether there is a write request (S31). If there is a write request, data is written in the sub-buffer 112 (S32).

  Next, the sub-buffer 112 checks whether data is stored in the sub-buffer 112 (S33). If data is stored in the sub-buffer 112 as a result of the confirmation, whether or not all of the registers R28 to R31 for the upper 4 words of the shift register 110 are free according to the values of F28 to F31 of the flag bit shift register 111. Is confirmed (S34). If all the upper 4 words are empty as a result of the confirmation, the data of the sub-buffer 112 is stored in the upper 4 words of the shift register 110 (S35). Further, in order to indicate that valid data is stored in these shift registers R28 to R31, F28 to F31 of the flag bit shift register 111 are set to 1 (S39).

  The shift register 110 sequentially performs shift processing in the lower register direction (S36). Since the data in the register of R0 cannot be shifted any further to the lower register, the shift process is performed on the data stored in the upper register from R1. The shift method of the shift register 110 is the same except that the shift direction of the contents described in FIG. 5 is changed from the upper level to the lower level, and the description is omitted here.

  When the shift process is completed, it is checked whether data is stored in R0 (S37). If the data is stored as a result of the confirmation, the data of R0 is output to the reading circuit 10 (S38). After outputting data to the read circuit 10, F0 is set to 0 (S40).

  In this way, the interface circuit 11 can transfer data between the data read circuit 10 and the data write circuit 12 having different transfer protocols.

  A specific example will be described. FIG. 11 is a diagram illustrating data in the shift register 110 and the flag bit shift register 111 when the interface circuit is operating. First, 4-word data is input to the sub-buffer 112, and the sub-buffer data is stored in the registers R28 to R31. The state at this time is (a).

  Each time a shift process is performed thereafter, the data in the shift register 110 is shifted to the lower register. The state shifted once from the state of (a) is (b), and the state shifted once more is (c). Since all the registers R28 to R31 are not empty in this state, even if data is input to the sub-buffer 112, the data in the sub-buffer 112 is not stored in the shift register 110, and the sub-buffer 112 is in a standby state.

  Thereafter, the shift process is repeated, and it is assumed that data is input to the sub-buffer 112 in the state of FIG. At this time, since all of the registers R28 to R31 are empty, the data of the sub-buffer 112 is stored in the registers R28 to R31. Since the shift process and the operation of storing the sub-buffer data in the shift register are performed simultaneously, the state after the data storage is (b).

  In this way, the shift process and data input are repeated. However, as shown in FIG. 13A, when it is not possible to shift any more, data is accumulated in order from the lower register without being shifted. Data is read from R0 in response to a request from the data read circuit 120. The reading here is performed in units of one word. FIG. 6B is a diagram illustrating an example of data in the shift register 110 and the flag bit shift register 111 when the interface circuit operates when data is read.

  When data is read from R0 to the data read circuit 120, the flag bit F0 indicating the storage state of the data of R0 is rewritten from 1 to 0. The state at this time is shown in FIG. If the shift process is performed in this state, since F0 is 0, it is treated as no data is stored in R0. Therefore, the state after the shift is (b).

  As described above, by providing the shift register 110 and the flag bit shift register 111 indicating the data storage state of each register, output data management can be performed without using the pointer control circuit. Since the circuit is unnecessary, it is possible to configure the circuit with a smaller area than in the past. Alternatively, by providing the sub-buffer 112 in addition to the shift register 110, it is possible to realize the configuration and control of the shift register 110 (FIFO circuit unit) without complicating when transferring in units of a plurality of words. .

Embodiment 2 of the Invention
In the first embodiment of the invention, it is possible to use an output data selector without using a sub-buffer. A configuration using the output data selector will be described below.

  FIG. 16 is a diagram showing the configuration of the interface circuit in the second embodiment of the present invention. The interface circuit 21 includes a shift register 210, a flag bit shift register 211, an output data selector 212, a pointer control circuit 213, and a shift operation control circuit 214.

  The shift register 210 includes a plurality of registers, and data is sequentially transferred between the registers. The shift register 210 here is a shift register that transfers data in units of words. The configuration of the shift register itself is the same as that of the first embodiment, and the only difference is that the output destination of the data in the upper register is not the sub-buffer 112 but the output data selector.

  The flag bit shift register 211 is composed of a plurality of flag bits, and data is sequentially transferred between the flag bits. Each bit of the flag bit shift register 211 corresponds to each register of the shift register, and indicates whether or not valid data is stored in the corresponding register by a flag bit. The configuration of the flag bit shift register 211 itself is the same as that of the first embodiment, except that the flag bit is cleared by the shift operation control circuit.

  The output data selector 212 outputs the data in the upper register of the shift register 210 to the SDRAM 22. Data is output by inputting an output data signal from the pointer control circuit 213 and sequentially outputting the data of the connected upper register based on the input signal.

  The pointer control circuit 213 outputs to the output data selector 212 a pointer signal that indicates which register among the registers in the shift register 210 connected to the output data selector 212 is to output data.

  The shift operation control circuit 214 performs clear control of the flag bit shift register 211 corresponding to the upper register of the shift register 210. The clear control is performed after the reading process is completed based on a signal input from the pointer control signal.

  Next, the flow of processing when the interface circuit 21 operates will be described. FIG. 18 is a flowchart showing a process flow of the interface circuit 21 according to the second embodiment of the present invention.

  First, shift processing of the shift register 210 is performed (S40). The shift register 110 shifts the stored data at a predetermined timing. The timing for shifting is determined by the operation clock of the shift register. Since the shift method is the same as that of the first embodiment, the description thereof is omitted here.

  When the shift of the shift register 210 is completed, it is determined whether or not there is data input (S41). If there is data input as a result of the determination, the input data is stored in R0 of the shift register 210 (S42). At this time, F0 of the flag bit shift register 211 becomes 1 because data is entered. If no data is input, the register R0 is empty. At this time, F0 of the flag bit shift register 211 becomes 0 because data is entered.

  When the shift processing of all the registers of the shift register 210 is completed, it is determined whether or not data is stored in the upper 4 words, that is, all the registers from the 28th to the 31st (S43). The determination at this time is made by determining that all the flag bit shift registers 211 are set to 1.

  As a result of the determination, if data is stored in the upper 4 words of the shift register 210, the pointer control circuit 213 outputs a readable signal to the data read circuit 220 (S44). The pointer control circuit 213 confirms whether or not a read request signal is input from the data read circuit 220 (S45). When the read request signal is input, the pointer control circuit 213 shifts the output register from the output data selector 212 to the data read circuit 220. The data of the upper 4 words of 210 is output.

  The output of data is performed by the output data selector 212 sequentially selecting the upper four words of data R28 to R31 of the shift register 210 and outputting them to the data read circuit 22. Which register data is output at which timing is determined by a signal output from the pointer control circuit 213 to the output data selector 212.

  With such a configuration, a pointer control circuit is not required when data is written from the data write circuit 200 to the shift register 210 at the time of data write, so that the circuit configuration can be simplified.

It is a figure which shows the structure of the DVD apparatus in this invention. It is a block diagram which shows the structure of the interface circuit in this invention. It is a figure which shows the structure of the shift register in this invention, a flag bit shift register, and a subbuffer. It is a flowchart which shows the flow of a process of the interface circuit in this invention. It is a figure which shows an example of the data of the shift register at the time of the interface circuit operation | movement in this invention, and a flag bit shift register. It is a figure which shows an example of the data of the shift register at the time of the interface circuit operation | movement in this invention, and a flag bit shift register. It is a figure which shows an example of the data of the shift register at the time of the interface circuit operation | movement in this invention, and a flag bit shift register. It is a figure which shows an example of the data of the shift register at the time of the interface circuit operation | movement in this invention, and a flag bit shift register. It is a figure which shows an example of the data of the shift register at the time of the interface circuit operation | movement in this invention, and a flag bit shift register. It is a flowchart which shows the flow of a process of the interface circuit in this invention. It is a figure which shows an example of the data of the shift register at the time of the interface circuit operation | movement in this invention, and a flag bit shift register. It is a figure which shows an example of the data of the shift register at the time of the interface circuit operation | movement in this invention, and a flag bit shift register. It is a figure which shows an example of the data of the shift register at the time of the interface circuit operation | movement in this invention, and a flag bit shift register. It is a figure which shows an example of the data of the shift register at the time of the interface circuit operation | movement in this invention, and a flag bit shift register. It is a figure which shows the structure of the DVD apparatus in this invention. It is a block diagram which shows the structure of the interface circuit in this invention. It is a flowchart which shows the flow of a process of the interface circuit in this invention. It is a figure which shows the structure of the shift register in this invention, a flag bit shift register, and a subbuffer. It is a block diagram which shows the structure of the interface circuit in a prior art.

Explanation of symbols

1 DVD device 10 control circuit 100 data writing circuit 11 interface circuit 110 shift register 111 flag bit shift register 112 sub-buffer 12 SDRAM
120 Data Read Circuit 13 DVD Read Circuit 2 DVD Device 20 Control Circuit 200 Data Write Circuit 21 Interface Circuit 210 Shift Register 211 Flag Bit Shift Register 212 Output Data Selector 213 Pointer Control Circuit 214 Shift Operation Control Circuit 22 SDRAM
220 data read circuit 23 DVD read circuit 30 control circuit 300 data write circuit 31 interface circuit 310 shift register 311 pointer control circuit 312 output data selector 313 pointer control circuit 314 shift operation control circuit 32 data read circuit 320 data read circuit

Claims (18)

An interface circuit that interfaces data transfer between different circuits,
M (where, M is 2 or more is a natural number) a register consisting of bits N (where, N is the 2 or more a natural number) provided, the data transferred between the different circuit input, between the register A shift register for sequential transfer,
A register storage state data holding circuit for holding data indicating whether or not the stored data of each of the N registers is valid ,
The shift register includes the number of bits of input data to the shift register (the number of bits of the input data is a value obtained by multiplying the M by a natural number of 1 or more) and the number of bits of output data of the shift register ( The number of bits of output data is an input / output operation under the condition that M is a value obtained by multiplying M by a natural number of 1 or more) . A part of the N registers included in the shift register functions as an output data storage register that outputs transfer data;
When the output data storage register stores transfer data in all its registers , and the register storage state data holding circuit indicates that the transfer data stored in all the registers is valid, Output the transfer data,
The interface circuit according to claim 1. The register storage state data holding circuit includes a plurality of flag registers,
Each of the plurality of flag registers corresponds to each register of the shift register, and stores flag data indicating whether or not the data stored in the corresponding register is valid.
The interface circuit according to claim 1 or 2.   The interface circuit according to claim 3, wherein the plurality of flag registers sequentially transfer the stored flag data between the flag registers in response to the sequential transfer operation of the shift register. The plurality of flag registers sequentially transfer data from the flag register on the data input side to the flag register on the data output side,
For each flag register, determine whether or not the flag data stored in the flag register can be transferred to the flag register adjacent to the output side of the flag register. 4. The interface circuit according to claim 3 , wherein the stored flag data is transferred to a flag register adjacent to the output side of the flag register. Said shift register, said sequential corresponding to the transfer operation of the plurality of flag registers, the interface circuit of claim 5, the data that the stored sequentially transferred between registers.   The plurality of flag registers determine whether or not the flag data stored in the flag register for each flag register can be transferred to an adjacent flag register on the output side of the flag register. The interface circuit according to claim 5, wherein the interface circuit is obtained by a logical product of all the flag registers.   The interface circuit according to claim 2, further comprising an output data selector that outputs data selected from the output data storage register to the outside. The interface circuit includes a shift operation control circuit that rewrites the information in the corresponding flag register from information in which the data is valid to information in which the data is invalid in accordance with data output from the output data selector. the interface circuit of claim 8,. An interface circuit that interfaces data transfer between a first circuit and a second circuit,
A first storage unit having a plurality of storage areas for sequentially storing a data string composed of a predetermined number of bits input from the first circuit ;
A second storage unit that stores a plurality of flag bits in which a flag is set when the corresponding storage area stores valid data corresponding to each of the plurality of storage areas;
When the flag is set in all of the predetermined flag bits of the second storage unit, the plurality of data strings stored in the storage unit corresponding to the predetermined flag bit are read and the second A sub-buffer that outputs to the circuit of
An interface circuit comprising: Said first and said second storage unit is a shift register, the first storage unit sequentially transfers the data string input from said first circuit to the upper direction from the lower between the storage area 11. The interface circuit according to claim 10, wherein the predetermined flag bit is the upper N bits (where N is a natural number equal to or greater than 2) of the second storage unit . 12. The interface according to claim 11, wherein the sub-buffer outputs the N data strings to the second circuit in response to an operation clock different from the operation clock of the first storage unit. circuit. 12. The plurality of registers included in the first storage unit connected to the sub-buffer input data from the sub-buffer on condition that data is stored in the sub-buffer. Interface circuit described in 1. The shift register included in the second storage unit, in response to sequentially transfer operation of the shift register included in the first storage unit sequentially transfers the data that the store between registers, The interface circuit according to claim 11 . The shift register included in the second storage unit sequentially transfers the data from the data input register in the direction of the data output side of the register,
The information about each register is stored in those 該Re register determines whether it is possible to transfer to an adjacent, Relais register on the output side to those 該Re register, if it is possible as a result of the judgment those 該Re register the interface circuit of claim 11, wherein the transfer of information stored in the Relais register to adjacent the output side to those 該Re register to. The shift register included in the first storage unit, in response to sequentially transfer operation of the shift register included in the second storage unit sequentially transfers the data stored between registers, wherein Item 16. The interface circuit according to Item 15 . Said second of said shift register included in the storage unit, each for registers in the flag data stored in those 該Re register whether it is possible to transfer to an adjacent, Relais register on the output side of this 該Re register the interface circuit according to claim 15 or 16 determines, and performs a logical product of the output-side near Relais register all than those 該Re register. An optical disc apparatus for processing data read from an optical disc by a control circuit,
In the data transfer of the read data, the optical disc apparatus having an interface circuit according to any one of claims 1 to 17 performs interface processing for the control circuit.

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