JPS63146095A - Character display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a single character display device, and more particularly to a display control section of a character display device.

BACKGROUND OF THE INVENTION Conventionally, this type of device has been constructed of blocks as shown in FIG.

The microprocessor 401 is a microprogram execution unit, the memory 402 is a microprogram and data storage unit, and the interface control unit 403 is a unit that controls an iterative interface with a host device.

The character frame buffer 404 is a part that stores display character patterns, and is a part that stores display attribute information of the display character pattern.

The dot shifter 406 is a part that converts the display character pattern information read from the character frame buffer 404 into pixel serial information, and the ATR register 407 is a part that converts the display character pattern information read from the character frame buffer 404 into pixel serial information.
This is a part that temporarily buffers the display attribute information read from the R frame buffer 405.

The ATII control circuit 408 is a part that generates a video signal with display attributes taken into consideration by taking the logic between the output of the dot shifter 406 and the output of the ATR register 407, and the display synchronization circuit 410 is a part that generates a video signal with display attributes added.
The CR7 display section 409 controls display readout of the ATR frame buffer 405 and generates synchronization signals for CRT display.
The deflection is controlled by the synchronization signal provided from the ATR.
This is the part that displays the video signal output by the control circuit 408 on the cathode ray tube.

Problems to be Solved by the Invention However, in the conventional technology described above, although display attribute information is given for each character, exactly the same information is stored in the attribute frame buffer corresponding to all raster lines in the row. It is necessary to do so, and for that purpose,
This has the disadvantage of unnecessarily reducing drawing performance.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel character display device that makes it possible to eliminate the above-mentioned drawbacks inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, the display control section in the character display device according to the present invention stores a character frame buffer that stores one character display information and display attribute information of one display character pattern. A video whose display attributes are added by logic between an attribute frame buffer, a line/line register that sets the number of line rusks per line, read information from the character frame buffer, and read information from the attribute frame buffer. an attribute control circuit that generates a signal, and controls display reading of the character frame buffer and attribute frame buffer according to the settings of the line/row register;
The display synchronization circuit is configured to include a display synchronization circuit that generates a synchronization signal for RT display.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a character display device according to the present invention.

Referring to FIG. 1, a microprocessor 101 is a microprogram execution unit, a memory 102 is a microprogram and data storage unit, and an interface control unit 103 is a unit that controls the interface with a host device. be. That is, the microprocessor 101
By executing the microprogram, display information from the host device is developed into display character patterns and display attribute information, and these are stored in a character frame buffer 104 and an attribute (ATR) frame buffer 105, respectively.

The character frame buffer 104 is a memory that stores display character patterns, and the attribute (ATR) frame buffer 105 is a memory that stores display attribute information. A capacity of M×N bits is required.

The dot shifter 106 converts the read information of the character frame buffer 104 into pixel serial information.
The attribute (ATR) register 107 is a register that temporarily buffers read information from the ATR frame buffer 105.

The attribute (ATR) control circuit 108 is a part that generates a video signal with display attributes taken into consideration by calculating the logic between the output of the tonoton lid 106 and the output of the ATR register 107.

The line/row register 111 is a register for setting the number of raster lines per line, and the 1 display amount period circuit 110 controls display reading of the character frame buffer 104 and ATR frame buffer 105 according to the settings of the line/row register 111. It is also a part that generates synchronizing signals for CRT display.

The CItT display section 109 is deflection-controlled by a synchronization signal output from a display synchronization circuit, and ATI'! Control circuit 10
This is the part that displays the video signal output by & on the screen on the cathode ray tube.

FIG. 2 shows the correspondence between the character frame buffer 104 and the ATR frame buffer 105.

That is, the display character pattern stored in the character frame buffer 104 is displayed on the screen with the display attribute stored at the same address in the ATR frame buffer 105. Display attributes are given in units of 8 pixels.

FIG. 3 shows the display readout operation of the display synchronization circuit 110 when the set value to the line/row register 111 is n, using a relationship diagram between the character frame buffer 104 and the ATR frame buffer 105.

That is, when the set value to the line/row register 111 is n, the Y-direction read address of the ATR frame buffer 105 is fixed for n raster lines.

As described in detail, according to the present invention, the display readout operation of the attribute frame buffer of the display synchronization circuit is controlled according to the number of raster lines per line set in the line/row register, that is, n raster 9427 In the case of rows, by fixing the Y-direction read address of the attribute frame buffer for n raster lines, it is possible to eliminate unnecessary drawing to the attribute frame buffer and improve drawing performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a character display device according to the present invention. 101, , microprocessor, 102. ,
, memory, 103. , ,Interface control section, 1
04. , . Character frame buffer, 105. , , ATR frame buffer, 106. , , Dot Shifter, 10
7. , , ATR register, 108. , , A
TR control circuit, 1091. , CRT display section, 110
．． , , display synchronization circuit, tii, , , line/
The line register in Figure 2 is the character frame buffer 104°ART in Figure 1.
3 is a correspondence diagram of frame buffers 105. FIG. Figure 3 shows the display synchronization circuit 11 in the case of 9427 rows of n rasters.
0 read operation to the character frame buffer 104, ATR.
This is shown in a relational diagram of the frame buffer 105. FIG. 4 is a block diagram of a conventional character display device. 401, , microprocessor, 402. ,
, memory, 403. , ,interface control section,
404. , .

Claims (1)

[Claims] A character frame buffer that stores character display information, an attribute frame buffer that stores display attribute information of a display character pattern, a line/row register that sets the number of raster lines per line, and a character frame buffer that stores display attribute information of a display character pattern; an attribute control circuit that generates a video signal with display attributes taken into account by performing logic between the read information of the frame buffer and the read information of the attribute frame buffer; A character display device comprising: a display control section; and a display synchronization circuit that controls display reading of a buffer and an attribute frame buffer and generates a synchronization signal for CRT display.