JPS61260291A - Character graphic display circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a character/figure display circuit, and more particularly to a character/figure display circuit suitable for efficient use of memory and high-speed display.

[Background of the invention]

: For example, as a display processing circuit on the edge side of a text/graphic information transmission system using broadcast radio waves or telephone lines,
As described in Japanese Patent No. 0-4988, an image display circuit has been proposed which can perform both prop recoloring display and dot unit coloring display using the same memory. However, in this conventional example, the display memory capacity when the foreground color and background color information is specified for each pixel block,
The display memory capacity is the same as when color is specified in units of pixels and dots, and even when only coloring is performed in blocks, such as in teletext broadcasting, the display memory capacity is the same as in the case of coloring in units of dots. Requires. In other words, originally one piece of color information per block is sufficient, but in the conventional example described above, an extra piece of color information is required for the number of lines in one block, and this increase in display memory causes an increase in the cost of the entire terminal device. It became.

In addition, in the conventional example, since the display period uses the data bus of the display memory only for display reading, writing of character and graphic information to the display memory has to wait during the non-display period 1, making high-speed display impossible. .

[Object of the Invention] The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to eliminate the need for a storage area for color information specified for each block in a display format that performs color display in units of blocks such as teletext. An object of the present invention is to provide a character/figure display circuit capable of displaying text/figures at high speed without increasing the number of characters.

[Summary of the invention]

In order to achieve the above object, the present invention includes a display address for reading out character and graphic information recorded in the display memory in synchronization with display scanning, and an MPU in the address supply part of the display memory.
An address correspondence switching means is provided for switching the mutual address bit correspondence with the MPU address for writing character and graphic information into the display memory, and the display readout period is time-divided into a period for reading out pattern information and a period for reading out color information. , a specific bit of the MPU address is switched in each read period, and in the MPU write period, a specific bit of the MPU address is switched by an area selection signal that selects a pattern information area and a color information area, and is stored in the display memory. It is characterized by supplying an address.

[Embodiments of the invention]

The present invention will be explained below with reference to the drawings.

In FIG. 1, 1 is a micro gummy processor (abbreviated as MPU), 2 is a display address generation circuit, 3 is a display mode setting register, 4 is an MPU address register, 5 is a display area selection address decoder, and 6 is a display memory address. a generation circuit; 7 a display memory; 8 a bidirectional data control circuit;
9 is a data latch, 10 is an image data synthesis circuit, and 11 is a display device.

Further, FIG. 2 is a timing diagram of each signal appearing on the main signal lines shown in FIG. 1.

Below is the character/graphic display shown in Figure 1! ! The operation of the device will be explained in detail. In FIG. 1, the display address generation circuit 2 not only generates the display address signal (e) but also
The MPU clock signal (a) shown in Figure 2 and the display
Generates timing signals such as I/(d). , MPU
1 is operated by the MPU black signal (a) output from the display address generation circuit 2, and when writing character/graphic information to the display memory 7, the signals shown in FIG. Output the MPU address and MPU data as shown in C). MPU clock signal (a
) is an cycle signal (d
) Since the MPU address and MPU data cannot be directly supplied to the display memory 7, they are held in the MPU address register 4 and the data register of the bidirectional data control circuit B.

On the other hand, the display address (e) is generated by the optical display address generation circuit 2 during the display period of the display cycle signal (d) shown in FIG. 2, and the period is divided into four to output four addresses. For example, in a teletext display, the number of display pixels as shown in Figure 3 is 256 dots in the horizontal direction and 1 dot in the vertical direction.
With 92 lines, the size of the colored block is 4 dots horizontally and 4 dots vertically.
When displaying blocks of dots in color, the foreground color information (■) specifies the color when the pattern is 111, and the color when the pattern is 10' in the pattern information according to the MPU address assignment of the display memory shown in Figure 4. The background color information (■) that specifies the background color information, and the display attribute information (■) such as flashing and concealment (concealing) are shown in ■, respectively, in Figure 2 (e).
■、■.

Occurs at the timing of and ■. If a relatively low-line dynamic memory is used as the display memory lJ7, this continuous display address is divided and multiplexed into row-direction addresses and column-direction addresses and supplied, but following one row-direction address, By using a so-called page mode in which only four column-direction addresses are supplied, the display read period can be shortened and the remaining period can be allocated to the MPU data write period. This eliminates the need to wait until the non-display period for the MPU to refine the display data, and only requires one display cycle period at most, making it possible to significantly improve the MPU display speed.

The display memory address generation circuit 6 switches between the MPU address (f) output from the MPU address register 4 and the display address (e) output from the display address generation circuit 2 using the display cycle signal (d) shown in FIG. ,
In addition, during the display period, the display address for reading out the four display areas is switched in each display readout period, and during the MPU period, the MPU address from the MPU address register 4 is switched by the area selection signal of the display area decoder 5, and the display and a circuit that changes bit correspondence between addresses of the MPU and supplies the changed bit correspondence to the display memory 7.

Further, the data latch circuit 9 receives foreground color information (2) of the pattern information read out during the display period.

This circuit stores character and graphic information of background color information (■0) and display attribute information (2) in synchronization with the cycle signal (d) for displaying. The stored character and graphic information is synthesized by an image data synthesis circuit 1o as image data matching the cycle cycle to be displayed, and is supplied to a display device 11 such as a cathode ray tube to display the character and graphic information. This shows an example of the correspondence between the display address and the MPU address in the colored display mode, when pattern information is drawn (A) and when color information such as the foreground color and background display attributes is read (CB). The relationship between rivers and rivers is different.

In other words, in the case of pattern information, the MPU address corresponds to the horizontal and vertical display address signals incrementing by one address, and in the case of color information, the MPU address is the same for only 4 lines that are the same colored block. The lower two bits of the address of the vertical display address signal are removed to correspond to the MPU address. In this way, color information such as foreground color and background color 1 display operation information can be read out in a display memory area that is 1/4 of that of pattern information, and the display memory capacity used can be reduced.

Next, a specific circuit configuration of the display memory address generation circuit 6 will be explained.

FIG. 6 is a diagram showing an example of a specific circuit configuration of the address generation circuit 5 shown in FIG.
are respectively address switching circuits. The table below shows the bit correspondence between the display address and the MPU address with respect to the address input of the display memory 7.

In the margin of FIG. 6 below, the address switching circuit 61 is shown in FIG.
), the display memory is activated by four display period signals: display address ■ for reading out the pattern information area, and display addresses ■, ■, and ■ for reading out the respective information areas for foreground color and background color 9 display complementarity. This is a circuit that generates a display address by switching a part of the display address supplied to 7.
As shown in the table, the addresses supplied to three bits of the column-direction addresses of the display memory 7 are switched. Further, the address switching circuit 62 is connected to the display area decoder 5 which selects the respective memory areas of the foreground color information area (2) and the background color information area (0) of the pattern information area, as shown in FIG.
A part of the MPU address is switched by the output signal of M
This circuit generates a PU address, and as shown in the table, switches the upper 9 bits of the MPU address and supplies it to each address bit of the display memory 7. The address switching circuit 63 is a circuit that switches the display address and MPU address generated by switching between the address switching circuit 61 and the address switching circuit 62, respectively, using the display cycle signal (d) shown in the timing diagram of FIG. The switching circuit 64 supplies the display address of the display period and the MPU address of the MPU period switched by the address switching circuit 63 to the display memory 7 using a dynamic memory, so that the switching circuit 64 performs switching to divide the address into a row direction address and a column direction address. It is a circuit.

According to the configuration of the address generation circuit 6, even if a dynamic memory is used as the display memory 7, when display reading is performed, only the column direction address is switched in four read periods, and the row direction address is kept the same. Therefore, a so-called page read mode in which only one row direction address and four column addresses are supplied can be used, and the correspondence between display addresses and MPU addresses as shown in FIG. 5 can be established, and the pattern Regarding information, the MPU address increases by 1 address for each display scan, and for color information such as foreground color and background color9 display attributes, 4 lines of the same colored block have the same MPU address and the color information is displayed. The amount of pattern information that takes up memory space can be reduced to 4.

As explained above, according to this embodiment, a low-mounted dynamic memory can be used as the display memory, reducing costs.Furthermore, compared to the display memory capacity used for conventional block coloring display, the color information memory You can make the area /4. Furthermore, by using the page read mode of the dynamic memory, the display period can be shortened, and by using the remaining display cycle period as a data writing period by the MPU, the display processing speed can be significantly increased compared to the conventional method.

In this embodiment, the size of the block is limited in the case of block coloring, but the bit correspondence between the display address and the MPU address may be changed depending on the size of the block.

〔Effect of the invention〕

According to the present invention, the display memory usage area for color information in block coloring display can be reduced by the thickness of the coloring program compared to the display memory usage area for pattern information, and the same can be achieved with a smaller display memory.

Anhydrous water can be achieved. Further, by using a dynamic memory, the cost of the display memory can be reduced, and the processing speed for writing character and graphic information to the display memory can be greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the character/figure display circuit according to the present invention, FIG. 2 is a timing diagram showing the timing relationship of each signal appearing on the main signal lines shown in FIG. 1, and FIG.
The figure shows an example of a display screen for block coloring display, Figure 4 shows an example of display memory address allocation in block coloring display, and Figure 5 (A) and (B) shows an example of address switching generation. The diagram shown in FIG. 6 is the address generation circuit 6 shown in FIG. 1.
FIG. 2 is a block diagram showing an example of a specific circuit configuration. 1...Microprocessor, 2...Display address generation circuit, 5...
Display mode setting register, 4...MPU address register, 5...Display area selection address decoder, 6...Display memory address generation path, 7
... Display memory, 8... Bidirectional data control circuit, 9°°°°°° de-clutch circuit, 10... Image data synthesis circuit, 11...・・・
・Display device, 61.62, 65.64...address switching circuit.

Claims (1)

[Claims] A memory having an area for storing first character and graphic information and an area for storing second character and graphic information; and character and graphic information write control for controlling writing of first and second character and graphic information separately to the memory. means, character/graphic display readout control means for reading first and second character/graphic information from the memory in synchronization with a display scanning cycle; and first and second character/graphic figures read by the character/graphic display readout control means. In a character/figure display circuit comprising an image synthesis conversion means for synthesizing and converting information into an image signal, the character/figure information whose writing is controlled by the text/figure writing control means is transferred between a first character/figure information area of the memory and a second character/figure information area of the memory. Display area discriminating means for determining in which area of the text/figure information area the text/figure information is written; and text/figure display so that the figure information read from the memory is time-divided into first and second text/figure information. A means for controlling the reading control means, and switching a specific bit of the memory write address from the character/figure writing control means based on an area discrimination signal from the display area discrimination means, and a time division signal from the time division reading means. A character/figure display circuit comprising address bit correspondence conversion means for switching a specific bit of a display readout address from a character/figure display readout control means to exchange address bit correspondence between a write address and a display readout address.