JPS6314546B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a facsimile device, and more particularly to a facsimile device using a microcomputer. Recent advances in integrated circuit technology have led to remarkable progress in microcomputers, and microcomputers that are small, have large storage capacities, and are capable of high-level arithmetic processing can now be obtained at very low prices. For this reason, microcomputers have permeated every field, and microcomputers have come to replace parts of facsimile machines that were conventionally made up of dedicated hardware. However, microcomputers currently have a limit to their arithmetic processing speed, and the hardware section that performs high-speed processing has the disadvantage that it cannot be replaced. On the other hand, since encoding processing in a facsimile device requires processing for each bit, a high processing speed is required. Therefore, in all of the facsimile machines that have been developed so far that use microcomputers, the parts that require high-speed processing are constructed with dedicated hardware, and the microcomputer is used exclusively as an auxiliary means for that hardware. However, the functions of microcomputers could not be fully utilized. For example, Figures 1a and 1b show block diagrams of conventional facsimile machines that use microcomputers. It was only used to sequence the hardware through an interface circuit. Therefore, even if a facsimile device is constructed using common items that can be used on both the transmitting and receiving sides, there are many components such as memory such as shift registers or random access memory, counters, many gate circuits, and flip-flops for timing control. A buffer device consisting of the following is required. When carrying out the protocol, delay circuits, flags, error check code generators and detectors, numerous counters, flip-flops, shift registers, A communication control device consisting of a gate circuit, etc. is required. At the time of transmission, a counter for counting run length, a flip-flop and exclusive OR circuit for detecting change points to detect run breaks, read-only memory for selecting an encoding code according to the run length, and read-only memory for selecting an encoding code according to the run length. FIFO (first-in, first-out) for temporarily storing output from memory and adjusting speed with line rate
Buffer memory, a counter for transferring the encoded code to the FIFO buffer memory, a counter for generating FILL bits for correcting the minimum transmission time when the compression rate is high, and a large number of flip-flops for controlling the clocks required at that time. A coder device consisting of a gate circuit is required. FIFO buffer memory for speed conversion of received image data input from the communication control device during reception;
To remove EOL (synchronization) codes, FILL bits, etc. from received image data, a detection circuit to detect them, a shift register and bit counter to extract the encoded code, and a run length binary value corresponding to the encoded code are installed. Read-only memory for selection, run length counter for transferring the number of bits of run length according to the run length binary value to the next stage buffer device,
A decoder device consisting of a cumulative counter for counting the number of bits for one line and detecting errors, a large number of flip-flops for controlling the necessary clocks, and a gate circuit is required. In this way, in conventional facsimile devices, only a very limited part such as the system controller is replaced with a microcomputer, and the majority of the device has to rely on random logic and hard wiring. However, the disadvantage is that the device is large and expensive. The present invention has been made in view of the above points, and it is possible to reduce the size and cost by leaving only the minimum necessary hardware such as a scanner, plotter, and modem in a facsimile device and replacing all other hardware with a microcomputer. The purpose is to provide facsimile equipment. In order to achieve this object, the present invention includes an image information input section that converts serial pixel data into parallel pixel data for each predetermined bit, and an image information input section that converts serial encoded data into parallel encoded data for each predetermined bit. The present invention is characterized in that it is provided with a transmitting/receiving information input/output section capable of transmitting and receiving information, and is configured so that a microcomputer can perform encoding and/or decoding processing in units of predetermined bits. An example of the present invention will be described below, but before that, the characteristic points of this example will be listed. That is, its characteristic points are as follows. (1) After the reading device reads the calligraphic information, a microcomputer performs everything from counting the run length to encoding and forming the data transmission format. (2) The received data is transferred to the microcomputer via the bus, and the subsequent steps from decoding the received data to converting it to pixel data and transferring the data to the recording device are performed by the microcomputer. (3) A microcomputer is used to blink the document illumination light source in the reading device, stop the document scanning mechanism, and start and stop the modem and/or network control device. (4) The protocol for handshaking with the other device and the mode setting of the own device are now performed by a microcomputer. (5) The microcomputer is used to notify the other device of its own functions and/or to set the mode of the other device. (6) A microcomputer is used to detect errors in the received calligraphy data and to process the calligraphy information of the line where the error occurred. (7) Driving the recording paper conveyance device in the recording device;
The point is that the stop and recording timing are controlled by a microcomputer. (8) A microcomputer is used to blink the display lamp on the operation unit and accept operation signals. (9) All of the above operations can be performed with a single computer by allocating the time used to perform the above operations on the microcomputer. (10) When transferring data from the reading device, the data transfer is completed in a shorter time than the image integration time of the image sensor, making it possible to follow the maximum speed of the microcomputer. (11) The preprocessing of the image signal is performed on multiple bits at the same time. (12) In order to encode the image signal in a short time, the first step is to detect the change point of multiple bits at once. (13) When the above change point is subsequently detected, the detection is switched to one bit at a time. (14) During operation, chattering of the operating switch is prevented and the operating signal is reliably input to the microcomputer. In this embodiment, the interface, microprocessing unit, read-only memory, and random access memory are configured using Intel's 8212, 8085, 8316, 8101A4, etc., but the invention is of course limited to these. Needless to say, it is unnecessary. Hereinafter, embodiments of the present invention will be described in detail with reference to FIG. 2 and the subsequent drawings. FIG. 2 shows a system block diagram of the entire facsimile apparatus according to the present invention, in which is a document reading section that reads a document during transmission and outputs an image signal, and a microcomputer that encodes the image signal. In order to enable high-speed processing, this is an image information input section that converts the serial pixel data output from the document reading section into parallel pixel data of every 8 bits and inputs it to the microcomputer. 1 is a received image output section that outputs an image signal decoded by a microcomputer at the time of reception to a received image recording section, and 1 is a received image recording section that obtains a copy of an original. Microcomputer (hereinafter referred to as μ-
The COM) consists of a microprocessing unit section, a timing generation section, a control program storage section, and an information storage section, and performs tasks such as encoding and decoding image information and controlling each section, which will be described later.
When transmitting, it serially converts the parallel data encoded by μ-COM every 8 bits and outputs it to the modem, while when receiving it converts the encoded serial data input from the modem to parallel data every 8 bits. This is an input/output unit for transmitting and receiving information that is input to μ-COM. Of course, this transmission/reception information input/output section inputs and outputs necessary data when performing protocols and the like in addition to inputting and outputting image data. and XI are control signal input and output sections, which input signals from the original reading section, received image recording section, modem, network control section, and operation display section to μ-COM, while also inputting signals from the μ-COM to predetermined control signals. This is the part that outputs signals to each part. The facsimile apparatus of this embodiment is roughly constructed as described above, and next, the specific construction and operation of each of the above-mentioned parts will be explained in sequence with reference to FIG. 3 and subsequent drawings. In addition, modem, network control section,
As the operation display section, a conventionally known one may be used, and since it is not directly related to the present invention, its details will be omitted. Furthermore, in the following explanation, buses and signal lines are generally expressed in uppercase letters, and signals appearing there are expressed in lowercase letters. Original reading section (see Figure 3) The one-dot chain line in Figure 3 is the original reading section, and the PM
is a pulse motor for sub-scanning the document,
R is a document conveyance roller driven by the pulse motor PM, _L1 is a light source for document detection, _L2 is a light source for document illumination, and SL1 and SL2 are document detectors. The operator manually or with the document feeder,
When a document is inserted into the document receiving slot in the direction of the arrow, the document detector SL1 is activated. μ-COM regularly monitors the status of detector SL1, so when SL1 is activated, it outputs a lighting command to the document illumination light source drive circuit via the control signal output section XI, which will be described later, and lights the light source _L2. Along with lighting up the
A drive signal is output to the pulse motor drive circuit to rotate the pulse motor PM. When the pulse motor PM rotates, the transport roller R
starts rotating and transports the original in the direction of the arrow. When the leading edge of the document reaches the detector SL2 position, the detector
SL2, via a control signal input section to be described later,
Inform μ-COM of this. The μ-COM temporarily stops the pulse motor PM and then switches to sub-scanning feed during the reading scan. The original image is contact glass CG, mirror M,
An image is formed on the image sensor IS via the lens l. The image sensor IS receives an element clock elck from the image information input section under the control of μ-COM.
and a row synchronizing pulse ss are input, and the video signal outputted in synchronization with the clock is serially input one bit at a time to the image information input section via an amplifier A and a binarization circuit B. Image information input section (see Fig. 4 a, b) The image information input section includes a counter CT1 and a shift register SR, as shown in the dashed line in Fig. 4 a.
1. Consists of tri-state buffer TB,
The serial pixel data output from the binarization circuit B is converted into parallel pixel data of every 8 bits, and is output onto data buses _D0 to _D7 , which will be described later. Generally, when converting serial pixel data into parallel data, there is a method of using two shift registers and taking out the parallel pixel data from the other while inputting the serial pixel data to one of them, but in this example, μ-COM converts the parallel pixel data. Since the clock speed is set so that the shift register is filled with the next pixel data within the data processing time, only one shift register is used as shown. Counter CT1 outputs eight element clocks elck when the read strobe rso, which will be described later and is output from μ-COM, is input, so
It consists of a synchronous 4-bit binary counter that can be preset. When the logic "1" is input to the L terminal of the counter CT1, the clock input to the CP terminal is
Counts up at the rising edge of clk. Further, when the L terminal input is logic "0", the output terminals Q〓, Q〓, Q〓, Q〓 are set to the logic input to the α, β, γ, and δ terminals. Furthermore, when "0" is input to the R terminal, it is reset asynchronously with the clock clk input. From the _C0 terminal, all Q〓～Q〓 outputs are “1”, that is,
When the hexadecimal number F is reached, "1" is output. The C ₀ output and the 〓 output are input to the L terminal of the counter CT1 via a NOR gate. Therefore, when the value of counter CT1 becomes 0 to 7 and 16 value number F,
The L terminal input becomes "0". Also, set terminal α,
β is always 0, Qc output is input to the γ terminal, and output is input to the δ terminal. Therefore, when the value of counter CT1 is 4 to 7 or hexadecimal number C to F, the γ terminal input is "1", the δ terminal input is "0", and when the value of counter CT1 is 0 to 3 or 8 to 13 , γ terminal input is “0”, δ
The terminal input becomes "1". From these things, when the value of counter CT1 is 4 to 7 and F, it becomes 4,
In addition, when the value of counter CT is 0 to 3, it is set to 8 respectively.
It is set at the rising edge of the next clock clk input to the CP pin. The Q〓 output of the counter CT1 is input to an AND gate to control generation and stop of the element clock elck and shift clock sfck. Shift register SR1 consists of an 8-bit serial input/parallel output shift register. The tristate buffer TB outputs the 8 bits of data shifted into the shift register SR onto each of the 8 data buses D ₀ to D ₇ of the microcomputer while the read strobe rs ₀ is active. Next, the operation will be explained with reference to the time chart of FIG. 4b. Read strobe rso (negative pulse) from μ-COM
is output, this pulse is transmitted to the signal line described later.
Input to the G terminal of the tri-state buffer TB in the image information input section via rso, and shift register SR.
1 contents in parallel to 8 data buses D ₀ to _{D 7}
Output on top. At the same time, it is also input to the R terminal of the counter CT1, and the counter CT1 is reset at the fall of the read strobe rso. The parallel pixel data output on the data bus is taken into the μ-COM accumulator. Incidentally, the timing at which the read strobe rso is generated at this time is arbitrary, and its pulse width may also be arbitrary. Also, the period of the clock clk is μ−
If at least 9 clocks do not occur after COM captures pixel data by outputting read strobe rso and then outputs read strobe rso to capture the next pixel data, 8-bit pixel data will be stored in shift register SR1. However, as long as 9 clocks or more are generated during this period, the period may be arbitrary. By resetting counter CT1,
The output of Q〓～Q〓 is "0000". As a result, the L input becomes "0", the α to δ inputs become "0001", and then the clock clk becomes the counter CT.
When inputted to 1, the Q〓 to Q〓 outputs are set to ``0001'', that is, 8 at the falling edge. When the counter CT1 is set to 8 and the Q〓 output becomes "1" and the AND gate is opened, the AND gate is opened.
A clock is output from the gate. This clock serves as the element clock ELCK and is used as an image sensor.
Enter into IS. At the same time, shift clock sfck
It is also input to shift register SR1. The image sensor IS is composed of, for example, a CCD, and is synchronized with the input of the element clock elck.
Outputs video signals serially. As described above, this video signal passes through the amplifier A and the binarization circuit B, and is added as pixel data to the shift register SR1, where it is input one bit at a time in synchronization with the input shift clock sfck. Since the Q〓 output becomes "1", the L input becomes "1", and after that the counter CT1 is clocked.
The value is incremented one by one in synchronization with clk. Furthermore, 7 clocks clk are input, and the counter CT
When the value of 1 becomes F, that is, "1111", the _C0 output becomes "1" and the L input becomes "0" again. Also,
At this time, the α to δ inputs become “0010”. Therefore,
When the next clock CLK is input, at its falling edge,
Counter CT1 is set to 4 and the AND gate is closed. During this time, a total of 8 clocks are output from the AND gate, and based on these clocks, 8-bit serial pixel data _d0 to _d7 are input to the shift register SR1. Thereafter, the counter CT1 repeats setting 4 in synchronization with the input of the clock clk. Further, the shift register SR1 holds 8-bit data _d0 to _d7 . Next, read strobe ws ₀ from μ-COM again.
When this is output, the data held in the shift register SR1 is output onto the eight data buses _D0 to _D7 , the counter CT1 is reset, and the above series of operations is repeated again. In this way, the μ-COM takes in pixel data for one main scanning line. For example, when capturing pixel data for one line of 2048 bits from a B4 size original, the above operation is repeated 256 times for each 8 bit. μ-COM encodes the captured pixel data line by line as described below, and then transmits the data to the other party's device via the transmission/reception information input/output unit, modem, and network control unit. Before explaining the operation, we will explain the received image output section and the received image recording section for recording the received image after data sent from the other party's device is decoded by μ-COM. Since this embodiment employs a thermal recording method, the received image output section and received image recording section have circuit configurations suitable for this purpose. It goes without saying that the basic configuration is not limited to only heat-sensitive recording methods. Received image output unit (see Figure 5 a, b) The received image output unit has 33
Bit shift registers SFR1 to SFR8, NAND gates NAND1 to NAND8, power switching transistors Tr1 to Tr8, monomulti M, and inverting circuit N are connected as shown in the figure. Input terminal of each shift register SFR1 to SFR8
Data buses D ₀ to D ₈ are connected to IN, and the output terminals of each shift register SFR1 to SFR8
O ₁ is for each NAND gate NAND1 to NAND8,
Output terminals O ₂ to _{O 7} are signal input lines B1 to B256 of the thermal element of the received image recording section, which will be described later.
It is connected to the. Each power switching transistor Tr1 to Tr8
Each output terminal is connected to each segment selection input line EG1 to EG8 of the thermal element described later. Next, the operation will be explained with reference to the time chart of FIG. 5b. At the time of reception, the microcomputer performs decoding processing on the received data, which will be described later, and sends the decoded pixel data 8 bits at a time in parallel to the data bus D ₀ -
Output on _D7 . Also, at this time, μ-COM is 8 each.
Write strobe _WS0 is output on signal line _WS0 in synchronization with bit parallel data. Each 8-bit data is a write strobe ws ₀
The data is sequentially input to each shift register SR1 to SR8 and written. In this way, each shift register SFR1~
When the data transfer of 32 bits to the SFR8 is completed, that is, when a total of 256 bits of pixel data has been transferred to the received image output section, μ-COM temporarily stops the data transfer and finally transfers the data to each thermal element. Outputs segment selection data along with write strobe ws ₀ . This is shifted into the 33rd bit of each shift register SR1-SR8 via data buses _D0 - _D7 . This segment selection data is added to each 256-bit pixel data, and as a result, each time the pixel data in shift registers SR1 to SR8 is updated, shift registers SFR1 to SFR
Set the O ₁ output of 8 to 1 in order. Predetermined data is output from the microcomputer, and this is sent to the shift register of the reception image output section.
When stored in SFR1 to SFR8, μ-COM
A read strobe _RS2 is outputted from the unit, and this is input to the monomulti M of the received image output section. As a result, a power enable is generated from the monomulti M for a predetermined time τ, and gates NAND1 to
Input to NAND8. On the other hand, at this time the gate
Shift register SFR1 for NAND1 to NAND8
~Since segment selection data is input from the output terminals _O1 to _O8 of SFR8 via signal lines _G1 to _G8 , when recording a predetermined gate, for example, the first segment of one line, the gate The output of NAND1 becomes "0", transistor Tr1 is turned on, and signal line EG1 of thermal element SE of the received image recording section is connected to the power supply. Received image recording unit (see Figures 6a and b) The received image recording unit is driven by a pulse motor PM that feeds the thermal recording paper in the sub-scanning direction, as shown in Figure 6a, and a pulse motor PM that conveys the recording paper. It consists of a transport roller R, a presser roller RO, a thermal element SE, a recording paper roll PR, and a recording paper detector SP. As shown in Figure 6b, the thermal element SE has heating resistive elements R1 to R204 of 2048 bits for one line in order to record on B4 size recording paper.
8 are arranged. Each element has 256 bits and 8
It is divided into two segments, and one end of each element of each segment is connected to each segment selection signal EG1 to EG8.
It is connected to the. Further, the other end side of each element is connected to common thermal element input lines B1 to B256 in the order of arrangement in each segment.
Note that the diode D connected to each element is provided to prevent current from flowing around. Next, its operation will be explained. As mentioned above, when the first 1 segment 256-bit pixel data and segment selection data outputted from μ-COM are input to the received image output section in _FIG . From the image output section, connect the segment selection signal line
The power supply voltage is supplied via EG1, and the signal lines B1 to B
256, the image signal is sent to the thermal element.
It is applied to each heating resistance element R1 to R256 of SE.
As a result, the image signal of the first segment is recorded on the thermal recording paper. This recording time is determined by the output duration τ of the monomulti M as described above. When the recording of one segment is completed, the pixel data and segment selection data of the next segment are output from μ-COM, and these are input to the received image output section. Furthermore, when the light strobe ws ₂ is input, the heating resistor element R257 is activated in the same way as above.
~R512 is driven, and the image signal of the second segment is recorded. By repeating this action 8 times, 1
An image signal of 2048 bits per line is recorded on the recording paper. During this time, pulse motor drive data, which will be described later, is output from μ-COM to the control signal output section XI, and based on this, the pulse motor PM rotates to perform sub-scanning for recording. In addition, μ-COM periodically checks the status of the detector SP and takes appropriate measures if the recording paper runs out. As mentioned earlier, μ− in this example
COM is the microprocessing unit section,
Timing generation section, control program storage section,
It consists of an information storage section. Below, these configurations will be explained in order. Microprocessing unit section (see Fig. 7) The microprocessing unit section (hereinafter referred to as the CPU) is configured using Intel's 8085 CPU in this embodiment, as shown in Fig. 7. There is. This 8085CPU has 16 terminals for outputting addresses and data, and on the 16 terminals, at the first timing, a total of 16 bits of address signals a ₀ to a are generated, including the upper 8 bits and the lower 8 bits. ₁₅ , and at the second timing, the upper 8 bits of address signals a ₈ to a ₁₅ and the 8 bits of data signals d ₀ to _{d 7}
is configured so that it is output. Therefore, when the 8-bit data signals _d0 to _d7 are output at the second timing, the upper and lower 16-bit address signals _a0 to _a7 are output. It is necessary to latch the lower 8 bits of address signals _a0 to _a7 . For this reason, a latch circuit RCH1 is provided, and the lower 8 bits of the address signal
The eight output terminals of _the 8085 CPU, which output 8-bit data signals _{d0 to d7 with} timing shifts, are connected to the latch circuit RCH1. That is, when the 8085CPU outputs the address signals a ₀ to a ₇ at the first timing, the ale signal is also output in synchronization with this. Therefore, using the ale signal as a latch strobe, the latch circuit RCH
1, the lower 8 bits of address signals _a0 to _a7 are latched. By the way, the number of terminals for inputting and outputting signals to the 8085 CPU is extremely limited. However, in order to simplify the configuration of a facsimile device and operate it conveniently, it is necessary to use many signal lines.
It is necessary to provide more signals between the CPU, memory, and input/output devices. Therefore, in this embodiment, the decoders DCD1 to
DCD3 is installed to increase the number of signal lines. That is, decoder DCD1 has the upper address
By inputting the 3 bits from the 14th bit to the 16th bit (a ₁₃ to a ₁₅ ), 8 decoder DCD2
By inputting the 4 bits from the 5th bit to the 8th bit (a ₄ to a ₇ ) of the lower address, 16 lines can be created.
The number of signal lines is increased to eight by inputting three bits from the second bit to the fourth bit ( _a1 to _a3 ) of the lower address to the decoder DCD3. However, in the case of this embodiment, since there is no need to use all of these signal lines, the decoder DCD1 uses only two of them.
The present decoder DCD2 uses only six of them. The 8085CPU outputs signals when it is in the input mode to capture address signals, data signals, etc. into the CPU, and outputs signals when it is in the output mode, so these signals are sent to the decoder via gate G.
It is configured to be input to DCD1 and DCD2. The 8085CPU also outputs the io/signal that determines whether to output memory data on the data bus or data from the input/output device, so this signal is also connected to the NOT terminal of decoder DCD1 (NOT terminal).
and is input to DCD2. As a result, when outputting memory data onto the data bus, the decoder DCD1 is selected and the memory select signal line MS4 or MS0 is selected according to the address signals _a13 to _a15 input thereto. The signal ms ₄ or ms ₀ is output.
Also, when outputting the data of the input/output device onto the data bus, the decoder DCD2 is selected and the IO select lines IOS0 to IOS4 and IOS7 are activated according to the address signals _a4 to _a7 input there at that time. Signals iOS ₀ to iOS ₄ or iOS ₇ are output to either. Of these, when the signal ios ₄ is output to the IO select line IOS4, the decoder DCD3 is further selected, and at that time, the address signal a ₁ to input there
a Signal lines RS0 to RS2 and signal lines WS according to ₃
Read strobe signal rs to any of 0 to WS4 ₀
~ _rs2 or write strobe signals _ws0 ~ _ws4 are output. In addition, the signal line INT is connected to the 8085CPU,
Each interrupt signal inta to intd, which will be described later, is accepted. The CPU of this embodiment is configured as described above, and therefore has eight upper address buses.
_A8 to _A15 , data buses _D0 to _D7 , write strobe signal lines WS, eight lower address buses _A0 to _A7 ,
Two memory select signal lines MS4, MS0, 5
Main IO select signal line IOS7, IOS0 ~ IOS3,
Three lead strobe signal lines RS0 to RS2, 5
The write strobe signal lines WS0 to WS4 and the interrupt request signal line INT are connected. Of course, this is just one embodiment of the present invention, and it goes without saying that if the microprocessor used is different, the circuit configuration will also be different. Among the above signal lines, for example, the read strobe signal line RS0 is connected to the write strobe signal lines WS0 and WS to the image information input section of FIG.
2 is connected to the received image output section of FIG. 5a, and other buses and signal lines are also connected to each section described below. Timing Signal Generation Unit (See Figure 8) The timing signal generation unit, as shown in Figure 8, is composed of a crystal oscillation circuit and a frequency division circuit that divides and outputs the clock obtained from the crystal oscillation circuit. It generates a clock clk, a row synchronization signal ss, timing signals s ₁ to s ₄ to be described later, etc., which are input to the image information input section of FIG. 4a. Control program storage section (see Figure 9) The control program storage section is a section in which the operation procedures for performing the operations described above and the operations described later, and the code conversion table described below are stored.
As shown in FIG. 9, it is configured using two 4K byte read-only memories (hereinafter referred to as ROM). This ROM has 13 address buses _A0 to _A12 ,
Memory select signal line MS0 and data bus D ₀
~ _D7 is connected. Therefore, as mentioned above, the signal line MS from the CPU
When the memory select signal _ms0 is output on the data bus D0 to D7, memory data can be output to the data bus _D0 to _D7 , and the address bus output from the CPU
ROM or ROM is selected by the address signal _a12 on _A12 , and the address bus _A0 ~
8 bits of memory data _d0 to _d7 within a predetermined address are output onto data buses _D0 to _D7 by _the 12 bits of address signal a0 to _a11 on _A11 . Information storage unit (see Figure 10) The information storage unit is a part that temporarily stores data required during execution when the CPU executes a predetermined program, and is a 1K x 4-bit random access memory (hereinafter referred to as RAM). It is constructed using two pieces. Ten address buses _A0 to _A9 , a memory select signal line MS4, a write strobe signal line WS, and data buses _D0 to _D7 are connected to this RAM. Furthermore, the data bus is divided into four lines, data buses D ₀ to D ₃ are used for RAM, and data buses D ₄ to _{D 7} are used for RAM.
is connected to RAM. Therefore, the RAM is selected by the memory select signal _ms4 on the signal line MS4 outputted from the CPU, and put into a write or read state according to the write strobe signal ws outputted from the CPU on the signal line WS, In _addition , _{the RAM and}
A predetermined address in the RAM is selected, and the data d ₀ - d ₇ on buses D ₀ - D ₇ are divided into 4-bit units and input thereto, or from there, 4-bit units are sent to data buses D ₀ - D _7. Output. Transmission/reception information input/output section (see Figures 11 a to c) The transmission/reception information input/output section transmits encoded parallel data every 8 bits or protocol output from μ-COM to the other device during transmission. - While outputting the parallel data of every 8 bits output from COM to the modem serially,
During reception, this is the part that converts the serial data sent from the other device into parallel data of 8 bits and outputs it in order to input it to μ-COM, and uses latch circuits RCH2 to RCH4 and shift registers SR2 and SR8.
It consists of a forward counter CT2, a flip-flop FF, and gate circuits GT2 to GT6. The latch circuit RCH2 has eight data buses D ₀
~ _D7 and write strobe signal line WS1 are connected, and when a write strobe is output from the CPU onto signal line WS1, data bus _D0 ~ _D7
Latch the above data d ₀ to d ₇ and shift register
Output to eight input terminals P ₀ to P ₇ of SR2. Shift register SR2 has a signal line for receiving received data RXD output from the modem.
RXD, transfer clock clkm output from modem
Signal line CLKM and gate to accept
A signal line for inputting the parallel load signal p1 output from GT ₃ is connected. In addition, a signal line TXD for outputting transmission data txd is connected to the modem from the parallel data output terminal _Q7 , and when the parallel load signal p1 is input during transmission, it is latched at the rising edge of the transfer clock clkm. Shift the data d ₀ to _{d 7} of circuit RCH2 to shift register SR
At the same time, the data is serially output from the _Q7 terminal to the modem in synchronization with the transfer clock. The latch circuit RCH3 is composed of a latch circuit with a tri-state output, and includes a read strobe signal line RS1, data buses _D0 to _D7 , and a signal line for inputting the latch strobe rc output from the gate _GT2 . During reception, when the latch strobe rc is input, the 8-bit data d ₀ input to the shift register SR2 at the rising edge of the latch strobe rc is connected.
~d ₇ is taken into the latch circuit RCH3, and when read strobe rs ₁ is input, the data d ₀ ~ d ₇
is output on data buses _D0 to _D7 . The latch circuit RCH4 responds to the input of the write strobe ws ₂ , and then outputs data from the CPU to the data bus D ₀ ,
Signals d ₀ and d ₁ output on D ₁ are set and output to husband gates GT ₃ and GT ₄ . Counter CT2 outputs a signal c to gates GT2, GT3 and flip-flop FF every time it counts eight transfer clocks clkm. Flip-flop FF is set at the next rising edge of transfer clock clkm when counter CT2 generates carry C, and generates a signal for generating interrupt request signal intc or intg, which will be described later. When the latch circuit RCH4 is generating the interrupt enable signal i, the gate GT4 issues an interrupt request intc based on the generation of the signal r.
Or output intg to CPU. Since interrupt request signals are also input to the CPU from other input/output devices via one signal line INT, a gate GT6 is provided to distinguish them from those interrupt causes. That is, the CPU periodically generates a read strobe _rs2 and takes in the signal r from the data bus _D0 to the CPU, so that the interrupt request generated at that time is an interrupt request from the transmission/reception information input/output section. Discriminating between things. Therefore, if each signal line is prepared for each interrupt request, this gate GT6 becomes unnecessary. Next, the operation is shown in FIGS. 11b and 11c for the transmission mode and reception mode, respectively.
This will be explained with reference to the time chart. [Transmission mode] During transmission, as shown in FIG. 11b, the signals d ₀ and d ₁ output from the CPU onto the data buses D ₀ and D ₁ are sent to the latch circuit RCH4 by the write strobe ws ₂ .
is latched to. As a result, the latch circuit RCH4
A transmission mode signal tx/=logic "1" and an interrupt permission signal i=logic "1" are output from. Counter CT2 counts 8 transfer clocks clkm, and when the value reaches 7, generates a signal c. Due to the occurrence of this carrier c, the flip-flop
FF is set at the next rise of transfer clock clkm and outputs signal r to AND gate GT4. Therefore, an interrupt request intc is sent from gate GT4 to the CPU.
is output. Also, this Kyari c is Gate GT
3 to the shift register SR2 as a parallel load signal p1. Shift register SR2 receives parallel load signal p
1 input, the data d ₀ to d ₇ of the latch circuit RCH2 are taken in at the next rising edge of the transfer clock clkm. This data _d0 to _d7 is shifted by the transfer clock clkm and serially outputted bit by bit from the _Q7 terminal to the modem. When the CPU receives the interrupt request signal intc output from gate GT4, the next 8-bit data d ₀
Output ~d ₇ on data D ₀ ~ _{D 7} and connect signal line
Output light strobe ws ₁ on WS1. As a result, the latch circuit RCH2 latches the data _d0 to _d7 at the rising edge of the write strobe _ws1 .
At the same time, the flip-flop FF is reset. When 8 transfer clocks clkm are input, all data d ₀ to _{d 7} in shift register SR2 are output to the modem, and parallel load signal p1 is generated again by the signal c from counter CT2, and latch circuit RCH2 is output. The data is taken into the shift register SR2, and at the same time, it is outputted to the modem one bit at a time, as described above. In this way, the transmission/reception information input/output section
Converts 8-bit parallel data output from the CPU into serial data and continuously outputs it to the modem. By the way, the CPU only has to output 8-bit data and the write strobe _ws1 on the data buses _D0 to _D7 after accepting the interrupt request signal intc and before the counter CT2 outputs the next signal c. However, if the processing speed of the CPU is very fast and it is possible to output data d ₀ to d ₇ and write strobe ws ₁ within 1 bit of the transfer clock clkm after accepting the interrupt request signal intc, then
The latch circuit RCH2 can be omitted. Therefore, this example is effective when the transfer clock clkm is extremely fast or when the CRU processing speed is extremely slow. [Reception mode] During reception, as shown in Figure 11c, the CPU
The latch circuit RCH4 outputs the reception mode signal tx/=logic “0” and the interrupt enable signal i=by the signals d ₀ and d ₁ and the write strobe ws ₂ output from the
Outputs logic "1". The counter CT2 counts eight transfer clocks clkm as described above, and outputs a signal c when the count reaches seven. This carrier c is input to gate GT2 and flip-flop FF. Therefore, the latch strobe rc is generated from the gate GT2 at the timing shown in the figure, and at its rising edge, the data shifted into the shift register SR2 at that time is latched into the latch circuit RCH3. Data is continuously input one bit at a time from the modem to the shift register SR2 in synchronization with the transfer clock clkm. Therefore, after the data in the shift register SR2 is latched into the latch circuit RCH3, the next data _d0 to _d7 are sequentially shifted into the shift register SR2 in synchronization with the transfer clock clkm. Data _d7 is shifted into the shift register SR2, and at the timing when data _d0 to _d7 appear at its output terminals _Q0 to _Q7 , a signal c is output from the counter CT2. As a result, the gate GT2 generates the latch strobe signal rc, and latches the data _d0 to _d7 in the latch circuit RCH3. Also, at this time, flip-flop FF is set and outputs an interrupt request signal intg to the CPU. The CPU receives this interrupt request signal intg, outputs the read strobe rs ₁ again, and outputs the latch circuit RCH3.
Take in data d ₀ to _{d 7} output from . In this way, in the transmission/reception information input/output section,
It converts the serial data output from the modem into parallel data of every 8 bits and outputs it to the CPU. Like the write strobe ws ₁ in the transmission mode, the read strobe rs ₁ generated at this time may be generated anywhere within the period until the next latch strobe rc is generated. The above describes two latch circuits RH2 and RH3.
An example was shown in which the transmitting/receiving information input/output unit was configured by providing the latch circuit RH2 and
RH3 does not necessarily need to be provided. That is, the data buses D ₀ to D ₇ are directly connected to the P ₀ to _{P 7} terminals and Q ₀ to _{Q 7} terminals of the shift register SR2, and in the transmission mode, the interrupt request signal is
Data d ₀ to _{d 7} and write strobe ws ₁ are transferred within 1 bit of clock clkm after accepting intc.
and outputs an interrupt request signal in receive mode.
The CPU is configured to issue a hard strobe within 1 bit of the transfer clock clkm after receiving intg and capture data _d0 to _d7 . With this configuration, data d ₀ to _{d 7} can be directly received from the CPU to the shift register without going through the latch circuits RH2 and RH3, and in the same manner as described above, every 8 bits output from the CPU are Parallel encoded data is converted to serial data by shift register SR2 and outputted to the modem bit by bit, and serial encoded data inputted from the modem bit by bit is converted to parallel data by shift register SR2 every 8 bits and sent to the CPU. can be taken inside. Control signal input unit (see Figure 12) The control signal input unit receives detection signals or status signals output from input/output devices such as the original reading unit, received image recording unit, modem, network control unit, and operation display unit. This is the part that takes signals into the CPU, and consists of a multiplexer MLP, and the CPU is a data bus.
They are connected via D ₀ , D ₁ , address buses A ₀ , A ₁ , and signal line IOS7. The CPU periodically outputs an input/output select signal iOS ₇ and address signals a ₀ and a ₁ , and the signal input to the multiplexer MLP terminal selected based on these signals is routed to the data bus D ₀ or
Output on _D1 . Control Signal Output Section
and an addressable latch circuit ARCH for outputting operation signals or display signals to input/output devices such as a document reading section, a received image recording section, a modem, a network control section, and an operation display section.
What are address buses A ₀ to _{A 4} , A ₆ , signal lines WS ₃ ,
WS ₄ , connected via IOSO. When the write strobe signal ws ₃ is output from the CPU, the latch circuit RCH 5 latches the signals a ₀ , a ₂ , a ₄ , and a ₆ on the address bus, and outputs the signals to the document reading section as described below. Perform phase excitation of the pulse motor. Also, when the write strobe signal ws ₄ is output from the CPU, the latch circuit
The RCH 6 latches the signals a ₀ , a ₂ , a ₄ , and a ₆ output on the address bus at that time, and phase-excites the pulse motor of the received image recording section. When the input/output select signal ios ₀ is output from the CPU, the addressable latch ARCH latches the signal a ₀ on the address bus A ₀ and selects the output terminal based on the signals a ₁ to a ₃ on the address bus. outputs the latch signal _a0 to a predetermined input/output device. The facsimile apparatus of this embodiment is roughly configured as described above, and in the transmission mode, the process shown in the comprehensive operation flow in FIG. 14 is carried out, and in the reception mode, the process shown in the comprehensive operation flow in FIG. 15 is carried out.
Executed by CPU. Next, details of the processing will be explained below for the cases of transmission mode and reception mode. Transmission Mode In order for the CPU to execute the processing shown in FIG. 14, it is necessary to consider the time allocation for tasks A to E described below. Therefore, the CPU executes each of the tasks A to E in a time-sharing manner in response to each interrupt request. That is, at the time of transmission, the CPU receives the synchronization signal s ₁ generated from the timing signal generation section in addition to the interrupt request signal intc generated from the above-mentioned transmission/reception information input/output section.
Interrupt request signal inta by synchronous signal _s2 , interrupt request signal intb by synchronous signal _s3 , interrupt request signal by synchronous signal s3
intd inputs via signal line INT. The priority order when performing tasks A to D in response to the interrupt request signals inta to intd is A>B>C>D, and work E is normally executed. Below is an outline of the tasks A to E performed by the CPU.
This will be explained with reference to the image data processing path diagram in the figure. [Work A] When an interrupt request is made by inta, the CPU performs work A.
Execute. Its job is to set a memory empty flag MEF or MEF in the working area (WK area) to indicate that the line buffer area (LBF area) I or the information storage RAM that stores image data (described later) is empty. If so, reset the flag MEF or set the data acquisition flag DRF. Furthermore, if the memory empty flag MEF or MEF has been reset, the data retrieval flag DRFI or MEF is reset. This data acquisition flag DRF is referred to when performing tasks B and D described below. [Task B] When an interrupt request is made by intb, the CPU accepts the interrupt request only if the data import flag DRF or the above is set.
Work B is executed to advance the sub-scanning pulse motor of the document reading section by one step. However, depending on the sub-scanning line density, the timing to perform the work differs slightly, and the sub-scanning line density is 7.7 lines/
In the case of mm, when the flag DRF is set, interrupt requests are accepted every other intb, and sub-scanning of 8 steps per line is performed. Sub-scanning line density
In the case of 3.85 lines/mm, when the flag DRF is set, an interrupt request is accepted every time intb occurs,
Performs sub-scanning of 1 line and 16 steps. The details of the work will be described later. Next, before explaining job C, jobs D and E will be explained first. [Work D] When an interrupt request is made by intd, the CPU performs work D.
Execute. As shown in Figure 16, when the data import flag is set, the image data read by the document reading section is sent from the image information input section via the CPU in 8-bit units. Information storage RAM line buffer area
It is best to store in the LBF area or.
However, the above is for the case where the sub-scanning line density is 7.7 lines/mm, and when the sub-scanning line density is 3.85 lines/mm, the CPU is
An interrupt request by intd' is also accepted, and after one line of data is fetched by the interrupt by intd, another line of data is fetched by intd', and logical processing with the previous line is performed to complete the line. Store in Hua area (LBF area) or. Memory full flag after data acquisition is complete
Set MFF or [Job E] This is a job normally executed by the CPU. If the memory full flag MFF or MFF is set, it is reset and the line buffer area (LBF area) is set as shown in Figure 16. )
The bits stored by job D are fetched in units of 8 data, encoded, and then stored in the FIFO area, which will be explained later in the information storage section. When the encoding process for one line is completed, the memory empty flag is set. [Work C] When an interrupt request is made by intc, the CPU performs work C.
Execute. Its job is to sequentially output 8 bits of coded data stored in the FIFO area to the transmission/reception information input/output section. Figure 17 shows an example of a time chart for each job A to E when the sub-scanning line density is 3.85 lines/mm. Interrupt requests inta and based on synchronization signals s ₁ and s ₃ while performing the task E of encoding
When intb is applied, first the data import flag DRF is
A job that sets or resets
After that, job B is executed in which the document sub-scanning pulse motor is advanced by one step, and after jobs A and B are completed, the process returns to job E. Meanwhile, the transmission/reception information input/output section outputs coded data serially to the modem, and as described above, generates an interrupt request signal intc every time 8-bit data is output to the modem. When this interrupt request signal intc is input to the CPU
The CPU interrupts work E and executes work C, which sets the coded 8-bit data in the FIFO area to the transmitting/receiving information input/output section, and returns to work E again. When the interrupt request signal intd based on the synchronization signal _s2 is applied, job D is executed to store the image data read by the original reading unit in the line buffer area (LBF area) in 8-bit units, and the image data for one line is stored. Work E is suspended until everything is stored in the line buffer area (LBF area). Of course, during this time, job C of outputting coded data to the transmitting/receiving information input/output section is being executed continuously, and therefore data is output to the modem without interruption. In other words, the FIFO area capacity is determined by the encoding processing speed, scanner speed, and modem rate, and is set to exceed the number of bits necessary to maintain the minimum transmission time in order to send data to the modem without interruption. In this case, it is set to 256 bits with some margin. Once work D is completed, the CPU returns to work E again. Next, interrupt request based on synchronization signal s _2b
When intd is applied, when the image data read by the original reading unit is stored in the line buffer area (LBF area), the previously stored image data is also taken out at the same time, and the logical sum is calculated and stored in the line buffer area (LBF area). Do work D that you have saved up. Next, a more detailed operational procedure for the above-described work will be explained with reference to FIG. 18 and subsequent figures. FIG. 18a shows the processing procedure for job B in which the sub-scanning pulse motor of the document reading section is advanced by one step. As described above, this work B is performed based on the synchronization signal _s2 that is generated at regular intervals when data can be taken into the line buffer area (LBF area). When the CPU receives the interrupt request signal intb, it interrupts the work D or E that was being executed up to that point, and transfers the data that had been stored in each counter, register, etc. in the CPU to the RAM working area (WK).
area). Next, bring the pulse motor excitation pattern from the working area (WK area) into the CPU and set it. In the case of this embodiment, the phase excitation of the pulse motor is 1-
A two-phase excitation system is adopted, and as explained in the control signal output section XI in Fig. 13 above, the address signal
A ₀ , a ₂ , a ₄ , and a ₆ are used as phase excitation signals for the pulse motor. Therefore, when the system is started, a pulse motor phase excitation pattern, for example "11100000", is set in the working area (WK area), and each time this job B is executed, that pattern is imported into the CPU, and after 1 bit circulation, it is , address bus
The pattern is outputted to the control signal output unit XI via A ₀ , A ₂ , A ₄ , and A ₆ and returned to the working area (WK area). As a result, as shown in FIG. 18b, each time work B is executed, the pulse motor phase excitation pattern is changed to 1.
The bits are circulated, and the outputs a ₀ , a ₂ , a ₄ , and a ₆ change as shown in FIG. 18c, and the pulse motor can be driven one step at a time. After performing this job B, return to the previous job. FIG. 19a shows the flow for transferring the image data read by the original reading unit in job D from the image information input unit to the line buffer area (LBF area) of the information storage unit, and is the flow for transferring the image data read by the document reading unit in job D.
This is a flowchart when no processing is performed. In this embodiment, since the target is B4 size, the case where pixel data of 2048 bits per line is handled will be described, but the number of bits per line is not limited to this. 2048 bits is 8 bits/byte, so it can be expressed in 256 bytes. The line buffer area (LBF area) consists of two 1K x 4 bits as explained in Figure 10, i.e.
Uses 1K x 8-bit RAM from addresses 16384 to 16896. That is, this is expressed in hexadecimal code, and as shown in Figure 19b, the line buffer (hereinafter referred to as LBF) area uses addresses 4000 to 40FF, and the LBF area uses addresses 4100 to 41FF. . Further, the FIFO area is allocated from RAM address 4200 to 42FF, and the working area (hereinafter referred to as WK area) is allocated from RAM address 4300 to 43FF. Various flags, write and read addresses, etc. are stored in the WK area, and in explaining the flowchart below, it is assumed that the various initial settings have already been made and are stored in the WK area. do. When the program in Figure 19a is executed by the CPU, the CPU checks the flag stored in the WK area to see if it is possible to input data to the LBF area or If input is possible, the address stored in the WK area at which data should be written to the LBF area is set in the address register ADR in the CPU. Next, input data every 8 bits from the image information input section.
Transfer from CPU to that address in LBF area,
Add 1 to address register ADR. When this operation is performed 256 times per line, the lower 8 bits of the 16-bit address register become 0. In other words, since one line of image data has been stored in the LBF area at this time, a memory full flag MFF indicating that the LBF area is full is set in the WK area. When the sub-travel line density is 7.7 lines/line, image data for one line is stored in a predetermined LBF area as described above. In the case of a sub-scanning line density of 3.85 lines/line, the logical sum of two lines of image data is obtained based on the programs shown in FIGS. 20a and 20b, and the result is stored in a predetermined LBF area as one line of image data. That is, in the case of odd-numbered line image data, as shown in the flowchart of FIG. 20a, one line of image data is stored, for example, in the LBF area, in exactly the same manner as in the case of FIG. 19a. Next, when the image data of the even numbered lines is taken in 8 bits at a time, the image data of the odd numbered lines previously stored in the LBF area are also taken out 8 bits at a time, as shown in the flowchart of Fig. 20b, and the CPU
By redoing the logical sum within and inputting it into the LBF area, one line of OR-processed image data is stored in the LBF area. Next, the flow of work E in which image data stored in the LBF area is taken out, run-length coded, and stored in the FIFO area will be described with reference to FIGS. 21 to 25. In this example, run length encoding is performed using the Modified Huffman method.
Coding Method). Of course, it goes without saying that other encoding methods may be used. In the case of the modified Hoffman system, the code is divided into a make-up code and a termination code depending on the run length. That is, the termination code is a code according to the run length from 0 to 63 as shown in Table 1 below, and the make-up code is as shown in Table 2.
This code corresponds to a run length that is an integer multiple of 64. In addition, the synchronization code EOL is as shown in Table 3.
It is a code with 11 "0"s and a "1" added at the end.

【table】

Claims (1)

[Claims] 1. A document reading section that reads a document during transmission and outputs serial pixel data; an image information input section that converts the serial pixel data output from the document reading section into parallel pixel data for each predetermined bit;
At the time of reception, a reception image recording section is driven by decoded received pixel data and records predetermined image information on recording paper, and at the time of transmission, parallel pixel data for each of the predetermined bits from the image information input section is recorded. a microcomputer that converts and outputs encoded data for each predetermined bit, and converts parallel encoded data for each predetermined bit that is input during reception into the received pixel data and outputs the same to the received image output section;
At the time of transmission, the parallel encoded data of each predetermined bit output from this microcomputer is converted into serial encoded data of each bit according to the transmission speed and output, while at the time of reception, the data is transmitted from the other party's device according to the transmission speed. The transmitting/receiving information input/output section converts input serial encoded data into parallel encoded data for each predetermined bit and inputs the converted data to the microcomputer, and the transmitting/receiving information input/output section converts input serial encoded data into parallel encoded data for each predetermined bit and inputs the converted data into parallel encoded data for each predetermined bit. a first latch circuit that latches predetermined bits of parallel encoded data and outputs it in parallel;
When transmitting, a predetermined bit of coded data output from this first latch circuit is captured in parallel and output serially one bit at a time in synchronization with the transmission clock, while during reception, it is output one bit in synchronization with the transmission clock. A shift register that sequentially stores encoded data that is input serially and outputs it in parallel when it reaches a predetermined bit, and a shift register that latches the encoded data of a predetermined bit that is output in parallel from this shift register at the time of reception. and a second latch circuit for outputting in parallel to the microcomputer.