JPH03293867A - Facsimile equipment - Google Patents

Abstract

PURPOSE:To obtain a small-sized and inexpensive facsimile equipment by leaving only required minimum hardware such as a scanner, a plotter, and a MODEM as it is and substituting all of the other hardware with a microcomputer (mu-COM). CONSTITUTION:A picture information input part 11 which converts serial data outputted from a document read part 1 to parallel data to input it to the mu-COM, a reception picture output part >=>=>= which outputs the picture signal decoded by the mu-COM to a reception picture recording part at the time of reception, and a reception picture recording part IV which makes a copy of a document are provided. The mu-COM consists of a microcoprocessing unit part V, a timing signal generating part VI, a control program storage part VII, and an information storage part VIII to perform encoding and decoding of the picture signal and control of each part. That is, hard parts such as a buffer device, coder/decoder device, and a communication controller are substituted with the mu-COM. Thus, the inexpensive facsimile equipment having the compact configuration is obtained.

Description

[Detailed description of the invention]

The present invention relates to a facsimile device, and more particularly to a facsimile device using a microcomputer. Recent advances in integrated circuit technology have led to remarkable progress in microcomputers, and microcomputers that are small, have large storage capacities, and are capable of high-level arithmetic processing can now be obtained at very low prices. For this reason, microcomputers have permeated every field, and microcomputers have come to replace parts of facsimile machines that were previously made up of dedicated hardware. However, microcomputers currently have a limit to their arithmetic processing speed, and the hardware part that performs high-speed processing cannot be replaced. On the other hand, since encoding processing in a facsimile machine requires bit-by-bit processing, high processing speed is required. Therefore, in all facsimile machines that have been developed using microcomputers, the parts that require high-speed processing are constructed with dedicated hardware, and the microcomputer is used exclusively as an auxiliary means for that hardware. However, it was not possible to fully utilize the functions of microcomputers. For example, FIGS. 1(a) and 1(b) show block diagrams of conventional facsimile machines that use microcomputers. When microcomputer μ
The mC0M (hereinafter simply abbreviated as H-COM) was only used to sequence control the hardware via each interface circuit 1/F. Therefore, even if a facsimile machine is constructed using common items that can be used on both the sending and receiving sides, there are many components such as memory such as shift registers or random access memory, counters, many gate circuits, and flip-flops for timing control. A buffer device BtJF consisting of the following is required. When performing the protocol, delay circuits, flags, error check code generators and detectors, numerous counters, flip-flops, and shifters are used to create the HDLC format and decode data in that format when received. A communication control unit CCU consisting of registers, gate circuits, etc. is required. At the time of transmission, a counter for counting the run length, a flip-flop and exclusive OR circuit for detecting change points for detecting run breaks, a read-only memory for selecting an encoding code according to the run length, FIF○ buffer memory for temporarily storing the output from the read-only memory and adjusting the speed with the circuit rate, a counter for transferring the encoded code to the FIFO buffer memory, and for correcting the minimum transmission time when the compression rate is high. FILL(
Supplementary) A coder device DCR is required, which consists of a counter for bit generation and a large number of flip-flops and gate circuits for controlling locking if necessary at that time. At the time of reception, a FIFO buffer memory for converting the speed of received image data input from the communication control unit CCU, and a detection circuit for removing FOL (synchronization) code, FII, L bit, etc. from the received image data. A shift register and a bit counter for extracting the encoded code, a read-only memory for selecting the run length binary value corresponding to the encoded code, and a next-stage buffer that stores the run length of the number of bits according to the run length binary value. A decoder device DCRII consisting of a run length counter for transferring to the device, a cumulative counter for counting the number of bits for 1912 minutes and detecting errors, and a large number of flip-flops and gate circuits for controlling locking if necessary at that time. Is required. Furthermore, Fig. 1(a)
, (b), SCN is a scanner, MDM is a modem, PL is a plotter, CO is a copy, CPU, ROM, R
AM is a microprocessor, read-only memory, and random access memory constituting μ-COM, and BUS is a pass line. In this way, in conventional facsimile machines, only a limited number of parts such as the system controller have been replaced with μmC0M, and most of the equipment has had to rely on random logic and hard-wiring, so The disadvantage is that the device is large and expensive. The present invention has been made in view of the above points, and by leaving only the minimum necessary hardware such as a scanner, plotter, and modem in a facsimile machine and replacing all other hardware with μmC0M, a small and inexpensive facsimile machine can be realized. The purpose is to provide equipment. In order to achieve this object, the present invention also includes the encoding process of transmitted image information and/or the decoding process of received image data.
The present invention is characterized in that the facsimile device is configured so as to be able to perform mC0M. Examples of the present invention will be described below, but before that,
The feature points in this example will be listed below. That is, its characteristic points are as follows. (1) After the image information is read by the reading device, everything from counting the run length to encoding and forming the data transmission format is performed in μmC0M. (2) Transfer the received data to μmC0M via the bus,
The subsequent process from decoding the received data to converting it to image data and transferring the data to the recording device is performed in μmC0M. (3) Blinking of the light source for document illumination in the reading device, driving and stopping of the document scanning mechanism, and starting and stopping of the modem and/or network control device are performed in μmC0M. (4) The protocol for handshaking with the other device and the mode setting of the own device are performed using μmC0M. (5) Notification of functions provided by the own device to the other device and/or mode setting of the other device is performed using μmC0M. (6) Error detection in the received image data and processing of the image information of the line where the error occurred are performed by μmC0M. (7) Control of driving, stopping, and recording timing of the recording paper conveying device in the recording apparatus is performed using μmC0M. (8) The blinking of the display lamp in the operation section and the acceptance of operation signals are performed in μmC0M. (9) By appropriately allocating the usage time when performing the above operations on the μmC0M, it is now possible to perform all of the above operations with a single μmC0M. (10) When transferring data from the reading device, the data transfer is completed in a shorter time than the image integration time of the image sensor, making it possible to follow the maximum speed of μmC0M. (11) The preprocessing of the image signal is performed on multiple bits at the same time. (12) In order to encode the image signal in a short time, the simultaneous detection of change points of multiple bits is performed first. (13) When the above change point is subsequently detected, the detection is switched to one bit at a time. (14) During operation, chattering of the operation switch is prevented and the operation signal is reliably captured in μmC0M. In this embodiment, the interface, microprocessing unit, read-only memory, and random access memory are Intel's 8212.80.
85.8316.8101A4, etc., but it goes without saying that there is no need to limit it to this. Hereinafter, embodiments of the present invention will be described in detail with reference to FIG. 2 and the subsequent drawings. FIG. 2 shows a system block diagram of the entire facsimile apparatus according to the present invention.
This is an image information input section that converts the serial data output from the document reading section 1 into parallel data of every 8 bits and inputs it to the μmC0M in order to enable high-speed processing when performing encoding processing in the mC0M. (2) is a received image output unit that outputs the image signal decoded by μmC0M at the time of reception to the received image recording unit, and (2) is a received image recording unit that obtains a copy of the original. μmC0M consists of a microprocessing unit section (2), a timing signal generation section (2), a control program storage section (2), and an information storage section (2), and performs tasks such as encoding and decoding of image signals and controlling each section, which will be described later. (2) converts the parallel data encoded with μmC0M every 8 bits into serial data and outputs it to the modem MDM during transmission, while converting the encoded serial data input from the modem MDM to parallel data every 8 bits during reception. This is a transmission/reception information input/output unit that inputs the information to μmC0M. Of course, this transmission/reception information input/output unit (2) inputs and outputs necessary data when performing protocols and the like in addition to inputting and outputting image data. X and sword are the control signal input section and output section, which include the original reading section ■, the received image recording section ■, the modem MDM, and the network control section N.
This is a part that inputs signals from the CU and the operation display section 10P to μmC0M, and outputs predetermined control signals from μmC0M to each section. Although the facsimile apparatus of this embodiment is constructed as shown in the schematic above, the specific construction and operation of each of the above-mentioned parts will be sequentially explained below with reference to FIG. 3 and subsequent drawings. In addition, modem MDM, network control unit NCU, operation display unit I
As OP, a conventionally known one may be used, and since it is not directly related to the present invention, its explanation will be omitted. Furthermore, in the following description, as a general rule, buses and signal lines are expressed in uppercase letters, and signals appearing there are expressed in lowercase letters. Original reading section I (see Fig. 3) The one-dot chain line part in Fig. 3 is the original reading section ■, where PM is a pulse motor for sub-scanning feed of the J manuscript, and R is driven by the pulse motor PM. Document conveyance roller, Ll is a light source for document detection, L is a light source for document illumination, SL, SL
, is a document detector. When the operator inserts a document into the document reception slot from the direction of the arrow manually or by using the document feeder, the document detector SL,
is activated. μmC0M regularly monitors the state of the detector SL, so when the detector SL is activated, a lighting command is sent to the document illumination light source drive bag 5f via the control signal output unit ℃, which will be described later.
It outputs to the OLD to turn on the light source, and outputs a drive signal to the pulse motor drive circuit PMD to rotate the pulse motor PM. When the pulse motor PM rotates, the transport roller R starts rotating and transports the original in the direction of the arrow. When the leading edge of the document reaches the position of the detector SL, the detector SL outputs it to μmC0 via the control signal input section X, which will be described later.
Let M know. After μmC0M temporarily stops the pulse motor PM, it thereafter switches to sub-scanning feed during reading scanning. Original image is contact glass CG, mirror M, lens L
The image is formed on the image sensor Is via the image sensor Is. The image sensor IS receives an element clock elck and a row synchronization pulse S from an image information input section under the control of μmC0M.
A video signal inputted by S and outputted in synchronization with the clock passes through an amplification NA and a binarization circuit B, and is serially input one bit at a time to the image information input section (2). Image information input section ■ (see Figures 4(a) and (b)) The image information input section ■ is as shown in the dashed-dotted line in Figure 4(a).
A data bus D, which will be described later, is composed of a counter CT, a shift register SR, and an l-license buffer TB, and converts the serial image data output from the binarization circuit B into parallel image data every 8 bits. -D, output above. Generally, when converting serial data to parallel data, there is a method of using two shift registers and taking out the parallel data from the other while serial data is being input to one of them, but in this example, the time required for μmC0M to process the parallel data is Since the clock speed is set so that the next data is filled in the shift register at the same time, only one shift register is used as shown in the figure. The counter CT is composed of a presettable synchronous 4-bit binary counter in order to output eight element clocks elck when a read strobe rSo, which will be described later and is output from μmC0M, is input. Counter CT counts up at the rising edge of the clock input to the CP terminal when logic "1" is input to its Lm child. Further, when the L terminal input is logic "o", the output terminals Qα, Qβ, Qγ, and Qδ are set to the logic input to the α, β, γ, and δ terminals. Furthermore, when "0" is input to the R terminal, it is reset asynchronously with the clock input. All Qα to Qδ outputs from the C0 terminal are “1”, that is, 1
When the hexadecimal number F is reached, "1" is output. It is input to the L terminal of the counter CT via the Go output and the Qδ small output NOR gate. Therefore, when the value of the counter CT becomes 0 to 7 and the hexadecimal number F, the L terminal input becomes "0". Also, the set terminals α and β are always “O”,
A small Qγ output is input to the γ terminal, and a small Qγ output is input to the δ terminal. Therefore, the value of counter CTI is 4 to 7 or hexadecimal C-
When F, the γ terminal input is "1", the δ terminal input is "O", and when the value of the counter CTI is O~3 or 8~13, the γ terminal input is rQJ, and the δ terminal input is FI. From these things, when the value of counter CT is 4 to 7 and F, it is 4.
Also, when the value of the counter CT is 0 to 3, it is set to 8 at the rising edge of the next clock input to the CP terminal. The Qδ small output of this counter CT is input to an AND gate to control generation and stop of the element clock elck. Shift register SR is composed of an 8-bit serial input/parallel output shift register. Tri-state buffer TB is read strobe rso
The 8 bits of data shifted into the shift register SR1 are transferred to each of the 8 data buses D in μmC0M during the period when the shift register SR1 is active. -D, output above. Next, the operation will be explained with reference to the time chart of FIG. 4(b). When a read strobe rso (negative pulse) is output from μmC0M, this pulse is input to the G terminal of the tri-state buffer TB of the image signal input section (■) via the signal line rso (described later), and the contents of the shift register SR, Output to eight data buses D0 to D in parallel. At the same time, it is also input to the R terminal of the counter CT, and the strobe r
At the falling edge of so, reset the counter CT. The parallel data output on the data bus is μmC0M
is taken into the accumulator. By the way, the lead strobe rs at this time. The timing of generation of is free, and its pulse width may also be arbitrary. In addition, the period of the clock clk is such that if at least 9 clocks are not generated between when μmC0M outputs read strobe rsa to take in data and outputs read strobe rso to take in the next data, shift register SR and Since the 8-bit data is not filled in, normal operation will not be performed.
The period may be arbitrary as long as nine or more clocks are generated during that period. By resetting the counter CT t , its Qα to Qδ outputs become ro OOOJ. As a result, ■, the large input is “0”, and the inputs of α to δ are “0001”.
J, and when the primary clock clk is input to the counter CT, the outputs of Qα to Qδ become rooo at the falling edge.
IJ, that is, set to 8. When the counter CT is set to 8 and the AND gate is opened with the Qδ small output "l", a clock is output from the AND gate, and this clock is input to the image sensor Is as the element clock elck. At the same time, shift register S is set as shift clock 5fck.
Also input R. The image sensor IS is composed of, for example, a COD, and serially outputs a video signal in synchronization with the input of the element clock 5ick. As mentioned above, this video signal passes through the amplifier A, the binarization circuit B, and the shift register S.
Shift clock 5fek added to R, and input thereto
Input l bits at a time in synchronization with . Due to the Qδ small output being “1”, the L input is “1”
After that, the counter CT + increments its value one by one in synchronization with the clock clk. Furthermore, when 7 Glock clks are input and the value of the counter CT becomes F, that is, rl 111J, the co small output [
1], the L input becomes "OJ" again. At this time, the α to δ inputs become roo 10J. Therefore, when the next clock clk is input, the counter CT is set to 4 at the falling edge of the next clock clk. Close the AND gate. During this time, a total of 8 clocks are output from the AND gate, and based on this clock, the shift register S R
l is 8-bit serial data D. 〜■−] has been input. Thereafter, the counter CT repeats the setting of 4 in synchronization with the input of the clock clk. In addition, the shift register SR receives 8-bit data d. ~d, is retained. Next, when the read strobe rs0 is output from μmC0M again, the data held in the shift register SR is output onto the eight data buses D, ~D7, and the counter CT t is reset, and the above Repeat a series of actions. In this way, μmC0M takes in data for two main scan lines. For example, when capturing image data of 2048 bits per line from a B4 size original, the above operation is repeated 256 times for 8 bits each. The μmC0M encodes the captured image data line by line as described below, and then transmits the data to the other party's device via the transmission/reception information input/output unit (2), the modem MDM, and the network control unit NCU. Before explaining these operations, we will explain the received image output section m and the received image recording section ■, which record the received image after decoding the data sent from the other party's device using μmC0M. . Since this embodiment employs a thermal recording method, the circuit configurations of the received image output section m and the received image recording section ' are also suitable for this purpose, but it can be done by making only a few changes. It can be applied to various recording methods, and its basic configuration is as follows:
Needless to say, the method is not limited to only the thermal recording method. Received image output section m (see FIGS. 5(a) and (Ll)) The received image output section has a 33-bit shift register SFR, ~SFR, and NAND game hN, as shown in FIG. 5(a) and (Ll).
, A N D , ~NAND, , power switching transistors Tr, ~Tr, , monomulti M, and inverting circuit N are connected as shown in the figure. Data buses D6-D are connected to input terminals IN of each shift register SFR, -SFR. Further, the output terminal 01 of each shift 1 register SFR, ~SFR, is each NAND gate NAND, ~NAND. Output terminals O1 to ○ are signal input lines B, to B, of a thermal element of a received image recording section (2), which will be described later. It is connected to the. Each output terminal of each power supply switching transistor T r , ~Tra is connected to each seventh segment selection input line EG, ~EG of a thermal element described later. Next, the operation will be explained with reference to the fifth [J(b) time chart]. During reception, μmC0M performs a decoding process (described later) on the received data, and sends the decoded image data 8 bits at a time in parallel to the data bus D. ~Output on D7. Also, at this time, μmC0M is synchronized with each 8-bit parallel data and a write strobe W S is generated. is output onto the signal line WSo. Each 8-bit data is sequentially input to each shift register SFR, ~SFR, by write strobe WS0,
It will be written. In this way, each shift register SFR to SFR
When the data transfer for 32 bits is completed in s, that is, a total of 256 bits of @i element data is transferred to the image information output section m.
When the data is transferred, μmC0M temporarily stops the data transfer and finally outputs data ssd for selecting each segment of the thermal element together with the write strobe WSO. This is shifted into the 33rd bit of each shift register SFR, -SFR, via data buses D0-D. This segment selection data is added to each 256-bit image data, and as a result, each time the data in the shift registers SFR, -3FR, is updated, the shift registers SFR, -3FR, are updated, as will be described later. The O1 output of each is set to 1 in turn. When predetermined data is output from μmC0M and stored in the shift register SFR, -3F Ra of the image information output section m, read strobe r is output from μmC0M.
s is output, and this is the mono multi M of the image information output section ■
Enter. As a result, a power enable is generated from the monomulti M for a predetermined time τ, and the gate N A N D + ~NA
Enter into NDI. On the other hand, at this time the gate NAND, ~
Since the segment selection data ssd is input to the NAND from the output terminals O3 to O of the shift registers SFR to 5FRa through the signal lines G1 to G, the first segment of a predetermined gate, for example, the l line, is recorded. In this case, the output of the gate NAND becomes "0", the transistor Tr is turned on, and the signal line EG of the thermal element SE of the received image recording section (2) is connected to the power supply. Received image recording section ■ (see Figures 6 (a) and (b)) The received image recording section ■ is equipped with a pulse motor PM and a pulse motor for sub-scanning feeding of thermal recording paper, as shown in Figure 6 (a). Conveyance roller R1 that is driven by PM and conveys the recording paper, press roller RO, thermal element SE, and recording paper roll PR.
1 recording paper detector SP. As shown in FIG. 6(b), the thermal element SE records on B4 size recording paper, so
48-bit heating resistance element Rl”” R! . , 8 are arranged. Each element is divided into eight segments of 256 bits each, and one end of each element in each segment is commonly connected to each segment selection signal EG, -EG. In addition, the other end side of each element is connected to a common thermal element input line B1=Bzs in the arrangement order in each segment.
connected to g. Note that the diode D connected to each element is provided to prevent current from flowing around. Next, its operation will be explained. As mentioned above, the first segment of 256-bit image data output from μmC0M and the segment selection data are input to the received image output section (■) in FIG. 5(a), and the write strobe W S is further input. Then, the power supply voltage is transmitted from the received image output unit m via the segment selection signal line 'E G , and the image signal is transmitted via the signal lines 81 to B164 to each heating resistor element R, to R of the thermal element SE.
Apply to o6. As a result, the recording time for recording the image signal of the first segment on the thermal recording paper is determined by the output duration τ of the monomulti M, as described above. When the recording of one segment is completed, the image data and segment selection data of the next segment are outputted from μmC0M, and these are input to the received image output section (2). When the write strobe WS is further input, the heating resistive elements R7, 7 to R51 are driven in the same manner as described above, and the image signal of the second segment is recorded. By repeating this operation eight times, an image signal of 2048 bits for one line is recorded on the recording paper. During this time, pulse motor drive data, which will be described later, is output from μmC0M to the control signal output section M, and based on that,
The pulse motor PM rotates and sub-scanning of recording is performed. In addition, μmC0M periodically checks the status of the detector SP and takes appropriate measures if the recording paper runs out. As mentioned above, μmC0M in this embodiment is composed of a microprocessing unit section V, a timing signal generation section (2), a control program storage section (2), and an information storage section (2). Below, these configurations will be explained in order. Microprocessing unit section V (see Figure 7) Microprocessing unit section ■ (hereinafter simply referred to as CP)
(abbreviated as tJ) is configured using Intel's 8085 CPU in this embodiment, as shown in FIG. This 8085 CPU has 16 terminals for outputting addresses and data, and on the 16 terminals, at the first timing, address signals a0 to a4 of a total of 16 bits (upper 8 bits and lower 8 bits) are output. However, at the second timing, the upper 8 bits of address signals a, ~ass
and 8-bit data signals d0 to d are output. Therefore, when the 8-bit data signal dO-d is output at the second timing, the upper and lower 16-bit address signals a0-a are output, so the lower 8 bits output at the first timing are It is necessary to latch the address signals a0 to a. For this reason, a latch circuit RCHI is provided, and the 8085CP outputs the lower 8-bit address signals 80 to a7 and the 8-bit data signals d0 to d7 with timing shifts.
U8 output terminals are connected to the latch circuit RCH1. That is, when the 8085 CPU outputs the address signals aO to a at the first timing, the ale signal is also output in synchronization therewith. Therefore, by inputting the ale signal as a latch strobe to the latch circuit RCH, the lower 8 bits of the address signals a0 to a
, is latched. By the way, the number of terminals for inputting and outputting signals to the 8085 CPU is extremely limited. However, in order to simplify the configuration of the facsimile machine and to operate it conveniently, it is necessary to provide more signal lines between the CPU, memory, and input/output devices, and to input and output more signals. Therefore, in this embodiment, the decoders DCD, ~DCD i
, and the number of signal lines is increasing. That is, by inputting the 3 bits from the 14th bit to the 16th bit (ass to a Is) of the upper address to the decoder DCD, the decoder DCD inputs 8 bits from the 5th bit to the 16th bit of the lower address. 8th bit (a4~
By inputting the 4 bits of a, ), 16 lines are input, and by inputting the 3 bits from the 2nd bit to the 4th bit (at to aJ) of the lower address to the decoder DCD, 8 bits are input.
The Honzuke Line is being added. However, in the case of this embodiment, there is no need to use all of those signal lines, so the decoder D
The CD uses two of the tenons, and the decoder DCD uses only six of them. From the 8085 CPU, in the input mode where address signals, data signals, etc. are taken into CPtJ, the wr multiplied signal,
Further, since rd times signals are output in the output mode, these signals are inputted to the decoder DCD and the decoder DCD via the gate G. Also,
The 8085 CPU also outputs an io/m signal that determines whether to output memory data on the data bus or input/output device data, so this signal is also sent to the decoder DCD, (NOT terminal of) and DCD. , is input. As a result, when outputting memory data onto the data bus, decoder DCD is selected, and address signals all to a1. Memory select signal line MS or MS according to the memory select signal line MS. A signal mSa or mso is output to either of the two. Also, when outputting data from the input/output device onto the data bus, the decoder DCD is selected, and the select lines IO3, ~IO3, and Signals 10so to 10S4 or 10s are output to either of l087. Among these, when the signal 10s4 is output to ■○ select [II○S, decoder DCD is further selected,
At that time, the signal lines R8, -RS and the signal lines WSO~ws,
Read strobe signals rso to rs or write strobe signals W So to W S are output to either of them. Further, a signal line INT is connected to the 8085 CPU, and is adapted to receive each interrupt signal int, to 1nt=, which will be described later. The C:PUV of this embodiment is configured as described above,
Therefore, there are eight upper address buses A, ~A +
&, data buses D0 to D2, write strobe signal lines WS, eight lower address buses A, ~A1, two memory select signal lines MS, , MSo, and five IO select signal lines IO5? , l03O to O8s, three read strobe signal lines RS o to R8,, five write strobe signal lines WS0 to WS4 and an interrupt request signal line INT
is connected. Of course, this is just one embodiment of the present invention, and it goes without saying that as the microprocessor to be used develops, its circuit configuration will naturally evolve as well. Among the above signal lines, for example, the read strobe signal line R
36 is the image information input section ■ of FIG. 4(a) already explained,
The write strobe signal lines WSO and WS2 are shown in FIG.
The image information output section a) is directly connected, and other buses and signal lines are also connected to each section described below. Timing Signal Generating Section (2) (See FIG. 8) The timing signal generating section is as shown in FIG. It consists of a crystal oscillator circuit having a crystal oscillator QCO, and a frequency dividing circuit DIV that divides and outputs the clock obtained from the crystal oscillator circuit, and inputs it to the above-mentioned fourth (5ffl(a)) image information input section It generates a clock clk, a row synchronization signal ss, a timing signal S, ~S4, etc., which will be described later.Control program storage section 1 (See Fig. 9) The control program storage section stores operations for performing the operations described above and operations described below. As shown in FIG. 9, this is the part where procedures and code conversion tables to be described later are stored, and 4 bytes of read-only memory (hereinafter simply referred to as ROM) 2
It is configured using individual ROMs, ROMs, and ROMs. This ROM,,ROM, has 13 address buses A.
. -Al1, memory select signal line MS0, and data buses D0 to D7 are connected. Therefore, as described above, when the memory select signal mso is output from the CPU onto the signal line MS0, memory data can be output to the data buses D0 to D7, and the CPU
The ROM or ROM is selected by the address signal all on the address bus A12 output from the address bus A1. Upper address signal 12 bit 1 soto a. 8 bits of memory data within a given address by ~all d. ~d7 is data bus D. -D
7 is output. Information storage section (see Figure 1O) The information storage section is used when the CPU executes a predetermined program.
IK is a part that temporarily stores data required during execution.
X4-bit random access memory (hereinafter simply referred to as RA)
It is configured using two RAMs (abbreviated as M). This RAM,,RAM, has 10 address buses A0.
~A, memory select signal line MS, write strobe signal line WS, and data buses D0 to D. is connected. Furthermore, the data bus is divided into four each, and data buses D0 to D are used as RAM, and data bus D4 is used as RAM.
~D, are connected to RAM. Therefore, depending on the memory select signal ms on the signal line MSo output from the CPU, the RAM or RAM
is selected and put into a write or read state according to the write strobe signal WS on the signal line WS output from the CPU, and the address signal 10 bit a on the buses A and -As. ~a. A predetermined address in RAM and RAM z is selected by bus D. ~Data d0 on D7
~d7 is divided into 4 bits each and inputted, or 4 bits each are inputted to the data bus D. ~D, is output. Sending/receiving information input/output section ■ (See Figure 11 (a) to (C))
The transmitting/receiving information input/output unit sends encoded parallel data every 8 bits output from μmC0M during transmission or parallel data every 8 bits output from μ-〇〇M during protocol to the other device. While serially outputting the parallel data of every 8 bits output from the modem to the modem, when receiving, the serial data sent from the other device is input to μmC0M, so it is converted to parallel data of every 8 bits and output. The parts include latch circuits RCH, ~RCH, shift register SR2, octal counter CT, flip-flop FF, and gate circuit GT.
, ~GT. The latch circuit RCH has eight data buses D. ~D7 and the write strobe signal line ws1 are connected, and when the CPU outputs the rad strobe signal ws on the signal line wsl, the data d on the data buses D0 to D7. ~d7 is latched, and eight input terminals P0~P of the foot register SR are latched. ! ,:Output. The shift register SR has a signal IRXD for receiving reception data rxd output from the modem, a signal line CLKM for receiving transfer lock c1m output from the modem, and a parallel signal output from gate GT3. A signal line for inputting a load signal p is connected thereto. In addition, the 6th parallel data output terminal Q7 is connected to the modem by the signal line TXD for outputting the message data txd, and when the parallel load signal pl is input during transmission, the rising edge of the transfer lock C1km is connected to the modem. At the same time, the data d0 to d7 of the latch circuit RCH are taken into the shift register SR, and at the same time, the data is serially output from the Q terminal to the modem in synchronization with the transfer clock. The latch circuit RCH is composed of a latch circuit with a tri-state output, and includes a read strobe signal JIR8, data buses D6 to D, and gates G T
A signal line inputting the latch strobe rc output from 2 is connected, and when receiving, the latch strobe rc
When input, the shift register S
The 8-bit data d0 to d7 input to Rz is taken into the latch circuit RCH3, and when the read strobe re is input, the data d0 to d7 are transferred to the data buses D0 to D.
Output on 7. The latch circuit RCH sets the signals d0 and d output from the CPU onto the data buses Do and Dl in response to the input of the write strobe WS, respectively, and sets the signals d0 and d output from the CPU to the respective gates GT.
, , output to GT. Counter CT 1 outputs carry C to gates GT, , GTs and flip-flop FF every time it counts eight transfer clocks clkm. Flip-flop FF is set at the next rising edge of transfer lock clkm when counter CT generates carry C, and generates an r signal to generate an interrupt request signal inn or intg, which will be described later. When the latch circuit RCH4 is generating the interrupt enable signal 1, the gate GT outputs an interrupt request signal int, e, or int to the CPU based on the generation of the signal r. Since interrupt request signals are also input to the CPU from other input/output devices via one signal line IN, a gate G T g is provided to distinguish them from those interrupt causes. That is, the CPU periodically generates a read strobe rc1 and takes in the signal r from the data bus D0 to CPtJ, thereby confirming that the interrupt request generated at that time is an interrupt request from the transmission/reception information input/output unit (■). It discriminates. Therefore, if each signal line is prepared for each of the five interrupt requests, this gate GT becomes unnecessary. Next, the operation will be explained in the case of transmission mode and reception mode with reference to the timing charts of FIG. 11(b) and FIG. 11(C), respectively. [Transmission Mode] During transmission, as shown in FIG. 11(b), data bus D is transmitted from the CPU. , D1 are latched into the latch circuit RCH by the write strobe W S . As a result, the latch circuit RCH outputs the transmission mode signal t, x / r x = logic HJI rl.
And interrupt permission signal 1=logic rlJ is output. Counter CT counts 8 transfer locks clkm,
When the value reaches 7, a carry C is generated. Due to the occurrence of this carry C, the flip-flop FF is set at the rising edge of the next transfer lock clkm, and outputs the signal r to the AND gate GT. Therefore, an interrupt request signal inte is output to the gate GT and cPU. Further, this carry C is input to the shift register SR as a parallel load signal pl through the gate GT. In response to the input of the parallel load signal p1, the shift register SR takes in the data d0 to d of the latch circuit RCH at the next rising edge of the transfer lock clkm. This data d. -d7 is shifted to 5Q by the transfer lock clkm, and is serially output from the terminal to the modem one bit at a time. The CPU receives an interrupt request signal in output from the gate GT.
When t is accepted, the next 8 bits of data d, ~dt
data bus D. ~D, output to the top and signal line WS
A write strobe WS is output on t. As a result, the latch circuit RCH, becomes the write strobe W.
Data d0 to d7 are latched at the rising edge of S. At the same time, flip-flop FF is reset. When the transfer lock clkm has an S* large input, the data d in the shift register SR. -d is output to all modems, and the parallel load signal p1 is generated again by the carry C from the counter CT, and the latch circuit RC
At the same time as the data of H, is taken into the shift register SR2, it is outputted to the modem one bit at a time as described above. In this way, the transmission/reception information input/output unit (2) converts the parallel data of every 8 bits outputted from the CPU into serial data and continuously outputs it to the modem. By the way, after the CPU receives the interrupt request signal 1nt6 and until the counter CT outputs the next carry C,
It is sufficient to output 8-bit data and write strobe WSI onto data buses D0 to D, but
If the processing speed of CPLI is very fast, after receiving the interrupt request signal int, the data can be transferred within the lock clkml bit? , and Rai[・
If the strobe WS, can be output, the latch circuit RCH, can be omitted. Therefore, this example is useful if the transfer lock clkm is extremely fast or if the transfer lock clkm is
This is effective when the processing speed of the PU is very slow. [Reception mode] During reception, as shown in FIG. 1.1(c), the signal d is output from the CPU. , d and light strobe w
s2, the latch circuit RCH receives the reception mode signal tx.
/rm = logic rQJ and interrupt enable signal 1 = logic "1"
Output. The counter CT counts eight transfer clocks clkm as described above, and outputs a carry C when the count reaches seven. This carry C is gate GT and flip-flop F
Enter in F. Therefore, a latch strobe rc is generated from the gate GT at the timing shown, and at its rising edge, the data shifted into the shift register SR at that time is latched into the latch circuit RCH. Data is continuously input one bit at a time from the modem to the shift register SR1 in synchronization with the transfer clock clkm. Therefore, after the data in the shift register SR is latched by the latch circuit RC:H, the next data d is transferred to the shift register SR in synchronization with the lock clkm. -d
7 are shifted in sequentially. Data dt is shifted into shift register SR,
Data d is output to the output terminals Q0 to Q. At the timing when ~d7 appears, a carry C is output from the counter CT. As a result, gate GT generates latch strobe rc, and latches the data d0 to d7 into latch circuit RCH. Also, at this time, flip-flop FF is set and outputs an interrupt request signal 1ntt to CPtJ. The CPU receives this interrupt request signal 10 and outputs the read strobe rs again, and the latch circuit RCH,
Data output from d. - Take in d7. In this way, the transmission/reception information input/output unit (2) converts the serial data output from the modem into 8-bit parallel data and outputs it to the CPU. Like the write strobe WSI in the transmission mode, the read strobe rs generated at this time may be generated anywhere within the period until the next latch strobe re occurs. Furthermore, if the processing speed of the CPU is fast and the read strobe rs, can be output within one transfer lock bit after accepting the interrupt request signal int, then the latch circuit RCH, is not needed. . Therefore, this example applies only when the transfer clock is extremely fast or when C
This can be said to be effective when the processing speed of the PU is very slow. Control signal input section This is the part where signals such as signals or status signals are taken into the CPTJ, and the multiplexer ML
The CPU is a data bus D. , D address bus A. , A, and are connected via a signal line 10S. The CPU periodically sends an input/output select signal i. S, and address signals a0 and al are output, and a signal input to a terminal of a multiplexer MLP that is selected based on these signals is connected to a data bus D. Alternatively, it is output on D1. *J* Signal output section , and an addressable latch circuit ARCH for outputting operation signals or display signals to input/output devices such as the original reading unit ■, the received image recording unit ■, the modem MDM, the network control unit NCU, and the operation display unit TOP. The CPU is configured with address buses A0 to A.
4, A5, and are connected via signal lines W S z, WS, , l03o. When the write strobe w s 3 is output from the CPU, the latch circuit RCH outputs the signal aO on the address bus.
- Latch a2, a4, and a6, and output the signals to the document reading section (2) to phase excite the pulse motor as described later. Further, when the write strobe w s is output from the CPU, the latch circuit 6 outputs the signal a that is output on the address bus at that time. , ai, a□, and a6 are latched, and the pulse motor of the received image recording section (■) is phase-excited. When the input/output select signal 10so is output from the CPU, the addressable latch circuit ARCH latches the signal a0 on the address bus 0, and
The latch signal a is outputted to a predetermined input/output device from the output terminal selected based on , ``'-a 3. The CPU executes the process shown by the comprehensive operation flow chart in Figure 14, and the process shown by the comprehensive operation flow chart in Figure 15 in the reception mode. will be explained below. In order for the transmission mode CPU to execute the processing shown in FIG. Each job A-
E is executed on a time-sharing basis. That is, at the time of transmission, the CPU receives, in addition to the interrupt request signal 1nte generated from the above-mentioned transmission/reception information input/output section (2), an interrupt request signal int and a synchronization signal S based on the synchronization signal S1 generated from the timing signal generation section (2). An interrupt request signal int based on the signal line INT, an interrupt request signal 1nta based on the synchronization signal S, and an interrupt request signal 1nta based on the synchronization signal S are inputted via the signal line INT. Work A-D according to the interrupt request signal jnt, ~int,
The priority order when performing is A>B>C>D,
Work E is always executed. The outline of tasks A to H performed by the CPU will be explained below with reference to the image data processing path diagram in FIG. [When an interrupt request is made by the task A1 interrupt request signal in t,
The CPU executes work A. Its work consists of the information storage section ■Line buffer area (RBF area) that stores image data (described later) in RAM■
Or memory empty flag M indicating that ■ is empty
EF I or ■ is the working area (WK area)
If it is set, the flag MEF I or ■ is reset and the data acquisition flag DRFI or ■ is set. Also, if the memory empty flag MEF+ or ■ is reset, the data import flag D
It is to reset RFI or ■. This data acquisition flag DRF I or ■ is referred to when performing tasks B and D described below. [Job B] When an interrupt request is made by the interrupt request signal intゎ, the CP
U accepts the interrupt request only when the data acquisition flag DRFi or ■ is set, and executes job B of advancing the sub-scanning pulse motor of the document reading section I by one step. However, depending on the sub-scanning line density, the timing to perform the work is slightly different, and in the case of a sub-scanning line density of 7.7 lines/-,
When flag DRF is set, interrupt request signal i
Interrupt requests are accepted every other time, and sub-scanning of 8 steps per line is performed. Sub-scanning line density 3.85 lines/w
In the case of ttr, when the flag DRF is set, an interrupt request is accepted every time the signal 1ntb is generated, and sub-scanning of 1 line and 16 steps is performed. The details of the work will be described later. Next, before explaining work C, work and E will be explained first. [Job D] When an interrupt request is made by the interrupt request signal 1nta, the CP
U performs the task. The content of the work is as shown in Figure 16, when the data import flag DRF I or ■ is set,
Original reading unit I7 - The read image data is transferred from the image information input unit ■ to the information storage unit ■ in 8-bit units via CPtJ.
It is stored in the line buffer area (RBF area) (2) or (3) of the RAM. However, the above is for the case where the sub-scanning line density is 7.7 lines/m, and the 5 sub-scanning line density is 3.85 lines/I! In the case of 111, the CPU also accepts the interrupt request by the signal 1nta, takes in one line of data by the interrupt by the signal int<, performs logical processing with the approximately line, and stores it in the line buffer area (RBF area) ■ or H Store in. After data capture is completed, the memory full flag MFFI or H is set. [Job E] This is a job normally executed by the CPU, and if the memory full flag MFF I or ■ is set,
Reset it, and as shown in +6cl, take in the data stored in 8-bit units from the line buffer area (RBF area), code it, and then store it in the FIFO area (described later) in the information storage section (■). . When the encoding process for l lines is completed, the memory empty flag MEFI or D is set. [Job C1 When the interrupt request by the interrupt request signal fntc goes down, the CP
U performs work C. Its job is to sequentially output the coded data stored in the FIFO area to the transmitting/receiving information input/output unit 8 bits at a time. Figure 17 shows an example of a time chart for each job A to H when the sub-scanning line density is 3.85 lines/m. . While performing the task E of encoding, the synchronization signal s
1 and S, the interrupt request signal int. and int, first, the data capture flag DR
Execute job A to set or reset F+ or
Return to Meanwhile, the transmitting/receiving information input/output unit (2) is serially outputting coded data to the modem, and as described above, generates an interrupt request signal 1ntc every time 8-bit data is outputted to the modem. When this interrupt request signal int is input to the CPU, the CPU
U interrupts work E and executes work C, which sets the coded 8-bit data in the FIFO area to the transmitting/receiving information input/output section (2), and returns to work E again. When the interrupt request signal int based on the synchronization signal S is received, the image data read by the document reading section 2 is stored in the line buffer area (RBF area) in 8-bit units, and the image data for one line is stored. Work E is suspended until all of are stored in the line buffer area (RBF area). Of course, during this time, the coded data is also transmitted and received by the information input/output section■
The job C to output to the modem MDM is being executed continuously, so data is output to the modem MDM without interruption. In other words, the FIFO area capacity is determined by the encoding processing speed, scanner speed, and modem rate, and is set to be at least the number of bits necessary to maintain the minimum transmission time in order to send data to the modem without interruption. The number of bits is set to 256 bits to allow for some margin. When the work is completed for the time being, the CPU returns to work E again.6 Next, when the interrupt request signal 1ΩL4 based on the synchronization signal st is applied, the image data read by the document reading section I is stored in the line buffer area (RBF area). At the same time, the previously stored image data is also extracted, the logical sum is taken, and the work stored in the line buffer area (RBF area) is performed. This will be explained below. 18th [i! (a) shows the operating procedure for job B in which the sub-scanning pulse motor of document reading section I is advanced by one step. As mentioned above, this work B is performed in the line buffer area (R
When it becomes possible to import data into the BF area),
A synchronization signal S that occurs at regular intervals. It is carried out based on. When the CPU accepts the interrupt request signal i n tb, it interrupts the work or E that was being executed up until then, and transfers the data that had been stored in each counter, register, etc. in the CPU to the RAM working area. Evacuate to (WK area). Next, change the pulse motor excitation pattern to the working area (
WK area) to the CPU and set it. In the case of this embodiment, a 1-2 phase excitation method is adopted for phase excitation of the pulse motor, and the control signal output section M shown in FIG.
As explained in , address signal a. ,al,a4,a,
is used as the phase excitation signal for the pulse motor. Therefore, when starting the system, set the pulse motor phase excitation pattern, for example, rl 1100000J, in the working area (WK area), and every time this work B is executed, that pattern is imported into Cp ll.
After bit circulation, address buses A6, A1, A4,
The pattern is outputted to the control signal output section Maki via A6, and the pattern is returned to the working area (WK area). As a result, as shown in FIG. 18(b), each time work B is executed, the pulse motor phase excitation pattern circulates one bit at a time, and the output a. , al, a4, ag are fIS18
As shown in Figure (C), the pulse motor can be driven one step at a time. After performing this work B, return to the work you were previously doing. Figure 19(a) shows the flow for transferring the image data read by the document reading section 2 to the image information input section 2 or the line buffer area (RBF area) of the information storage section 2 during work, as described below. It is a flowchart when 2-line OR processing is not performed. In this example, since the target is B4 size, 1
Although a case has been described in which pixel data of 2048 bits per line is handled, the number of bits per line is not limited to this. 2048 bits is 8 bits/byte, so it can be expressed in 256 bytes. As the line buffer area (RBF area), the first
Two IK×4 bits, that is, 1K×8 bits RAM addresses 16384 to 16896 are used as explained in FIG. That is, expressing this in hexadecimal code, as shown in FIG. 19(b), the line buffer (hereinafter simply referred to as RBF) area I is 4000000.
Address OFF address, RBF area U is 4 from address 4100
Use up to 1FF address. Also, the FIFO area is 420020 of RAM.
0 address 2FF address, working area (hereinafter simply W
(abbreviated as K area) is 430030 of RAM.
Addresses 0 and 3FF are allocated. Various flags, addresses for writing, successive output, etc. are stored in the WK area, and in explaining the flowchart below, it is assumed that the various initial settings have already been made and stored in the WK area. When the program in FIG. 19(a) is executed by the CPU, CPtJ checks the flag stored in the WK area to see if it is possible to input data into RBF area 1 or ■, and if one of the RBF areas is empty. When the data input is possible, the data stored in the WK area, R
The address at which data should be written to the BF area is set in the address register ADH in the CPU. Next, data of every 8 bits is transferred from the CPU to the corresponding address in the RBF area from the image information input section (2), and 1 is added to the address register ADH. Repeat this action 2 times per line.
After doing this 56 times, the lower 8 of the 16-bit address register
The bit becomes 0. That is, since one line of image data is stored in the RBF area at this time, a memory full flag MFF indicating that the RBF area is full is set in the WK area. When the sub-scanning line density is 7.7 lines/line, image data for one line is stored in a predetermined RBF area as described above. Figure 20(a) when the sub-scanning line density is 3.85 lines/sa.
, (L)), the logical sum of two lines of image data is calculated and a predetermined R is obtained as one line of image data.
Store in BF area. That is, in the case of odd-numbered line image data, as shown in the flowchart of FIG. 20(a), the image data of one line is transferred to, for example, the RBF area Store in. Next, when taking in the image data of the even numbered lines 8 bits at a time, as shown in the flowchart 201m(b), the image data of the odd numbered lines previously stored in the RBF area I are also taken out 8 bits at a time, and By redoing the logical sum and inputting it into the RBF area (2), one line of OR-processed image data is stored in the RBF area I. Next, in this way, the image data stored in the RBF area is extracted, converted into a run length code, and converted into a FIF
Figures 21 to 25 show the flow of work E stored in area O.
This will be explained with reference to the figures. In this embodiment, run length encoding is performed using the Modified Iuffman C
method). Of course, it goes without saying that a value encoding method may also be used. In the case of the Modify Hoffman method, the code is divided into a make-up code and a termination code depending on the run length. That is, the termination code is a code corresponding to the run length from θ to 63 as shown in Table 1 below,
The makeup code is a code corresponding to a run length that is an integral multiple of the ratio 64, as shown in Table 2. Also, as shown in Table 3, the synchronization code EOL consists of 11 "0"s and rl at the end.
” is added to the code. (Margins below) Table Table 3 Also, as you can see from the table above, each run length code is further divided into the WHITE code, which expresses white J, and the BLACK code, which expresses "black." . By the way, in order to create the termination code, 0~
The run length up to 63 is T, and the run length for creating the makeup code is 64 x M (M = 0.1.2
．． 3...), all run lengths RL can be expressed as RL=64XM+T. Therefore, T and M are sequentially found and extracted from the image data for one line, and predetermined coded data is extracted from the table stored in the ROM based on the T and M, and this is stored in the FIF○ area. By sequentially storing the data in , it is possible to perform run length encoding for each line. In the table in the ROM, a data block for extracting one coded data consists of 3 bytes, and the first byte uses the 4 bits to determine the code length. Run length encoded data is stored in the third byte. That is, as is clear from the above table, each code length is different, so when a predetermined run length code is extracted from the table according to a certain T and M, it is difficult to determine which part of the second and third bytes is valid data. is identified and extracted based on the code length of the first byte. Of course, the table configuration method is not limited to this. For example, as is clear from the table above, run length codes with a code length of 8 bits or more can also be used.
Since the bits above are "O", one data block is made up of 2 bytes, and by putting the coded data in the 1st byte and the run length code in the 2nd byte, It is also possible to extract a predetermined run length code depending on T and M. By the way, when performing line-by-line coding, it is a promise that a WHITE code is always issued after the synchronization code. That is, the first reference color of the line is determined to be "white". Therefore, if we start by encoding a "black" pixel,
Transmit a WHITE code with run length O. Figure 21 shows R of the work E that the CPU normally performs.
This figure shows a flow for extracting image data from the AM RBF area and obtaining a run length. As mentioned earlier, this work E is also performed in a time-sharing manner, so when starting this work, the CPU first performs the task E. The address for extracting 8-bit image data from the RBF area is brought from the WK area and set in the address register ADH in the CPU. Next, add 9 to the total code length counter TCLC.
Set 6's complement, bit counter BTCI to 8, T counter to 64's complement, and M counter to 0. BTCI is a 6T octal counter used when bit processing is used to find the change point if it exists in the 8-bit image data extracted from the RBF area.
The counter is an 8-bit configured counter to obtain the run length 1' from 0 to 63 when drawing the termination code table.
4 is set. The M counter is an 8-bit counter used as an argument for M when drawing the makeup code table. Note that the total code length counter TCLC will be described later. Next, it is determined in program step jSTI whether all of the 8-bit image data taken into the accumulator ACC of CPtJ is "O", that is, "white" pixel data. If the determination result in step JSTI is NO, the process moves to bit processing. That is, if the 8-bit image data taken out to the accumulator ACC contains "black" pixel information, the 8-bit image data is shifted by 1 bit by adding the contents of ACC to ACC. As a result, check whether a carry occurred (, that is, the change point from "white" pixel data to [black J pixel data) using the step knob J S T 2, and if the judgment result is YES, check the "white" pixel data. ”, and perform the second run length count described later.
The flow shifts to the flow for extracting predetermined coded data from the table, as shown in FIG. For example, if the first "black" pixel data of one line exists, the T counter remains at 0 and the process moves from step JSTI to step JST2 to the flow of extracting coded data shown in FIG. If the beginning of the 8-bit image data taken out to the accumulators A and CC, that is, 1 byte of data, is rQJ, the judgment result at JST2 is NO, and 1 is added to the T counter. That is, the "white" run length of 1-byte data is counted. As a result, check whether a carry has occurred from the T counter or not. In other words, when adding 1 bit to the T counter, the total number of additions is 6.
Step JST3 determines whether 4 bits have been reached. In this step, IS T 3 is the first "white" of the line.
This is not relevant when counting run lengths, but becomes relevant when the "black" run length encoding process is executed next and the "white" run lengths are counted again in the second flow. That is, as will gradually become clear from the following explanation, if there is a change point in the middle of the 8-bit image data taken into the accumulator ACC, the run length counting process of course first performs the counting process for the remaining part. After that, the next 1 byte is brought from the RBF area and counting is performed. Therefore, the T counter receives a fraction of 8 bits or less, so while bit processing is being performed, the T counter receives 1.
, the total number of bits input to the T counter is 6
There may be cases where the number exceeds 4 and a carry occurs. In step J Sr3, if the carry occurs, add 1 to the M counter for creating the makeup code, and
After setting the counter to the initial value, ie, 256-64, 1 is subtracted from BTCI to remember that the 1-bit counting process has been completed. 1” Even if you add 1 to the counter, 1 gear will not be activated (j
If so, immediately turn the counter BTC1 to 1, step BTC+ to ``0'', and press I.
Judge by ST4. Like step JST3, this step JSr1 is also related to the case of performing fraction processing of 8 bits or less. As long as the rounding is not completed, the above operation is repeated, and if there is a change point, the coded data is taken out (+), and a total of 64 bits are put in the T counter (f, 1 in the M counter). Add T counter

[Initial value, I! pchi, 64
Set the complement of . Step J Sr1 judgment result is YES, 1111chi,
When the bit counter BTCI becomes O, the bit processing for the fraction has been completed, and byte processing begins. Byte processing is YE with $1 cutting result force of step JSTI
This is done in the case of S. That is, if all 1-byte data is O, 8 is added to the tf and T counters, and the occurrence of a key 1) from the T counter is checked. As a result, if a carry occurs, initial setting is performed taking into account the fraction in the T counter. That is, the lower three digits of the T counter are left as they are, the upper digits are set to the complement of 64, and 1 is added to the M counter. If a carry does not occur in the T counter, the read address of the RFB area is incremented in order to accumulate the next 1 byte data from the RFB area (to the muller ACC).
RF address 0-4OFF or 4100-41FF
Since it is stored in the B area, when the 1-byte data is taken out from the RFB area, one line may end there. To check this, when the read address of the RFB area is incremented, step J
Judge by Sr6. If the determination result is No, the above operations are repeated. YE
If S, it means that all the image data for one line has been taken out from the RFB area and the run length counting process has been completed, so the process moves to the flow of reading the WHITE code from the table. FIGS. 22(a) and 22(b) are flowcharts for extracting the WHI-E code from the table based on the run-length counting results. First, check whether a makeup code is required. That is, the contents of the M counter are checked in step JSr7 to determine whether M=O or not. If the determination result is YES, there is no need to create a make-up code, and the process immediately begins creating a termination code. That is, based on the lower value stored in the T counter in the flow shown in FIG. 21, the table is looked up and predetermined block data is taken out. As described above, the block data extracted at this time has a 3-byte structure, the first byte contains the code length, and the second and third bytes contain the WHITE termination code. Therefore, first, this code length is put into the code length register CLR and added to the total code length counter CLC. This total code length counter TCLC is necessary to determine whether fill bit generation is necessary. That is,
As mentioned above, when transmitting one line of coded data, one line must be transmitted with a predetermined number of bits, for example, 96 bits or more, in order to guarantee the minimum transmission time. For this reason, if the hood compression rate of the image data of 1 ray and 2 minutes is high, it is necessary to add wild bits. Therefore, each time coded data is created according to the run length, the code length is accumulated and the code length for one line is monitored. The complement of 96 is set in this total code length counter TCLC when the flow shown in FIG. 21 is executed. Step J If the judgment result in Sr8 is YES, there is no need to generate a fill bit, so the non-fill flag NFF is set.
stand up. The coded data taken out from the table is transferred one bit at a time to the FIFO area of the RAM, and each time 8 bits of the data are transferred, it becomes possible to output the data from the FIFO area to the transmission/reception information input/output unit (2). As mentioned above, the FIFO area is RAM 4.
The 32 bytes below address 200 are used, and in order for the FIFO to function, there is also a write address register WAR1 that stores the address when writing 1 byte data there.
Read address register RAR that stores the address when reading 1-byte data, and bit counter BTCII that stores the number of bits written in 1-byte data when writing coded data bit by bit.
Is required. Through the joint work of these components, coded data is sequentially written to predetermined write addresses in the FIFO area, and the data written in the FIFO area is transferred from a predetermined read address to the transmission/reception information input/output section (1). It is read out one byte at a time. The write address and read address constantly cycle through 0 to 32, and data is written and read in the FIF area in an orderly manner. However, the conditions at this time are that (1) the write address must not overtake the read address in order not to destroy the data written in the FIFO area. Furthermore, in order to prevent the FIFO area from becoming empty, there are two conditions: (2) the write address must not be overtaken by the read address; if these two conditions are not satisfied, this embodiment becomes meaningless. In other words, the important point in this embodiment is that it is configured so that the above two conditions are always satisfied. Now, in step JSr1, it is determined whether coded data is currently being written to a predetermined address in the FIFO area, and if it is being written, data is removed from the table.
7. Write the next 1 bit of the output coded data to the FIFO area. If the determination result in step JST9 is YES, that is, not even one bit has been written to that address yet, it is determined in step JSTIO whether the read address and write address match. If the determination result is YES, that is, the read address matches the write address, writing of data is prohibited until data is read from that address to prevent data destruction. When writing to the FIFO area becomes possible, 1 bit of coded data is transferred and 1 is subtracted from bit counter BTCII. In step JSTII, it is determined whether the bit counter BTCII has become 0, that is, whether 8 bits of data have been entered at a predetermined address in the FrF○ area. If the determination result is No, 1 is subtracted from code length register CLR in order to monitor the number of bits transferred. In step JST12, it is determined whether the code length has become 0, that is, whether all coded data has been transferred to the FIFO. If the judgment result is NO5, that is, all of the coded data taken out from the table has not been transferred to the FIFO area, then the coded data is transferred to the 1-bit FIFO area again.
Repeat the above process for transferring to the area. At this time, if the judgment result in step JSTII is YES, that is, 8 bits of data have entered the predetermined address of the FIFO, the bit counter BTC is set to 8,
Add 1 to the write address register WAR to update the write address. As mentioned above, data is written to and read from the FIFO area endlessly, so once data is written to the final address of the FIFO area, the next data is written to the first address of the FIFO area. There must be. Therefore, when updating the write address, step JSTI
In step 3, it is determined whether the write address register WAR has overflowed, and if the determination result is YES, that is, there is an overflow, the start address is set in the write address register WAR. If the determination result is No, 1 is directly subtracted from the code length register CLR. Next, in step JST14, it is determined whether the code length register CLR has become O, that is, whether the transfer of all coded data has been completed. If the judgment result is NO1, that is, the process has not been completed yet, step JST determines whether it is possible to write the next data.
Determine based on IO and repeat the above process. When all the encoded data taken out from the table has been transferred, the initial value is set in the T counter. Next, in step JST15, it is determined whether the memory empty flag MEF is set. This flag MEF is activated when exactly 1 byte of the image data is extracted in the flow shown in FIG. 21 that extracts "white" image data from the RBF area and counts the run length. Set when data retrieval is finished. Therefore, if the last coded data of the l line is transferred to the FIFO area, the determination result in step JST15 becomes YES, and the flow shifts to the generation of the synchronization code EOL. On the other hand, if the determination result in step JST15 is NO, then the process moves to the flow of extracting "black" image data from the RBF area and counting the run length. The above is an explanation of the operation when the M counter is O.
If the counter is not O, that is, if it is necessary to create a make-up code, the process moves to the flow shown in FIG. 22(b) where a table is drawn using the contents M of the M counter as an address. The subsequent operation is the same as when creating a termination code.The code length is set in the code length register CLR, the code length is added to the total code length counter TCLC, and the occurrence of a carry is checked. sets the flag NFF to 1, and if it does not occur, the bit counter BTCn goes to O.
Check whether or not. As a result, when the bit counter BTCn is 0 and coded data is to be transferred to that address in the FIFO area for the first time, it is checked whether data can be written to that address or not, and the process waits until writing becomes possible. If coded data has already been transferred to that address, the next 1 bit is immediately transferred to the FIFO area. Meanwhile, the bit counter BTCI[ is used to check whether 8 bits have been transferred to the FIFO area, and the code length register CLR is used to check whether all the coded data at that time has been transferred to the FIFO area. I'm checking. When 8 bits of coded data is transferred to the FIFO area, that is, when the specified address of the FIFO area is
If it is filled with byte data, the write address is updated in order to transfer the coded data to the next address. At this time, if the previously transferred data is the final address of the FIFO area, the next data must be transferred to the first address of the FIFO area, so the first address is set in the write address register again.6M counter The above process is repeated until the process of transferring the makeup coded data taken out from the table to the FIFO area based on the content M of is completed, and when it is completed, the process shown in FIG. 22(a) above is repeated. Executes termination coded data transfer processing. In this way, once the compression process for the white J image data is completed, the compression process for the "black" image data will begin. FIG. 23 is a flowchart for counting the "black" run lengths and extracting T and M for this purpose. Since this flow is always entered after the flow shown in FIG. 21 described above has been executed, each register and counter contains a predetermined value based on the flow executed so far. That is, the T counter contains the initial value, the M counter contains O, the bit counter BTCl contains the remaining fractional bits when the flow in FIG. 21 is executed, and the CPU's accumulator A.
CC contains the corresponding [Black J image data. More precisely, when the counting of the "white" run length is finished in the flow shown in FIG. is shifted out, and the rest is held as is in the accumulator ACC. Furthermore, the number of bits remaining after removing the "white" pixel data from the 8-bit image data, ie, the number of bits of the "black" pixel data, is stored in the bit counter BTCI. Therefore, when executing the flow shown in FIG. 22 and moving to this flow, first, add 1 to the T counter, subtract l from the bit counter BTCI, and as a result, the bit counter BTCI becomes 0. In other words, in step JST1, it is determined whether or not the run length counting process for the fraction has been completed.
Judging by 6. If the judgment result is No, that is, there is still a fraction remaining, the contents of accumulator ACC are added to accumulator ACC, thereby shifting by 1 bit. In this case, since the run length of "black" is counted, if there is a change point, at that time the ACC is changed to "0".
” is shifted out. Therefore, in step JST+7, it is determined whether a carry rQJ has occurred, and if a carry [OJ has occurred,
Finish the run length count and send the coded data to FIF○
Shift to the process of taking it out to the area. If the determination result in step JST17 is NO, 1 is added to the T counter, and it is determined in step JST18 whether or not the value T exceeds 64. If the judgment result is YES, that is, it exceeds 64, then M
After adding 1 to the counter and setting the initial value to the T counter, 1 is subtracted from the bit counter BTCI. If it does not exceed 64 yet, immediately subtract 1 from the bit counter BTCI. As a result, whether the bit counter BTCI is 0 or not, that is,
It is determined in step JST19 whether or not the processing for the fraction has been completed. If the judgment result in step JSTI9 is No, that is, if the processing for the fraction has not been completed, the above operation of shifting the contents of the accumulator ACC is repeatedly executed. If the judgment result in step JSTI9 is YES, that is, the processing for the fraction has been completed, set 8 in the bit counter BTCI, add 1 to the read address register RAR,
Update the read address of the RBF area. As a result, it is determined in step JST20 whether a carry has occurred from the read address register RAR. If the judgment result is YES, it means that all the pixel data for one line has been taken out, so the memory empty flag MEF is set and the coded data is created based on T and M at that time. darn. If the judgment result in step JST20 is No, RB
One byte data is taken from the F area into the accumulator ACC of the CPU, and it is checked whether all of the pixel data is "1". If the determination result in step JST20 is YES, processing moves to each byte. If No, there is a change point within the 1-byte data, so the bit-by-bit process of adding the contents of ACC to the accumulator ACC described above is repeated again. When the process moves to byte processing, 8 is added to the T counter and whether or not a carry has occurred in step JST22, that is, 6
Determine whether the number exceeds 4 or not. If 64 is exceeded by adding 8 to the T counter, the excess is equal to the fraction processed in the first stage of this flow, and that value is set in the T counter as is. Therefore, in order to keep the fraction, leave the lower three digits of the T counter as is and set the upper digit to the initial value, that is, the complement of 64, and the T counter will store the counted value for the processed fraction. Ru. Next, after adding 1 to the M counter, 1 is added to the read address register RAR to update the read address in order to take in the next 1-byte data into the CPU again. In this way, after the result of counting the run length of "black" is obtained in the T counter and the M counter, a table is drawn using the values T and M as addresses, and the coded data of "black" is stored in the FIFO area. Figure 24 (a)
), the process moves to the flow shown in (b). The flow shown in Fig. 24 (a) and (b) is the same as the flow shown in Fig. 22 (a) and (b), except that the data retrieved from the table is replaced with "black" coded data. Since there is no difference in the processing procedure, detailed explanation thereof will be omitted. When executing the flowcharts in FIGS. 24(a) and 24(b), if all the coding processing for one line is completed, the process moves to the flow for creating the synchronization code EOL shown in FIG.
If the processing for 42 minutes has not been completed, the "white" coding processing will be performed again, so the process returns to the flow shown in FIG. 21 described above. Figure 25 shows the flow of creating the synchronization code EOL.As mentioned above, the synchronization code EOL is +149 O and 1.
Therefore, in order to count these 11 O's, a decimal counter is prepared and an initial value of 11 is set there. Next, if the number of encoded data for 1942 minutes is less than a predetermined number, it is necessary to add a fill bit before the synchronization code EOL, so it is checked whether the non-fill flag NFF is set. This flag NFF is set when the number of coded data exceeds a predetermined number when the flow of FIG. 22 or FIG. Start creating EOL. That is, "O" is transferred to the 1-bit FIFO area and 11
Subtract 1 from the decimal counter and use the FIF in step JST31.
It is determined whether the number of rQJs transferred to area O has reached 11. If the judgment result is No, bit counter BTCI
By subtracting 1 from T, it is determined in step JST32 whether 1 byte has been transferred to the FIFO area. If the determination result is No, that is, 1 byte has not been transferred yet, "0" is written again to 1 bit FIFO. Repeat the operation to transfer to the area. When 1 byte is transferred to the FIFO area, 8 is set in the bit counter BTCI[, 1 is added to the write address register WAR, and the 1-IF○ write address is updated. At this time, it is determined in step JST33 whether a carry has occurred from register WAR, and if the determination result is YES, an initial value is set in register WAR. After that, in step JST34, it is determined whether or not writing to the FIFO area is possible by checking the match between the write address and the read address, and if writing is possible, "0" is transferred to the 1-bit FIFO area again. Repeat the process. By the way, if the judgment result in step JST30 is No, that is, it is necessary to add a fill bit, then in the next step JST35, whether to add a fill bit, that is, "0" to the new FIFO write address, or if the data is already halfway If the fill bit is to be written to a new address, it is determined in step JST36 whether or not it is possible to write to that new address. 0” as FIFO
Transfer to area. At this time, 1 is added to the total code length counter TCLC, and it is determined in step JST37 whether the result has reached a predetermined number of bits. If the judgment result is No, that is, the predetermined number of bits has not yet been reached, subtract 1 from the bit counter BTCII,
In step JST38, it is determined whether one byte of data has entered a predetermined address in the FIFO area, and if it has not, the operation of transferring "0" to that address is repeated. If 1 byte is transferred to that address, the bit counter BTCn is set to 8 and the write address register WA
Add R1:1. In step JST39, it is determined whether or not a carry has occurred from the register WAR at that time. If a carry has occurred, the data has been transferred to the final address of the FIFO area, and the next 1-byte data will be at the beginning. Since the data must be transferred to the address, the initial value, ie, the start address, is set in the write address register WAR. In this way, the fill bit, i.e. rQJ, is set to FIF○
When the total code length reaches a predetermined number by transferring one bit to the area, the judgment result in step JST37 becomes YES, and in order to add the synchronization code EOL after that, 11 O's are transferred to the FIFO as described above. Transfer to area. As a result, since the determination result in step JST31 is YES, the bit counter BTCII is also subtracted by 1. At this time as well, 1 is placed at the specified address in the FIFO area.
Whether or not a byte was transferred; if so, whether it is necessary to return the address to the first address when updating the address; and whether the next data can be written to the updated write address in the FIFO area. Kawo step JS
After making a judgment at T40 to JST42 and performing processing based on the judgment result, the last l of the synchronization code EOL is set to FI.
Transfer to FO area. After the transfer, 1 is decremented from bit counter BTCII, and counter B is decremented in step JST43 in the same manner as described above.
After determining whether it is necessary to set TC■ to 8 and whether or not it is necessary to return the write address to the first address of the FIFO area in step JST44, and performing processing based on the determination results, the next step is In order to perform the encoding process for one line, the process returns to the flow shown in FIG. 21. As described above, the image data stored in the RBF area is taken out one byte at a time into the CPU, compressed, and then stored in the FIF area. Figure 26 shows the information input/output section for transmitting and receiving coded data stored in the FIFO area one byte at a time.
This figure shows the operating procedure for job C to be transferred to. As mentioned above, this job C is executed by the interrupt request signal 1□ltc generated from the transmitting/receiving information input/output section ■ every time the 8-bit data transferred to the transmitting/receiving information input/output section ■ is serially output to the modem. Ru. This interrupt request signal, int, increases the transmission rate by 4, for example.
In the case of 800 bps, 8/4800 (se
c) = 1°6 (sec). When the interrupt request signal 1nLe is generated, the CPU interrupts the work or E that was being executed up to that point. The data that had been stored in each counter, register, etc. in the CPU up to that point is saved to the WK area of the RAM. Next, the read address of the FIFO area is brought from the WK area and read address register RAR of the CPU is read.
, transfers 1 byte of data from that address in the FIFO area to the transmission/reception information input/output unit (2), and adds 1 to register RAR to update the read address. As a result, as in the case of writing data to the FIFO area described above, a carry occurs from register RAR, and F
If the final address of the IFO area is exceeded, set the initial value in register RAR, and then write register RAR again.
If no carry occurs from AR, the address is stored in the WK area. Thereafter, the previously saved data is returned to the CPU and the process returns to the previous work or E. The comprehensive operation flow performed by the CPU when receiving data in the receive mode has already been shown in FIG. do. That is, at the time of reception, the CPU receives an interrupt request signal i n t generated from the transmission/reception information input/output unit 2 explained in FIG. 11 above.
, an interrupt request signal 1nLt based on the synchronizing signal S generated from another timing signal generating section (2) of , and an interrupt request signal 1nth based on the synchronizing signal S are inputted via the signal line INT. The priority order when performing work in response to the interrupt request signals 1n11 to jnth is F>G>H, and work I is always executed. Next, an outline of these tasks F-1 will be explained with reference to the image data processing path diagram in FIG. 27. [Work F1 When an interrupt request is made by the interrupt request signal int, CP
U performs work F. Its work consists of the memory full flag MFFI indicating that one line of decoded pixel data has been stored in the RBF area of the RAM (or
If is set, reset the flag MFF and set the data read flag DRF + or ■
is set, and if the memory full flag MFFI or ■ has been reset, that flag MFF is reset. This data read flag DRF I or D is referred to when performing work H described below. [Work G] When an interrupt request is made by the interrupt request signal int, CP
U performs work G. As shown in the image data processing path diagram in FIG. This involves transferring bit data, ie, 1-byte data, to the FIFO area mentioned above and writing it to a predetermined address. The received image data transferred to the FIFO area is decoded into pixel data in the next step (2) and transferred to the RBF area for storage. [Job I] This is a work normally executed by the CPU. If RBF area I or n is empty and the memory empty flag MEFr or ■ is set, after resetting it, the F
Image data is taken into the CPU from the IFO area, decoded, and the decoded image data is sequentially transferred to the RBF area and stored. When decoding for one line is completed, the presence or absence of an error in the received image data is checked, and if there is no error, the memory full flag MFFI or ■ is set. [Work H] When an interrupt request is made by the interrupt request signal int, the CP
U is the data read flag DRF! Alternatively, only if ■ is set, the interrupt request is accepted and job H is executed. Its job is to advance the sub-scanning pulse motor of the received image recording section (2) by one step, and to output the image data decoded in 8-bit units from the RBF area to the 256-bit received image output section (2). . However, the timing at which the job is performed differs somewhat depending on the sub-scanning line density, and when the sub-scanning line density is 7.7 lines/m, when the flag DRF is set, the signal 1nth
The pulse motor is advanced by one step for each interrupt request, and one line of image data is output to the received image output section m after eight interrupts. When the sub-scanning line density is 3.85 lines/III+, when the flag DRF is set, the signal j n
Interrupt requests are accepted every other time in th, and the pulse motor is advanced by one step, while one line of image data is successively outputted twice to the received image output section m by the 16 occurrences of the signal 1nth. FIG. 28 shows an example of a time chart for each job F to ■ when the sub-scanning line density is 3.85 lines/m.
For example, synchronization signals S1 and S are generated while the CPU is executing task (3) in which image data is fetched in 8-bit units from the FIFO area, decoded, and sequentially transferred to the line buffer RBF area. When the signal int and 1nth interrupt request is received, first, work F is executed to set or reset the data read flag DRF, and then the sub-scanning pulse motor is advanced by one step, and the data is decoded from the RBF area. A job H is executed to output the received image data to the received image output section m. During this time, the received image data is serially input from the modem MDM to the transmitting/receiving information input/output unit (■), and as mentioned above, every time 8-bit data is input there, the transmitting/receiving information input/output unit (■) sends an interrupt request signal. generates int. When this interrupt request signal int is input to the CPU, the CPU
U interrupts work H or ■ and sends/receives information input/output unit■
Execute job G to transfer the 8-bit data input to the FIFO area. After finishing this work G, return to work H or I again. By 8 interrupt requests by the interrupt request signal intwa,
After outputting one line of image data from the RBF area to the received image output section m, the same one line of image data is outputted to the received image output section m again for each interrupt request of signal 1nt7, and the received image recording section ■ Now, write the image data twice. Next, we will explain the more detailed processing procedure of the work explained above in the second section.
This will be explained below in Figure 9. FIG. 29 is a flowchart of job G that transfers 8-bit data inputted from the modem MDM to the transmission/reception information input/output unit (■) to the FIFO area. As mentioned above, the transmission/reception information input/output unit
When 8-bit data is input to the interrupt request signal int,
occurs. This interrupt request signal int is also the same as in the transmission mode.
For example, if the transmission speed is 4800 bps,
Occurs every 8/4800 (sec) = 1.6 (msec). When this interrupt request signal intg is accepted, the CPU interrupts the work H or I that it was doing up to that point and starts this work. That is, in order to make the contents of counters, registers, etc. used in the program that was being executed up to that point available for use when returning to that program, the CPU
Evacuate to AM WK area. It also fetches the write address of the FIF○ area from the WK area and sets the address register ADR in the CPU. Next, the 8-bit data input to the transmission/reception information input/output unit (2) is taken in, transferred to the PIF, O area, and written into that address. After the transfer, add 1 to address register ADH and check whether a carry has occurred. If a carry occurs, the above 1-byte data has been written to the final address of the FIFO area, and the first data must be written to the first address of the FIFO area, so set the initial value in the address register ADR. and store this in the WK area. Furthermore, if no carry occurs, the write address is stored in the WK area as is. After that, in order to return to the previous work, the previously saved contents are set back into the CPU. In this way, the coded data stored in the FIFO area is then decoded in job I. FIG. 30 shows the flow for extracting the run length (binary number) by looking up a table based on the received coded data in the task (2). When entering this flow, the CPU first initializes the registers, then checks whether it is possible to take out coded data from the FIFO area, and if the data is stored in the FIFO area and can be taken out. , the data is taken into the data register DR+ in the 8-bit CPU. When drawing a table based on coded data and comparing the run lengths corresponding to the coded data, in this embodiment, as described later, if the first bit of the coded data starts with 1, the first bit is 0. If 1 comes in the 2nd bit, 0 up to the 2nd bit and 1 in the 3rd bit, then...
A table is constructed for dividing codes and BLACK codes into groups and extracting run lengths corresponding to the codes. Therefore, now from the FIFO area, data register DR,
Since it is necessary to check how many O bits are added to the beginning of the coded data taken in, an O counter is prepared for this purpose. As is clear from the above, the O added to the beginning of the coded data has a maximum of 7 bits. If 8 or more bits of O are added, the code is a synchronous code. Therefore, the 0 counter is initially set to 8. Next, in order to check how many bits of O are added to the beginning of the coded data in data register DR, the coded data in data register DR is transferred to accumulator ACC and shifted by 1 bit. The shifted and extracted carry is stored in a 1-bit memory. Furthermore, since the coded data shifted by one bit needs to be taken out and examined one after another, it is returned to the data register DR and stored. At this time, it is necessary to remember how many bits of coded data have been extracted, so 1 is subtracted from the bit counter BTCII, which is set to 8 in the initial setting. 8 of the coded data taken into the data register DR.
If all bits have been taken out, it is necessary to take in the next 8 bits to the data register DRt.
In that case, the subroutine FIFOR shown in FIG.
Execute EAD. After that, first shift the encoded data by 1 bit, check whether the carry taken out is rOJ or r14, and select rl.
In the case of J, the process moves to a flow for pulling the table and taking out the run length. If the carry is "0", the O counter is decremented by 1, and if the count value is 7 or less, the coded data is shifted again and the flow of counting the number of rQHs is repeated. In this case, if there are 8 consecutive bits of "0" at the beginning of the coded data, the result of subtracting ] from the O counter will be O, and we know that the coded data is a synchronous code.
Check for errors in received data. In this case, if rQJ continues for 8 bits at the beginning of the coded data, the O counter will be 1.
The result of subtraction is 0, which indicates that the coded data is a synchronization code, so check the received data for errors. If a carry rlJ occurs by shifting the 9-coded data that performs the return code detection operation, program step 5T50 is executed to draw the first table T1 using the contents of the 0 counter as an address. The table is divided into two, one for extracting the run length corresponding to the coded data of "white" and the other for the coded data of "black". The structure of the table in the case of `` is as shown in FIG. 30(b). That is, it consists of a first table T1 and a second table T provided in a predetermined area of the ROM, and the first table T has addresses 1 to 8.
Second table T! WHff~W indicating the start address of
H, is stored. The second table T1 is divided into blocks for each number of 0 bits added to the beginning of coded data, and each block contains data necessary to extract the run length corresponding to the coded data. ing. 1!30 (c) shows the second table T when only the first bit of the encoded data is O, that is, the table from addresses WH1 to WH. Hereinafter, in explaining the flow from program step 5T50 onward in step 30S(a), we will take as an example the case where the run length of coded data in which only the first bit is O is extracted, and FIG. 30(b), ( This will be explained with reference to table C). In the flow up to step 5T50, the coded data is shifted by 2 bits "0.1", the content of the O counter is 7, and the content of the bit counter BTCm is 6. Therefore, in step 5T50, the first Data WH, can be taken out from address 7 of table T1.Next, in steps 5T51 and 5T52, data 2 is taken out from address WH, of second table T, based on the data, and data 2 is transferred to data register DR1. The reason why 2 is included in the address WH of the second table T2 will become clear from the following explanation.
As can be seen from Table 1.2 above, when "0.1" appears at the beginning of coded data, the number of data bits that follow is always 2 or more. That is, the coded data starting with ro and IJ is 4 bits or more. In step 5T53, the data register DR2 is cleared in order to input predetermined data in the following step. Next, in step 5T54, the contents of the data register DR are shifted to the accumulator ACC, and in step 5T55, the shifted data is returned to the data register DR, and at step 5T56, it is transferred to the previously cleared data register DR. , and inputs the shifted 1-bit data. As a result, the coded data in the data register DR has been shifted to 3 bits, so in order to store it, the bit counter BTC is shifted in step 5T57.
Subtract l from II. The judgment result of judgment step 5T58 is NO, and step 5
Proceeding to T59, steps 5T54 to 5T59 are repeated again. Therefore, when step 5T59 is executed for the second time, data for the remaining 4 bits of the coded data is stored in the data register DR, and data for the 3.4th bit of the coded data is stored in the data register DR. and also
The contents of bit counter BTC■ are 4, data register D
Rs is O. As a result, the judgment result at step 5T60 is YES,
The process moves to step 5T61. In step ST61, the contents of the data register DR2 are added to the second table address WH, and in step ST6
At 2.5T63, 1 is further added to the addition result and the second table is drawn. For example, the 3rd and 4th bits of the coded data are “Ol
o”, that is, if o, then WH, +. , , rQ, 1'', then W H+-1-t, r 1, O'', data a, b, respectively from the addresses of W H, , , ,
Take out c. Also, if the 3rd and 4th bits are rl and IJ, then WH1
Extract data from address +3.1. The coded data at this time is ``rO,l,1.1'', which is coded data with a run length of 2, as is clear from the above description. Therefore, at the address of W H, , , , the run length is "2", the code T=rOJ indicating that the run length is the run length of the termination code, and the run length are found, so the code "2" indicating the end of table reference is found.
1" is stored. That is, the predetermined address of the second table has the information shown in FIG.
), the run length (binary number) RUN corresponding to the coded data (however, if the coded data is a makeup code, the number obtained by dividing the corresponding run length by 64) is the run length for the termination code. A code T/M indicating whether it is a length or a run length for a make-up code and a code "1" indicating the end of table reference are stored, and these codes will be used in later program steps. In step 5T64, the extracted data is shifted by 1 bit in order to check whether the table reference is completed, and in step 5T65, it is determined whether the carry "1" has occurred. As a result, for example, if the 3.4th bit is "1, ■" and data is extracted from the address W Hl 03+ 1, a carry "1" will occur, so based on the run length, one bit at a time will be Subroutine RUNLENGTH5TORE that transfers pixel data to the RBF area
Execute. Also, for example, the 3.4th bit is ro, OJ and the address W Hl+. If data a is taken out from or to register ADR, the carry is rOJ, so the process returns to step 5T52. Returning to step 5T52, this time, as a result of drawing the second table using the contents a of register ADR, 1 is found in data register D.
Set to R3. Therefore, in step 5T56, the fifth bit of the coded data is taken out into the data register DR, and in step 5T63, the data at address a+0+1 or a+1+1 is taken out into the register ADR, depending on the contents. Thereafter, the same operation is repeated, and if all 8 bits of data stored in the data register DR are shifted out during that time, the judgment result at step JST5g is YES.
Therefore, the subroutine FIFOREAD transfers the next data from the FIFO area to the data register DR.
Execute. FIG. 31 shows the flow of the subroutine FIFOREAD. When this flow is entered, the C
Evacuate various data stored in the PU. Next, data is read from the FIFO area, but in this case as well, as explained in the transmission mode above, the conditions for transferring data to and from the FIFO area are as follows: In order not to destroy data, (1) the read address must not overtake the write address. Furthermore, in order to prevent the data in the FIFO area from becoming empty, there are two conditions: (2) the read address must not be overtaken by the write address. Therefore, it is checked whether the read address and write address of the FIFO area are equal or not, and the data is transferred from the transmission/reception information input/output section (■) to the FIFO area, and the data is read out until the judgment result in step JST66 becomes No. is prohibited. If the determination result in step JST66 is No, the initial value 8 is set in the bit counter BTCn in case the process returns to the flow shown in FIG. 30(a). Next, take out 1 byte of coded data from the FIFO area, store it in the data register DR, and store it in the FFO
Update the area lead address. At this time, it is determined in step JST67 whether or not it is necessary to reset the read address to the first address.
If there is no need to do so, leave it as is; if necessary, set the initial value in the read address register and return the previously saved data in the CPU to its original state, as shown in Figure 30 (a). ) Return to the flow. Figure 32 shows the subroutine RUN LENGTH3T.
This shows the flow of ORE. First, while saving various data in the CPU, initial values of various data are set by extracting data necessary for executing this flow from the WK area. Next, when the flow shown in FIG. 30(a) is executed, it is determined whether the run length shifted by 1 bit in step 5T64 and stored in the register ADR corresponds to a termination code or a makeup code. To check, shift by 1 bit again. As a result, if T=rOJ is shifted and a carry "O", that is, a carry "l" does not occur, the judgment result in step JST68 is NO, and the run length stored in the register ADR corresponds to the termination code. , the flow shifts to the flow of generating the pixel data and transferring it to the RBF area. If the determination result in step JST68 is YES, the register ADR stores the numerical code obtained by dividing the run length corresponding to the makeup code by 64, that is, the makeup run length M, as described above. A flow begins in which pixel data 64 times the value is generated and transferred to the RBF area. That is, the make-up run length of register ADH is M
Set it on the counter. Next, it is determined in step JST69 whether byte processing is possible or whether bit processing must be performed. In other words, when executing this flow, if the pixel data transferred to the RBF area is less than 8 bits, the fractional bits must be transferred first to fill the address with 8-bit data. Must be. The fractional bit number is stored in the bit counter BTCI. Therefore, in step JST69, the bit counter BTCI
Judge whether or not is 8, and the judgment result is Y I-. If S, byte processing is performed; if NO, bit processing is performed. In the case of byte processing, it is determined whether the data to be processed is "white" or "black" in step JST7o, and if it is "white", the flow described below is performed, and if it is "black", the flow described below is performed, and if it is "black", the data to be processed is "r black".
A flow is executed in which 8 bits of pixel data are generated and transferred to the RBF area, but the flow is the same as in the case of "white" described below, except that the pixel data to be generated is different. Therefore, detailed explanation thereof will be omitted. When bit processing is started, it is determined in step JST71 whether the data to be processed is F white J or black J.As mentioned above, when data is sent from the transmitting side,
Since "white" coded data is always sent after the synchronization code EOL, execute the flow shown in Figure 30(a), draw a table based on this coded data, and find the corresponding run length. When the IJ is taken out, the first run length is "white", and thereafter there is no change in color in the case of make-up run lengths, but a color change occurs each time a termination run length is taken out. Therefore, when the contents of register ADR are shifted in step JST68 to determine the occurrence of carry rl, carry rQ)
By storing the color change that occurs each time the run length occurs, it is possible to determine in step JST71 whether the run length is "white" or "black." If the judgment result in step JST70 is "black", "
A flow of generating black J pixel data and transferring it to the RF3F area is executed, but since the flow is almost the same as the case of "white" described below, detailed explanation thereof will be omitted. If the judgment result of step JST7+ is "white", R
The 8-bit data of the address in the BF area where the pixel data fraction bits are to be written is once taken into the accumulator ACC of the CPU. Next, the contents of accumulator ACC are shifted by one bit by adding the contents of ACC. As a result,
After the pixel data of 8 bits or less that was previously stored in the accumulator ACC, the fractional white pixel data rQ is added.
J enters 1 bit. As a result, one bit of the fraction has been processed, so 1 is subtracted from the bit counter BTCI, and it is determined in step JST72 whether or not the processing of the fraction has been completed. If the judgment result in step JST72 is NO and the processing for the fraction has not yet been completed, the operation of shifting the contents of the accumulator ACC and inserting "0" therein is repeated. When the bit counter becomes O and all rQJs are included in the fraction, the contents of the accumulator ACC are transferred to the RBF area and the write address of the RBF area is updated. As a result, bit processing is completed and byte processing can be performed from the next address, so first, an initial value of 8 is set in the T counter. After that, the contents of accumulator ACC are all [O
”, transfer it to the RBF area, update its write address, and subtract 1 from the T counter.
Repeat times. When the judgment result in step JS73 is YES, that is, 64 bits of pixel data has been transferred to the RBF area,
Subtract 1 from the M counter. As a result, it is determined in step JST74 whether the content of the M counter has become O or not, and if the determination result is No, 8 is set in the T counter again. Transfers 64 bits of "white" pixel data. If the determination result in step JST74 is YES, that is, all the "white" pixel data of the run length corresponding to the makeup code is transferred to the RBF area, the bit counter BTCI is corrected. That is, the run length corresponding to the makeup code is 8.
Since it is a multiple of 0, when pixel data of that run length is generated and stored in the RBF area, the pixel data written to the last address is bit-processed from the 8 bits to the first address. The bits obtained by subtracting the written fraction are valid pixel data. Therefore, when the pixel data of the termination run length is transferred to the RBF area next time, the contents of the bit counter BTCI are returned to the first fraction in order to remember how many bits of pixel data should be input to that address. . After storing it in the WK area, the CP that was evacuated first
Set the various data of U to the original state again and see Figure 30 (
Return to the flow of a). Returning to the flow in Figure 30 (a), when the run length is retrieved from the table as described above, the termination run length is retrieved to the register ADR after the makeup run length, so the process in step JST68 is performed. If the determination result is NO, the flow shifts to generating pixel data of that termination run length and transferring it to the RBF area. FIG. 33 shows the flow, and the register AD
Check whether the run length in R is O. If the judgment result in step JST75 is YES, that is, if the run length is O and there is no need to transfer the pixel data to the RBF area, after returning the various data in the CPU that was saved earlier to its original state, Return to the flow of a). If the determination result in step JST75 is No, a fraction check is performed on the data in the address from which data is to be transferred in the RBF area. Therefore, say whether the bit counter BTCI is 8 or not.
The determination result in step JST76 is YES. That is, if the fraction is O and it is possible to write 8-bit data to that write address, it is checked whether the pixel data to be generated is "black" or "white" and the process moves to the byte processing flow. The byte processing for "black" is explained below, but for "white"
In the case of , almost the same processing as in the case of "black" is performed, so the details will be omitted. If the judgment result in step JST76 is No, that is, if the previously transferred data is 8 bits or less, first bit processing is performed to transfer fractional bits to that address to make it 8 bits. For this reason, first, it is checked whether the pixel data to be generated at that time is "white" or "black", and if the judgment result in step JS777 is "white", "white" pixel data is generated. , the flow moves to transfer it to the RBF area. This flow is carried out in almost the same way as in the case of "black J" described below, so the details are omitted. If the judgment result in step JST77 is NO, the data in the address to be transferred from among the pixel data is taken into the accumulator ACC.Next, 1 is set in the 1-bit memory, and the data in the accumulator ACC is shifted by 1 bit via the 1-bit memory.As a result, the previously written 8-bit pixel is stored in the accumulator ACC. One bit of the data is rewritten to "black" pixel data "1" to be written this time and stored. Now that the process of generating pixel data of fractional 1 bit is finished,
Subtract 1 from the bit counter BTCI. As a result, it is determined in step JST78 whether or not the bit counter has become 0. If the determination result is NO1, that is, there are still fractional bits to be processed, the register AD
I is subtracted from the run length in R, and it is determined in step JST79 whether or not all termination run length processing has been completed. If the determination result in step JST79 is NO, the process of shifting the accumulator ACC again and inserting 1 bit of "black" pixel data is repeatedly executed. If the determination result in step JST79 is YES, that is, if the pixel data generation process for the termination run length is completed before the fraction processing is completed, the contents of the accumulator ACC are transferred to the write address of the previous RBF area. Thereafter, the write address and the contents of the bi-soto counter BTCI are stored in the WK area, the internal state within the CPU is returned to its original state, and the process returns to the flow shown in FIG. 30(a). If the fraction processing ends before the termination run length processing is completed, and the extracted pixel data contains "black" pixel data corresponding to the fractional bits in the accumulator ACC, and the accumulator ACC is filled with the specified data. , the judgment result of step JST78 is Y.
ES and the contents of its accumulator ACC as RB
Transfer to F area and subtract 1 from termination run length. Next, the judgment result at step JST80 is NO1, that is,
If the termination run length processing has not yet been completed, the write address in the RBF area is updated by one and the process moves on to byte processing. If the determination result in step JST80 is YES, the bit counter BTCI is set to 8, the write address in the RBF area is updated by one, and then they are stored in the WK area. After that, the internal state inside the CPU is restored to its original state as shown in Figure 30 (
Return to the flow of a). When byte processing is started, accumulator ACC
8-bit all rlJ is set in , and transferred to the RBF area. Next, 8 is subtracted from the termination run length, and it is determined in step JST81 whether or not the result is O. If the judgment result in step JST81 is YES, RB
Since the termination run length processing has been completed with exactly 8 bits of pixel data written to the write address of the F area, the bit counter BTC
Set I to 8 and update the write address by 1. Thereafter, the data is stored in the WK area as described above, the internal state of CPtJ is restored to its original state, and the process returns to the flow shown in FIG. 30(a). If the determination result in step JST8] is No. In step JST82, if the result of subtracting 8 from the run length is positive or negative, that is, its sign is "0" or "l".
”. If the determination result in step JST82 is NO, that is, if there is still a run length remaining, the write address is updated, and then the process of transferring the "black" pixel data to the 1-byte RBF area is repeated. If the judgment result in step JST82 is YES, that is, the pixel data longer than the termination run length is transferred to the RBF.
When pixel data is transferred to that address in the RBF area, set the bit counter BTCI to the fractional number in order to remember how many bits should be inserted the next time pixel data is transferred to that address in the RBF area. . At this time, extra "black" pixel data is written to that write address in the RBF area, but as is clear from the above explanation, it will be replaced by the next pixel data, so there will be no effect. No inconvenience will occur. After correcting the bit counter BTCI, the write address is updated, the data is stored in the WK area, the internal state of the CPU is restored, and the process returns to the flow shown in FIG. 30(a). By the CPU executing the job I explained above,
The data stored in the FIFO area is stored one byte at a time in C.
The data is taken into the PU, decoded, and stored in the RBF area. The pixel data stored in the RBF area is then sent to the CPU
When executing work H in response to the interrupt request signal 1ntb described above, the received image is taken out to the received image output section (2), further transferred to the received image recording section (2), and recorded on recording paper. FIG. 34 shows the flow of transferring pixel data in the job H to the received image output unit m. When entering this flow, the CPU first performs the following process as shown in Figure 5 (a).
, the thermal element segment selection data explained with reference to (b) is taken out from the WK area and set in register R. As mentioned above, the segment selection data is data that sequentially selects the 8 segments of the thermal element, so at the time the first segment of the line is selected, the WK area contains "0, O, O, O50. ,0,Oll
' is stored. Next, the initial value 32 is set in the byte counter BYC. As mentioned above, this means that the data for one segment is 256.
This is because it consists of 32 bits, that is, 32 bytes, and in order to set the image data in the received image output section m, it is necessary to process 8 bits each 32 times. Also, the read address of the RBF area is extracted from the WK area and set in the CPU. Next, 1 byte data is taken into the accumulator ACC from that read address, and it is output directly to the reception image output section, and the read address of the RBF area is updated.Since the 1 byte transfer process is completed, the byte counter BYC Subtract 1 from. By repeating this transfer process 32 times by the CPU, data for one segment is set in the received image output section m. At this time, the byte counter B Y C becomes 0, so next the segment selection data is transferred from the register R to the accumulator ACC, and further transferred to the received image output section m. Now, the pixel data and segment selection data for 1 segment have been set in the received image output section (■), so next, CP (J is the write strobe W S for generating the power enable described above). 2 to the received image output unit m. As a result, the thermal element operates as described above, and the received image recording unit 2 records 1 segment i·. The CPU again starts the next job H. In preparation for the interrupt, the segment selection data is shifted by 1 bit, and after that data and the read address of the RBF area are saved in the WK area, the process returns to the work before the interrupt. Work I when performing ：h with a receiver (In addition to the data transfer process described above, there is a process to output a phase excitation signal to the sub-scanning pulse motor of the received image recording unit ■, but this is described above) Figure 18(a)-(
Since this is the same as the case in the transmission mode explained with reference to C), detailed explanation thereof will be omitted. In the transmission mode, the CPU executes the above tasks F to I, thereby decoding and recording the received image data to obtain a copy of the original. In the above embodiment, various registers, counters, etc. required for the CPU to perform each job are stored in the CPtJ.
Although we have explained the case where these registers are provided in
It goes without saying that a counter or the like may be provided outside the CPU. Further, in the above embodiment, the case where a public line using a modem is used has been described, but it is clear that the invention can also be applied when a digital line is used. Further, in the above embodiment, a case has been described in which data processing is performed by an 8-bit CPU, but the present invention is not limited thereto, and can be applied to, for example, a 16-bit, 4-bit, 32-bit, or bit slice CPU. However, it goes without saying that it can be processed in the same way. Furthermore, the configurations of the document reading section (2) and the received image recording section (2) in this embodiment can be arbitrarily designed. For example, the document reading section I may be one that extracts pixel data from an image lease such as a magnetic tape or a memory, and the received image recording section (2) may be a computer. Furthermore, the receiving device or the transmitting device itself may be a computer or a storage/forwarding device.As explained above, according to the present invention, the buffer device, KOG, decoder device, communication control device, etc. in the conventional device can be used. Since the hardware part is replaced with a microcomputer, the configuration becomes extremely compact and a facsimile machine can be obtained at a very low cost.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a conventional facsimile machine, in which (a) is a block diagram of its transmitting side, (b) is a block diagram of its receiving side, and FIG. 2 is an embodiment of the present invention. System block diagram of the facsimile machine according to the third
The figure is a specific configuration diagram of the document reading section l in Figure 2, and
Figure (a) is a specific configuration diagram of the image information input unit (■) in Figure 2, Figure 4 (b) is a time chart for explaining its operation, and Figure 5 (a) is the received image in Figure 2. Output part m
5(b) is a time chart for explaining its operation. FIG. 6(a) is a specific configuration diagram of the received image recording section (2) in FIG. ) is shown in Figure 6 (
A specific configuration diagram of the thermal element SE in a),
7 is a specific configuration diagram of the micro, processing, and unit section (CPU) V in FIG. 2, FIG. 8 is a specific configuration diagram of the timing signal generation section ■ in FIG. 2, and FIG.
The figure is a specific configuration diagram of the control program storage section ■ in FIG. 2, FIG. 10 is a specific configuration diagram of the information storage section ■ in FIG. 2, and FIG. The specific configuration diagram of section ①, Figure 1I (b) is shown in Figure 11 (
FIG. 11(c) is a time chart for explaining the operation in the receiving mode of FIG. 11(a),
FIG. 12 is a specific configuration diagram of the control signal input section X in FIG. 2, FIG. 13 is a specific configuration diagram of the control signal output section ℃ in FIG. FIG. 15 is a comprehensive operation flowchart for explaining the operation of the facsimile apparatus in the transmission mode; FIG. 15 is a comprehensive operation flowchart for explaining the operation of the facsimile apparatus in the reception mode according to an embodiment of the present invention; FIG. An image data processing path diagram showing the flow of image data in a transmission mode of a facsimile device according to an embodiment of the present invention;
FIG. 17 is a time chart of each job A to H executed by the micro, processing, and unit section V in FIG. 7 in the transmission mode, and FIG. 18 (a) is the micro. Processing, document reading unit executed by unit V■
18(b) is a diagram of the phase excitation pattern of the pulse motor at that time, and FIG. 18(C) is the phase excitation actually output to the pulse motor at that time. Signal diagram, Figure 19 (a)
191i1(b) is a flowchart for transferring the image data read by the original reading section 1 from the image information input section to the information storage section (2) in the work performed by the micro, processing, and unit section V; 191i1(b) is the information storage section Part ■R
A RAM configuration diagram for explaining each area when the AM is divided according to the type of data stored therein,
20(a) and (b) are flowcharts for pre-processing the image data in the above work and transferring it to the information storage section 2.
Flowchart for extracting image data from the RBF area of M and obtaining the run length of "white", FIG. 22 (a
), (b) is a flowchart for drawing a table based on the "white" run length in job E, extracting a WRITE code, and transferring it to the FIFO area;
Figure 23 is a flowchart for obtaining the "black" run length in job E, and Figures 24 (a) and (b) are the BLACK codes by drawing a table based on the "black" run length in job E. Figure 25 is a flowchart for generating a synchronization code and transferring it to the FIFO area in job E. Figure 26 is a flowchart for sending and receiving coded image data from the FIFO area. FIG. 27 is a flowchart of job C to be transferred to section (2). FIG. 27 is a data processing path diagram showing the flow of image data in the receiving mode of the facsimile machine according to embodiments of the present invention. FIG. Figure 29 is a time chart of each job F to ■ that section V executes in the reception mode;
) is a flowchart for drawing a table based on the data imported from the FIFO area in work ■ to obtain a run length code, Figures 30(b) to (d) are configuration diagrams of the table, and Figure 31 is Figure 30. The flowchart of the subroutine FIFOREAD in (a), and FIG. 32 is the subroutine>RUN in FIG. 30(a).
FIG. 33 is a flowchart for storing the termination pixel data in the RBF area, and FIG. 34 is a flowchart for transferring the pixel data from the RBF area to the received image output unit m.

Claims (1)

[Claims] (1) a document reading section that reads a document and generates serial pixel data; an image information input section that converts the serial pixel data into parallel pixel data; a microprocessor; and a data processing procedure executed by the microprocessor. A microcomputer that includes a read-only memory, a random access memory that performs data input/output, and a timing signal generator, and a transmitter/receiver that converts parallel encoded data to serial encoded data and serial decoded data to parallel decoded data, respectively. an information input/output section, a modem that adapts serial encoded data and serial decoded data to a transmission format, a received image output section that converts parallel pixel data from the microprocessor into serial pixel data, and a received image output section that converts the serial pixel data into serial pixel data. and a received image recording section that records image information on recording paper, and the processing that the microprocessor performs based on the data processing procedure includes at least the timing signal generation section responding to a plurality of timing signals generated at regular intervals. At the time of transmission, the sub-scanning process of the document reading unit, the process of sending the encoded data stored in the first area of the random access memory to the transmission/reception information input/output unit, and the process of transmitting the pixel data to the A process of storing pixel data from an image information input unit in a second area of the random access memory, and encoding pixel data stored in the second area of the random access memory and storing it in a first area of the random access memory. At the time of reception, the received image recording section is sub-scanned and the decoded pixel data stored in the second area of the random access memory is sent to the received image recording section. , storing the parallel encoded data in a first area of the random access memory, and decoding the encoded data stored in the first area of the random access memory to store the parallel encoded data in a second area of the random access memory. A facsimile machine is characterized in that it is configured to include processing for storing information in an area.