JPH0646180A - Picture communication equipment - Google Patents

Abstract

PURPOSE:To operate a modulation and demodulation processing, and an encoding and decoding processing by the same processor by preferentially operating the modulation and demodulation processing of transmitted and received data in a high interruption level, and operating the encoding and decoding processing in a low interruption level. CONSTITUTION:In an interruption first level, an A/D and D/A conversion at the time of transmission and reception is operated, and a high speed interrupt mucode is used. The data fetched in the first level are demodulated in the second level. In the third level, a general CPU instruction code is used in an I0 interruption, and in the fourth level, the general CPU code instruction code is used in a main program, and the encoding and decoding processing is operated. When the received data are inputted, the received data are A/D converted by an AFP 1 in the first level, and demodulated by a DSP 2 in the second level. The demodulated data are transferred to an RAM 7 in the third level, and the data in the RAM 7 are read and decoded in the fourth level. And also, at the time of transmission, the data encoded and stored in the RAM 7 are read, modulated, and transmitted to the D/A converter 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image communication apparatus such as a facsimile apparatus for transmitting and receiving image data.

[0002]

2. Description of the Related Art FIG. 10 is a diagram showing an example of the configuration of a facsimile apparatus. The modem 12 modulates and demodulates communication data transmitted and received through a telephone line via the line interface 13. ROM 6 stores programs and data, and RAM 7
Serves as a storage area for image data and a work area of the CPU 14. The reading unit 8 is a scanner that reads an original, and the recording unit 9 prints out the received electronic message. The display unit 10 is the operation unit 11
Display the phone number entered in and the content of Alum. The encoding / decoding unit 15 encodes the data read by the scanner together with the CPU 14, and decodes the data received from the modem 12. The CPU 14 further controls the whole.

FIG. 11 is a detailed diagram of the modem 12. Modem 12
Is a digital signal processor 121 that performs modulation and demodulation,
Analog front-end processor 122 for digital-to-analog conversion, CPU14 and digital signal
Interface 123 and RO with registers used to exchange digital data with processor 121
It is composed of M124. The digital signal processor 121 and the CPU 14 perform data transfer and control between the two by reading / writing the registers provided in the interface 123.

[0004]

In recent years, the capabilities of digital signal processors have been improved, and those having the capability of being capable of processing encoding / decoding and modulation / demodulation by one processor have appeared. When encoding / decoding and modulation / demodulation are processed by different CPUs as in the conventional case, a register is required to exchange data between both processors as described above.

The present invention has been made in view of the above problems and circumstances, and an object thereof is to provide an image communication apparatus in which modulation / demodulation and encoding / decoding processing are performed by the same processor.

[0006]

In order to achieve the above object, according to the present invention, the modulation / demodulation processing of transmission / reception data and the encoding / decoding processing of read / record data are performed by the same CPU. An interrupt level is provided so that the modulation / demodulation process has a high interrupt level and the encoding / decoding process has a low interrupt level.

Further, the interrupt level is set to 4 levels,
From the highest to the lowest, the first level performs analog-digital conversion of the transmitted / received data, and the second level performs modulation / demodulation processing.
Encode / decode at the level.

[0008]

When the same CPU processes modulation / demodulation and encoding / decoding, the modulation / demodulation processing of transmission / reception data, which cannot be kept waiting, is preferentially performed at a high interrupt level, and the encoding / processing can be performed at the pace in the apparatus. Perform the decryption process at a low interrupt level. As a result, one CPU can perform modulation / demodulation and encoding / decoding processing.

The interrupt level is provided in four steps from the first level to the fourth level in order from the highest level, and the processing for converting the transmission data into analog data and the reception data into digital data is performed at the first level. This is because this process involves the telephone line side and cannot wait. Modulation / demodulation processing is performed at the second level, interrupt processing from a keyboard or the like is performed at the third level, and encoding / decoding processing having the lowest urgency is performed at the fourth level. This is because the encoding / decoding processing can be performed only within the device, and thus the processing may be performed relatively slowly.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The same reference numerals as those in FIGS. 10 and 11 represent parts having the same functions. In FIG. 1, reference numeral 1 is a digital signal processor, 2 is an A / D converter for converting data transmitted by an analog front end processor into analog data, and D / A for converting the received data into digital data.
It is composed of a converter. A line interface 3 interfaces with the telephone line. Reference numeral 4 denotes a FAX circuit which interfaces the reading unit 8, the recording unit 9, the display unit 11, the operation unit 12 and the digital signal processor 1 which are connected via a bus, and controls the FAX logic.

FIG. 2 is a timing chart showing the interrupt level, demodulation processing, and decoding processing of this embodiment. The interrupt first level uses A / D and D / A conversion during transmission / reception and uses a high-speed interrupt μ code. Transfer of A / D and D / A is performed at 9600 bps, and is taken into RAM 7 every 104 μs. ADIN indicates this captured data. The data acquired at the first level is demodulated at the second level. Third
Level is IO interrupt, general CPU instruction code is used, fourth level is main CPU instruction code is used in main program, encoding, decoding processing, displaying alarm on display parel, or reading from scanner , Recording with a printer, etc.

The operation in FIG. 2 will be described. When received data is input, A / D conversion is performed at the first level and demodulation is performed at the second level. At the third level, the demodulated data is transferred to the external RAM 7, and at the fourth level, the data in the external RAM 7 is read and decoded. If you want to send again,
The data encoded in the fourth level and stored in the external RAM 7 is read from the external RAM 7 in the third level,
Modulate at the second level and transfer to the D / A converter at the first level. Transmission and reception are performed by repeating the above operation.

FIG. 3 shows a modulation block diagram and a demodulation block diagram. (A) In the modulation block, the transmission data is randomized by the scrambler 30 so that the phase change angles in the modulation are evenly issued, and the constellation pattern of this data is used as the XY map 31, and the roll-off filter is used.
After low-pass filtering at 32, the modulator 33 modulates the carrier with the transmission data and outputs it to the D / A converter 34.

In the demodulation block (b), the received data is A / D-converted (35), the demodulator 36 demodulates the signal component, and the roll-off filter 37 performs low-pass filtering. (38) and descrambler 39 to unscramble.

Next, the encoding / decoding process will be described. This encoding / decoding processing method is used for compressing raw data (NC data, Non Coded Format) read by a scanner and for receiving MH (Modified Huffman Forma).
t) When decompressing data or MR (Modified Read Format) data, mutual run of NC data, MH data, and MR data uses the accumulated run length as an intermediate code, and does not use dedicated encoding / decoding hardware. Is the way. Regarding this method, Japanese Patent Application No. 3-1929
No. 19 gives a detailed explanation.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 4 is a diagram showing the relationship between encoding / decoding instructions. NC represents image data read by a scanner in Non-Format, so-called raw data. RL indicates an accumulated run length, which is Run-Length Format. MH, M
R is CCITT's T.E. MH code of 4 recommendations, M
It is an R code. NC2RL indicates conversion from NC code to RL, and MH2RL also indicates conversion from MH code to RL. RESCNV indicates that RL is multiplied by the magnification to convert the resolution, and the arrow from B4 to A4 is B4.
A conversion from a size document to an A4 size document is shown. In the case of a facsimile machine with a memory, it indicates that the memory stores the MR code. Thus, the intermediate code R
Conversion between NC code, MH code and MR code is performed via L.

FIG. 5 shows the accumulated run length RL as the raw data N.
It is explanatory drawing at the time of generating from C. Raw data is data in which white pixel rows and black pixel rows are alternately arranged. When there is no white pixel at the beginning of one line of raw data, RL sets this to 0 and always starts from a white pixel, 3 black pixels of raw data are set to black 3, and the next 2 white pixels are integrated to form a white 5 pixel. Express. At the end of one line, enter 8000 as the end code.

FIG. 6 shows a memory configuration of encoding-type instructions.
The parameter table of each CODEC (encoding / decoding) instruction is set in the micro RAM, and the conversion table for CODEC referred to when each CODEC instruction is executed is user R.
Placed in the OM. Run length table is user RA
It is located at M. As a result, the raw data for one line is read and NC2RL is performed, and RL2MH or RL2 is read.
MR is performed and the operation of storing in the MH / MR data buffer is repeated to perform encoding.

FIG. 7 shows the memory structure of the decoding instruction system. Decoding is performed by repeating the operation of converting the raw data for one line stored in the MH / MR data buffer of the user RAM.

FIG. 8 is a flow chart of encoding. In step (40), a run length table is created from the raw data. The run length table is a set of accumulated run lengths, as shown in FIG. In step (41), it is checked whether or not there is conversion from B4 size to A4 size, in step (42) a run length table converted from B4 size to A4 size is created, and in step (43) MH / MR is set by K parameter. Branch off. The K parameter is a value recommended by T4. The EOL + tag bit is set by the application program in step (44,46), the MH code is created from the run length table in step (45), or the MR code is created from the run length table in step (46). In (48), 0-Fill is added by the application program. It is checked whether the process is completed in step (49), and an RTC (control return code) is added by an application program in step (50).

FIG. 9 is a flow chart of decoding. The EOL is searched from the compressed data received in step (51).
Check the tag bit in step (52). When the tag bit is 1, the next line is MH code, and when it is 0, M
It is an R code. In step (53), the MH code is converted into a run length table. In step (54), the MR code is converted into a run length table. Steps (55)
In step (56), if the EOL is detected at the beginning, the run length table is converted to raw data. If it is detected in step 55, the RTC is checked in step (57), and RTC is used. If not, error processing is performed in step (58), and if RTC in step 57, the process ends.

[0022]

As is apparent from the above description, the present invention can reduce the number of parts and the cost by performing modulation / demodulation and encoding / decoding processing by one CPU.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of the embodiment.

FIG. 3 Modulation and demodulation block diagram

FIG. 4 is a diagram showing an encoding / decoding code conversion system.

FIG. 5 is a diagram for explaining a cumulative run length table.

FIG. 6 is a memory block diagram of encoding instructions.

FIG. 7 is a memory configuration of a decoding instruction

FIG. 8 is a flow chart of encoding.

FIG. 9 is a decryption flow chart.

FIG. 10 is a configuration diagram of a conventional facsimile device.

[Fig. 11] Detailed configuration diagram of the modem

[Explanation of symbols]

 1 Digital Signal Processor 2 Analog Front End Processor 3 Line Interface 4 Fax Circuit 5 Dual Port Ram

Claims (2)

[Claims] 1. Modulation / demodulation processing of transmission / reception data and encoding / decoding processing of read / record data are performed by the same CPU, a plurality of interrupt levels are provided, and modulation / demodulation processing is set to a high interrupt level to perform encoding. An image communication device characterized in that the decoding process has a low interrupt level. 2. The interrupt level is set to four levels, the analog-digital conversion of transmission / reception data is performed at the first level from the highest level, the modulation / demodulation process is performed at the second level, and the encoding / decoding process is performed at the fourth level. The image communication device according to claim 1, wherein