JPS63145057A - Thermal printing head - Google Patents

Abstract

PURPOSE:To simplify circuit constitution, to reduce the number of the gate elements of IC and to perform rationalization such as the reduction in a chip area, by altering a transfer circuit to a memory address selection circuit. CONSTITUTION:A binary counter 10 initialized by the clear signal given to an input terminal 17e successively starts counting on the basis of the clock signal given to an input terminal 17c only when the signal level of an input terminal 17d is high. Further, the data to full count operation is outputted to an output terminal 18i through the Q-output of a D flip-flop 11. When the output signal of the binary counter 10 is successively advanced, only one of the outputs 12a-12h to the counter value becomes a high level, and a pixel data given to an input terminal 17b is selectively taken in memories 13a-13h. After pixel data necessary for all of the memories are stored, when a signal permitting printing output is applied to an input terminal 17a, heat generating resistors are driven through output drivers 15a-15h to perform printing.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a thermal printer used as an output device for characters, images, etc.

BACKGROUND OF THE INVENTION Conventional thermal printer heads of this type are not equipped with a launcher and consist only of shift registers, or they are assembled into integrated circuits (hereinafter referred to as ICs) with a structure as shown in Figure 4. ) etc. are used. (The type shown in FIG. 4 is a type equipped with a lunch.) In other words, in the IC chip body 1, the serial input/output of the transfer circuit composed of shift registers 2a to 2h is carried out via input terminals 7C, inverter clock b, and output terminals 81. Furthermore, the flock inputs are each interfaced with an external circuit via an input terminal 7d. Furthermore, the parallel outputs of each bit of the shift registers 2a to 2h are connected to memories (hereinafter referred to as latches) 33 to 3.
It is connected to the data input of the launch circuit consisting of h.

The launch inputs of latches 3a to 3h are connected in parallel across all pins and interfaced with an external circuit via input terminal 7b.

The data outputs of the latches 3a to 3h are output from the output control gate along with the output control signals via the input terminal 7a and the inverter 6a.
42 to 4h, and each output of the output control gates 43 to 4h is connected to output drivers 5a to 5h and output terminals 8a to 8h.
It is connected to the corresponding heat generating resistor of the thermal printer head through.

In FIG. 4, serial pixel data input to an input terminal 7C is sequentially transferred into shift registers 2a to 2h by a clock signal input to an input terminal 7d.

The pixel data transferred by the shift registers 2a to 2h is taken into the corresponding latches 3a to 3h by the launch signal input to the input terminal 7b, and the latched pixel data is output to the input terminal 7a. Output control gate 4 that corresponds only to the period when the control signal is active
The signals are output to output terminals 8a to 8h via a to 4h and output drivers 5a to 5h.

At this time, the output transistors of the output drivers 5a to 5h are turned on for black pixel data and turned off when white pixel data and the output control signal are inactive, thereby energizing and stopping the heating resistor.

Thermal printer heads generally consist of a plurality of the above-mentioned ICs arranged in the main scanning direction (horizontal direction with respect to the recording paper surface), moving the recording paper in the sub-scanning direction (vertical direction with respect to the recording paper surface), and installing the necessary heat generating resistors. Electricity is applied only to the body, and the Joule heat generated there is used to print on recording paper.

Problems to be Solved by the Invention However, since an IC with such a configuration has a large number of gate elements, it is difficult to rationalize it, and it is difficult to provide a thermal printer head that is effective for industrial use. . This is due to the following reasons.

In other words, as logic blocks constituting the IC chip body 1, the output drivers 5a to 5a occupy approximately 1/2 of the chip area.
5h and latches 3a to 3h, which occupy about 1/6th of the circuit, which are essential for driving the heating resistor, and shift registers 2a to 2h, which are necessary only for transferring pixel data, occupy about 2/6th of the total. This ratio will hardly change unless the internal configuration is significantly changed.Furthermore, since we have already reached the limit of increasing the number of integrated circuits from a manufacturing point of view,
It is difficult to reduce the area of the C-chip body 1, which poses a problem for rationalization. For this reason, it has been difficult to provide a thermal printer head that is effective for industrial use.

Therefore, the present invention aims at rationalizing the reduction of the IC chip area, etc., and facilitates the provision of a nozzle to a thermal printer that is effective for industrial use.

Means for Solving the Problems The technical means of the present invention for solving the above-mentioned problems is to change the circuit by changing the conventional transfer circuit to a memory address selection circuit while maintaining compatibility in the IC function. The structure is simplified and the number of gate elements of the IC is reduced.

That is, specifically, a circuit replacing the shift register in the IC chip body is realized by a logic circuit composed of a counter and a decoder.

action The effect of this technical means is as follows.

In other words, whereas conventional shift registers literally transfer pixel data, the present invention uses a latch circuit as a memory (random access).
In other words, pixel data is "delivered" by specifying the address of an arbitrary memory (latch) using a counter and a decoder.

In this case, although the internal operation of the IC is significantly different from the conventional one, its functions, signals, timing, etc.
Maintains compatibility with the previous version.

Furthermore, the circuit configuration of the present invention can be realized with approximately 40 to 50% the number of gate elements (however, this varies depending on the number of heat generating resistors to be driven) compared to when using a conventional shift register, The circuit operation itself is also simple.

As a result, IC
Since it is possible to further reduce the chip area compared to the current product, the number of chips that can be produced from one wafer increases, and rationalization can be achieved.

EXAMPLE Hereinafter, an example of the present invention will be described based on the accompanying drawings.

In Figure 1, 10 is a 3-bit binary counter (
This is used as an example of a counter, and in the drawing, the driving via of the heating resistor is set to 28).The clock input is input to the input terminal 17C, the inverter 16c and the decoder gate 12t, and the clear input is input to the input terminal 17e. It is ink-faced with external circuits through. Furthermore, the clear signal line is also connected to the clear input of the D flip-flop 11. Furthermore, the six counter outputs are sent to memories 13a to 13 through decoder gates 12a to 12h.
connected to the launch input of h.

(However, only the output of 12h is input to the clock input of the D flip-flop 11 and the decoder gate 12h'
The signal line from the input terminal 17d is connected to the launch input via the decoder gate 1.
2i and the above-mentioned 12h''.

The 11 data inputs are the power supply, and the Q output is the output terminal 18i.
, Q outputs are connected to the inputs of 12h° and 12i, respectively.

Furthermore, the data inputs of the memories 13a to 13h are connected in parallel across all bits, and the inverter 16b1 input terminal 1
It is interfaced with external circuitry via 7b.

The outputs of the memories 13a to 13h are connected to output control gates 14a to 14h together with output control signals via an input terminal 17a and an inverter 16a.
The output of 14h is output to the corresponding heating resistor of the thermal printer head via output drivers 152 to 15h and output terminals 183 to 18h.

Next, the operation of the configuration of this embodiment will be explained.

The binary counter 10 initialized by the clear signal applied to the input terminal 17e receives (K) of the input terminal 17d.
Counting is started sequentially by the clock signal applied to the input terminal 17e only when the signal level is high level, but when the signal level of the input terminal 17d is low level,
Since the decoder gate 12i disables clock input, no counting is performed, and when the counter fully counts, the D flip-flop 11, which was in the initial state, is triggered by the rising edge of the signal from the decoder gate 12h.
Since the decoder gate 12i is closed by the d output signal and clock input is prohibited, the counter is in a stopped state. Also, from this Q output and the signal from input terminal 17d, 12h
' By opening and closing the memory 13 when not needed.
The operation of h is prohibited.

Further, information regarding the full count operation is outputted to the output terminal 18i via the Q output of the D flip-flop 11. This output signal is externally connected to the input terminal 17d of the next IC.
It is also possible to continue counting across multiple ICs by inputting the data into .

In this way, the output signal of the binary counter 10 is sequentially advanced (and only one of the outputs 12a to 12h corresponding to the counter value becomes high level, and the pixel data given to the input terminal 17b is selectively transferred to the outputs 13a to 13h). Import it into memory.

After storing the necessary pixel data in all the memories, when a signal is given to the input terminal 17a to permit print output,
The output control gates 14a to 14h open and the output drivers 158 to 15 output according to the pixel data stored in the memory.
Printing is performed by driving the heating resistor through h.

As described above, although this embodiment has a different principle and operation from a conventional thermal printer head using a shift register, the signals to be given to the IC from the external interface are the same as in the conventional one, so it is easy to use. No particular inconvenience will occur.

In addition, a thermal printer head that is not equipped with a launcher and consists only of a shift register has to divide the shift register due to the timing of transfer and printing, and at least multiple pixel data input lines of the shift register are required on the head. Even if preparation is required, in this embodiment, only one pixel data input line needs to be provided, and if the pixel data is stored in the memory sequentially from the beginning, printing can be performed sequentially from the area where storage is completed. is possible, and there is no need to switch pixel data or stop storage in the middle. On the other hand, when it is necessary to provide a plurality of pixel data manual lines, such as when shortening the storage time of pixel data, it is possible to respond in exactly the same manner as in the past.

Furthermore, if pixel data is to be stored completely simultaneously with print recording, a D latch may be added.

Next, the number of gate elements in this example will be compared with that in the conventional case.

If the heat generating resistor that can be driven is 26 bits, the number of gate elements in the counter/decoder section is approximately 46% of that when using a conventional shift register, so the chip area can be reduced by that amount. The number of pieces that can be removed from one wafer increases.

Furthermore, in this example, since the number of defects due to defects is relatively reduced due to the small number of gate elements, a significant improvement in yield can be expected due to the synergistic effect of improving the number of parts and quality.

Next, other embodiments of the present invention will be described.

In terms of IC pixel data transfer direction, face amplifier/
Due to differences in implementation methods such as face-down, and hardware considerations, two types of transfer, rightward transfer and leftward transfer, are required, but with conventional technology, two types of ICs corresponding to each have to be developed, or a considerable amount of time has been required. Although it was complicated, there were only two options: use a bidirectional shift register.

An embodiment is shown in FIG. 2 to improve this problem.

In this embodiment, a binary up/down counter 10° is used as the counter section, and in this case, the input terminal 17r
With the signals, it is possible to realize an operation equivalent to transferring pixel data in the right direction and the left direction.

Further, in the above case, the transfer direction is normally fixed to either one by wiring on an external printed circuit board, etc., but by using a transfer gate 19 as shown in FIG. 3 as an additional circuit, 17d.

If 18i is used as the input/output terminal 20, the transfer direction can be completely controlled only by the control signal of the input terminal 17f, which is extremely useful when performing both rightward and leftward transfers with the same thermal blink head. It is valid.

When the number of heat generating resistors that can be driven is 26 bits, the second
In the embodiment shown in the figure, the number of gate elements in the counter/decoder section is approximately 42 when using a conventional bidirectional shift register.
%, the chip area can be reduced. Furthermore, even when the circuit shown in FIG. 3 is added, the cost is only about 43% compared to the conventional one, and the same effect can still be obtained.

In addition, the above-mentioned No. 1. In the second embodiment, the number of heat generating resistors that can be driven is set to 26 (64) bits, but for example, 26 (64) bits are used.
A similar effect can be obtained in the case of 5.27 bits, etc. However, the ratio of the number of gate elements differs in each case, and the area ratio also changes depending on the circuit configuration, mask layout, etc., so sufficient consideration is required before implementation.

Effects of the Invention The present invention simplifies the circuit configuration and operation of the conventional shift register section, thereby making it possible to realize similar functions with a smaller number of gate elements. Therefore, the chip area can be relatively reduced, and the number of chips can be increased, so that rationalization can be achieved. Furthermore, the following effects are also achieved.

That is, since the present invention can reduce the number of gate elements in a chip, the number of defects due to defects and the like is reduced accordingly, and yield and quality can be improved.

In addition, reversal of the transfer direction can be achieved with fewer gate elements than by using a conventional bidirectional shift register by making slight changes to the counter section, which reduces the increase in chip area for improved functionality. It can be held down.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of an internal circuit of an IC for a thermal printer head according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of an internal circuit of a counter/decoder portion of a TC for a thermal printer head according to another embodiment of the present invention. 3 is a circuit diagram of the additional circuit portion of FIG. 2, and FIG. 4 is a conceptual diagram of an example of the internal circuit of a conventional IC for a thermal printer head. However, in all the drawings, the number of heat generating resistors that can be driven is expressed as 8 bits. 9...IC chip body, 10.10'...
...Binary counter, 11...D flip-flop 7, 12...Decoder gate, I3...
... Memory (launch), 14 ... Output control gate, 15 ... Output driver, 16 ...
...Inverter, 17...Input terminal, 18.
...Output terminal, 19...Transfer gate, 20...Input/output terminal. Name of agent: Patent attorney Toshio Nakao Figure 2-3

Claims (4)

[Claims] (1) It has a structure in which a plurality of heat generating resistors have one end in common, and an integrated circuit for driving and controlling the heat generating resistors is connected to the other end of the heat generating resistors, and by supplying power and control signals from an external interface. An arbitrary heating resistor is configured to generate heat, and the integrated circuit includes output drivers for driving the heating resistors of the same number as the heating resistors that can be driven, a memory for storing binary pixel data for pixels to be printed, and the above-mentioned integrated circuit. A thermal printer head provided with a memory address selection circuit for storing the pixel data corresponding to the memory. (2) A thermal printer head according to claim (1), wherein the memory address selection circuit is constituted by a counter and a decoder. (3) The thermal printer head according to claim (2), wherein the counter and decoder circuit portions each include a 2^n-bit binary counter and a multi-input gate with n inputs. (4) The thermal printer head according to claim (2), wherein the circuit portion of the counter is constituted by a 2^n-bit binary up/down counter.