JPH106544A - Printer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printer for which the change of design for a printing driver and a gate array is not required even when the dimension of a printing medium to be used is different. SOLUTION: A printer comprises a mode signal generating circuit for generating a mode signal MODE, a line control signal generating circuit for making a line control signal MEND enable when the mode signal MODE becomes disable, a low-order bit counter 21 for counting when the mode signal MODE is enable and outputting address signals PA3-PA0 and outputting a ripple carry out signal RCO when the count value becomes the maximum count value, and a high-order bit counter 22 for triggering the ripple carry out signal RCO, counting up and outputting address signals PA19-PA4 and counting up when the line control signal MEND is enable and switching over the line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer.

[0002]

2. Description of the Related Art Conventionally, for example, in a ticket issuing machine, a printer such as a thermal printer or a thermal transfer printer is used.
The printer has a print head, and printing is performed by selectively driving a heating element of the print head. FIG. 3 is a block diagram showing a conventional print head drive circuit.

In the figure, reference numeral 11 denotes a shift register, and 12
The latch 13 is a gate circuit composed of NAND gates G1 to Gn, d ₁ to d _n is the n heating elements arranged in the main scanning direction of the print head so as to correspond to the respective NAND gates G1 to Gn of the gate circuit 13 It is. DATA is a data signal, LCLK is a clock, LATCH is a latch signal,
ENB is a head applied signal.

In general, a print head is used in a print mechanism of a printer (not shown) such as a thermal printer or a thermal transfer printer. The n-bit data is serially transferred to the shift register 11 as the data signal DATA. Then, the shift register 11 converts the data signal DATA into parallel data and outputs the parallel data to the latch 12. The latch 12 latches the parallel data from the shift register 11 and outputs the parallel data to the gate circuit 13.

At this time, among the NAND gates G1 to Gn of the gate circuit 13, the one in which the parallel data output from the latch 12 is "1" is the head application signal EN.
B is turned on during the period of "1", while the "1" heating element d ₁ corresponding to parallel data which is to d _n to the current I
_{Flow O} to generate Joule heat. In this way,
In the case of a thermal printer, heat-sensitive paper as a print medium is colored, and in the case of a thermal transfer printer, ink of an ink ribbon is transferred to plain paper as a print medium, and printing for one line can be performed.

[0006] By moving each of the printing media in the sub-scanning direction, printing can be continuously performed on the printing media. By the way, in the printer having the above-described configuration, when print data is sent from an upper-level device (not shown) to the printer at a timing set in accordance with the transport speed of the print medium, the control unit of the printer determines an image based on the print data. Data is generated, and the image data is stored as a map in an image memory (not shown). Then, the print driver, reads the image data from the image memory, the image data transferred to the print head, for selectively driving the heating element d ₁ to d _n. As a result, so that the dots are formed at the portion corresponding to the driven heating elements d ₁ to d _n in the print medium.

While the printing is performed, the print driver reads out the image data from the image memory by itself and transfers the read image data to the print head. However, the CPU of the control unit can perform another process. ing. Also,
The size of the printing medium used differs for each type of printer, and the map of the image data also changes accordingly.

FIG. 2 is a diagram showing a first example of a map in a conventional printer, FIG. 4 is a diagram showing a second example of a map in a conventional printer, and FIG. 5 is a third example of a map in a conventional printer. FIG. In each figure, a hatched portion indicates a medium image area set corresponding to a print medium (not shown). Numerals and letters indicate addresses in the image memory by hexadecimal numbers.

[0009] Then, in FIG. 2, for example, can write or read the image data of the first line to the 0 _H ~ 44 _H addresses of 0 _H ~7F _H address to configure the map. In this case, since each image data is one byte, the number of bits for one line is 44 _H × 8 = 544 _D.

Then, similarly, a map 80 is constructed._H
~ FF_H80 of addresses_H~ C4 _HThe second line at the address
Writing and reading image data
Can be. In FIG. 4, for example, a map is configured.
0 to make_H~ 3F_H0 of address_H~ 39_HNumber 1
Each image data of the line is_H~ 7F_HStreet address
40 out of it_H~ 79_HEach image on the second line at the address
Data can be written and read.

Furthermore, in FIG. 5, for example, each image data of the first line to the 0 _H to 96 _H addresses of 0 _H to ff _H addresses constituting the map, 100 _H ~1FF
To 100 _H ～196 _H address of the _H address you can write or read the image data of the second line. In this manner, the image data of each line can be written or read in the medium image area corresponding to the print medium.

[0012]

However, in the above-mentioned conventional printer, if the size of the print medium used is different, the map will be different. Therefore, it is necessary to change the design of the print driver for controlling the map. Occurs. When the print driver is formed in a gate array (not shown) together with other drivers, it is necessary to change the design of the gate array together with the design of the print driver.

An object of the present invention is to provide a printer which solves the above-mentioned problems of the conventional printer and does not require a change in the design of a print driver and a gate array even if the size of a print medium to be used is different. Aim.

[0014]

For this purpose, in the printer according to the present invention, a mode signal generating circuit for generating a mode signal, a line control signal are generated, and when the mode signal is disabled, the line signal is output. A line control signal generation circuit for enabling a control signal, and counting when the mode signal is enabled, outputting an address signal corresponding to the count value, and ripple when the count value reaches the maximum count value. The lower bit counter that outputs the carry-out signal and the ripple carry-out signal from the lower bit counter as a trigger count up, output an address signal corresponding to the count value, and enable the line control signal. Higher bit cow that counts up and switches lines And a motor.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit block diagram of a map control unit according to the first embodiment of the present invention. In the figure, 21 is a 4-bit lower bit counter, 22 is a 16-bit upper bit counter, G1
Is an OR circuit.

In the map control unit having the above-mentioned configuration, the clock LCLK is input to the enable input of the lower bit counter 21.
However, the mode signal MODE is input to the reset input, and the address signals PA3 to PA0 are output from the counter output.
However, a ripple carry-out signal RCO is output from the ripple carry-out output. The line control signal MEND and the ripple carry-out signal RCO are input to the OR circuit G1, and the OR signal G1 is output from the OR circuit G1. The OR signal SG1 is input to the enable input of the upper bit counter 22, the control signal SEL is input to the reset input, and the address signals PA19 to PA4 are output from the counter output.

Further, address signals PA19 to PA0
Is input to an address of an image memory (not shown). The mode signal MODE and the line control signal M
The END and control signal SEL are generated by a mode signal generation circuit, a line control signal generation circuit, and a control signal generation circuit (not shown).

Next, the operation of the map control unit having the above configuration will be described. FIG. 6 is a time chart of the map control unit according to the first embodiment of the present invention, and FIG.
FIG. 9 is a diagram showing a first example of a map according to the embodiment. FIG. 7 is a diagram in which the map shown in FIG. 2 is reconstructed by the map control unit of the present invention.

First, the upper bit counter 22 (FIG. 1) is reset by using the control signal SEL as a trigger. When the mode signal MODE is enabled (high level), the lower bit counter 21 starts counting by using the clock LCLK as a trigger. Subsequently, when the count value of the lower bit counter 21 becomes the maximum count value F _H, ripple carry-out signal RCO is enabled (high level). At this time, the upper bit counter 2 is triggered by the ripple carry-out signal RCO as a trigger.
2 counts up (one count).

When the count values of the lower bit counter 21 and the upper bit counter 22 become 44 _H , the mode signal MODE is disabled (low level).
, And the lower bit counter 21 is cleared (count value 0 _H ). Thus, the lower bit counter 2
1 and the addresses 0 _H ~44F _H corresponding to the count value by the upper bit counter 22 is set as an image area.

Subsequently, the line control signal MEND is enabled (high level), and the line control signal MEND is set.
, The upper bit counter 22 counts up (one count). As a result, each address 45 _H
４4F _H is set as outside the medium image area. When the mode signal MODE is enabled, the lower bit counter 21 starts counting again using the clock LCLK as a trigger to set each address of the next line.

In this way, the address is set for each line, and when the address setting for all the lines is completed, the mode signal MODE and the control signal SEL are reset, and the lower bit counter 21 and the upper bit The counter 22 is cleared. When printing is performed using the map having the above configuration, first, the control signal SE
Using L as a trigger, the upper bit counter 22 is reset. Next, when printing is started and the mode signal MODE is enabled, the lower bit counter 21 and the upper bit counter 22 start counting.

At this time, the image data stored at the address corresponding to the count value of the lower bit counter 21 and the upper bit counter 22 is read out by the print driver and transferred to the print head. When the count values of the lower bit counter 21 and the upper bit counter 22 become 44 _H , the mode signal MODE is disabled, and the lower bit counter 21 is cleared. Subsequently, the line control signal MEND is enabled, and the upper bit counter 22 counts up using the line control signal MEND as a trigger. In this way, reads each image stator from each address corresponding to the count value 0 _H ~44F _H by lower bit counter 21 and the upper bit counter 22, it is possible to perform printing of one line.

When printing of the next line is started,
The mode signal MODE is enabled, and the lower bit counter 21 starts counting by using the clock LCLK as a trigger. Then, 50 _H to 94 _H address one byte of data stored in is read by the print driver, it is transferred to the print head. As described above, the print driver reads out the image data stored at each address in the medium image area for each line, transfers it to the print head, and performs printing in accordance with the image data.

Next, another map will be described. FIG.
Is a diagram showing a second example of the map according to the first embodiment of the present invention, and FIG. 9 is a diagram showing a third example of the map according to the first embodiment of the present invention. In this case, in the map of FIG. 8, when the count values of the lower bit counter 21 (FIG. 1) and the upper bit counter 22 become 39 _H , the mode signal MODE is disabled and the lower bit counter 21 is cleared. In this manner, each address 0 _H ~ 39 _H corresponding to the count value by the low-order bit counter 21 and the upper bit counter 22 is set as an image area.

Subsequently, the line control signal MEND is enabled, and the upper bit counter 22 counts up using the line control signal MEND as a trigger. As a result, each address 3A _H ~3F _H is set as the extracellular medium image area. In this manner, the same map as the map of FIG. 4 in the conventional printer can be generated.

In the map shown in FIG. 9, when the count values of the lower bit counter 21 and the upper bit counter 22 become 96 _H , the mode signal MODE is disabled and the lower bit counter 21 is cleared. In this manner, each address 0 _H to 96 _H corresponding to the count value by the low-order bit counter 21 and the upper bit counter 22 is set as an image area.

Subsequently, the line control signal MEND is enabled, and the upper bit counter 22 counts up using the line control signal MEND as a trigger. As a result, each address 97 _H ~9F _H is set as the extracellular medium image area. In this way, the same map as that of the conventional printer shown in FIG. 5 can be generated.

As described above, in the present embodiment, the line control signal M does not depend on the address counter.
Since the line of the map can be switched by using END as a trigger, even if the size of the print medium used is different, the medium image area can be easily set only by changing the timing at which the line control signal MEND is enabled. And at the same time a map corresponding to the dimensions of the print medium can be generated.

Therefore, it is not necessary to change the design of the print driver for controlling the map. Further, there is no need to change the design of the gate array. Since the line of the map can be switched by using the line control signal MEND as a trigger, when the same map as that of FIG. 2 is generated as shown in FIG. 7, the memory capacity can be halved. Therefore, the image memory can be used effectively.

In the present embodiment, a 4-bit counter is used as the lower bit counter 21 and a 16-bit counter is used as the upper bit counter 22. However, the lower bit counter 21 and the upper bit counter 22 are used. Can be changed. When dummy data is added before and after the image data, the setting of addresses is restricted when writing the image data in the image memory or reading the image data from the image memory.

Therefore, a second embodiment of the present invention in which the setting of the address is not restricted will be described. FIG.
0 is a circuit block diagram of a map control unit according to the second embodiment of the present invention. In the figure, 21 is a 4-bit lower bit counter, 22 is a 16-bit upper bit counter, and G1 and G2 are OR circuits.

In the map control section having the above configuration, the control signal SEL and the line control signal MEND are respectively input to the OR circuit G2, and the OR signal G2 is output from the OR circuit G2.
Is output. Then, the clock LCLK is input to the enable input of the lower bit counter 21 and the data
-BUSA 31 receives the OR signal SG2 at the load input, and outputs the address signal PA from the counter output.
3 to PA0, the ripple carry-out signal RCO is output from the ripple carry-out output.

The line control signal MEND and the ripple carry-out signal RCO are input to the OR circuit G1, and the OR signal G1 is output from the OR circuit G1. The OR signal SG1 is input to the enable input of the upper bit counter 22, and the DATA-BUS3 is input to the input terminal.
2, the control signal SEL is input to the load input, and address signals PA19 to PA4 are output from the counter output.

Further, address signals PA19-PA0
Is input to an address of an image memory (not shown). Next, the operation of the map control unit having the above configuration will be described. FIG. 11 is a time chart of the map control unit according to the second embodiment of the present invention, and FIG. 12 is a diagram illustrating an example of a map according to the second embodiment of the present invention. FIG. 12 shows the map shown in FIG. 2 reconstructed by the map control unit of the present invention.

In this case, immediately before the printing is started, the control signal SEL and the OR signal SG2 are used as triggers to set the DATA
The data value (here, 4 _H ) is transferred to the lower-order bit counter 21 (FIG. 10) via the DATA-BUS
The data value (here, 14 _H ) is loaded into the upper bit counter 22 via B32. When counting is started with the clock LCLK as a trigger, the lower bit counter 21 and the upper bit counter 22 start counting from the loaded data values. In this case, the lower bit counter 21 counts up as 4, 5, 6,..., And the upper bit counter 22 counts up as 14, 15, 16,.

Thereafter, every time the counting for one line is completed, the DATA-BUSA 31 and DATA
Except that each data value is loaded via -BUS 32, the description is omitted because it is the same as that of the first embodiment. As described above, in the present embodiment, since the lower bit counter 21 and the upper bit counter 22 each start counting from the loaded data value,
As shown in FIG. 12, even when dummy data is written before the image memory and before the image memory of each line, there is no restriction on the address setting.

It should be noted that the present invention is not limited to the above-described embodiment, but can be variously modified based on the gist of the present invention, and these are not excluded from the scope of the present invention.

[0039]

As described above in detail, according to the present invention, in a printer, a mode signal generating circuit for generating a mode signal, a line control signal are generated, and the mode signal is disabled. A line control signal generation circuit that enables the line control signal when
Counting when the mode signal is enabled,
A lower bit counter that outputs an address signal corresponding to the count value and outputs a ripple carry-out signal when the count value reaches the maximum count value, and a ripple carry-out signal from the lower bit counter as a trigger. A high-order bit counter that counts up, outputs an address signal corresponding to the count value, counts up when the line control signal is enabled, and switches lines.

In this case, when the count values of the lower bit counter and the upper bit counter reach a predetermined value, the mode signal is disabled and the lower bit counter is cleared. Thus, in the image memory,
Each address corresponding to the count value of the lower bit counter and the upper bit counter is set. Subsequently, when the line control signal is enabled, the upper bit counter counts up using the line control signal as a trigger. As a result, the line is switched.

As described above, since the line of the map can be switched by using the line control signal as a trigger without depending on the address counter, the line control signal can be enabled even if the size of the printing medium used is different. By simply changing the timing of the printing, the medium image area can be easily set, and at the same time, a map corresponding to the size of the printing medium can be generated.

Therefore, it is not necessary to change the design of the print driver for controlling the map. Further, there is no need to change the design of the gate array.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a map control unit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a first example of a map in a conventional printer.

FIG. 3 is a block diagram showing a conventional print head drive circuit.

FIG. 4 is a diagram illustrating a second example of a map in a conventional printer.

FIG. 5 is a diagram illustrating a third example of a map in a conventional printer.

FIG. 6 is a time chart of the map control unit according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a first example of a map according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a second example of a map according to the first embodiment of the present invention.

FIG. 9 is a diagram illustrating a third example of a map according to the first embodiment of the present invention.

FIG. 10 is a circuit block diagram of a map control unit according to a second embodiment of the present invention.

FIG. 11 is a time chart of the map control unit according to the second embodiment of the present invention.

FIG. 12 is a diagram showing an example of a map according to the second embodiment of the present invention.

[Explanation of symbols]

 21 Lower bit counter 22 Upper bit counter MODE Mode signal MEND Line control signal PA19 to PA0 Address signal RCO Ripple carry-out signal

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masaru Shimakata 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (2)

[Claims] 1. A mode signal generating circuit for generating a mode signal, and a line control for generating a line control signal and enabling the line control signal when the mode signal is disabled. A signal generation circuit;
(C) a lower bit counter that counts when the mode signal is enabled, outputs an address signal corresponding to the count value, and outputs a ripple carry-out signal when the count value reaches a maximum count value; ,
(D) Counting up using the ripple carry-out signal from the lower bit counter as a trigger, outputting an address signal corresponding to the count value, and counting up when the line control signal is enabled, A printer comprising: an upper bit counter for switching. 2. The printer according to claim 1, wherein each of the lower bit counter and the upper bit counter is loaded with a data value and starts counting from the data value.