JP2866544B2 - Print data output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a print data output circuit used for a serial dot printer or the like.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional print data output circuit in a serial dot printer. The print data output circuit is provided with a print data holding circuit 4 for holding print data output from the central processing unit (CPU) 2. The print data holding circuit 4 is composed of 8-bit latch circuits 41, 42, and 43, and print data output from the CPU 2 is applied to each of the latch circuits 41, 42, and 43 through the data bus 5. The address decoder 6 is an address designating means for each of the latch circuits 41, 42, and 43. The address decoder 6 receives address data through an address bus 10 together with a write enable signal WI output from the CPU 2 through a signal line 8, and receives through the latch signal bus 12 A latch signal LA is applied to each of the latch circuits 41, 42, 43. The latch signal LA is
Latch circuits 41, 42, 43 in accordance with data addresses.
To rewrite the data.

On the output side of the print data holding circuit 4, an output buffer 14 for outputting print data is provided.
2, 43 held data are individually added. This output buffer 14 is constituted by a gate circuit,
Receives the drive control signal DC output through the signal line 16 from each of the latch circuits 41, 42, and 43.
After the character data is rewritten, the passage of the data is permitted, and the print data from each of the latch circuits 41, 42, and 43 is output. The head drive circuit 18 drives a print head based on the print data, and performs printing on a sheet (not shown).

[0004]

FIG. 5 shows the operation timing of the print data holding circuit 4 in the print data output circuit, wherein a is the drive control signal DC, and b is the drive control signal in the print data holding circuit 4. The data holding and rewriting operation of one latch circuit 41 is shown. As is apparent from this operation timing, the output buffer 14 becomes conductive (O) in the H section of the drive control signal DC.
N), the output buffer 14 is cut off (OFF) in the L section
Becomes The H section of the drive control signal DC is a print data holding section T ₁ of each of the latch circuits 41, 42 and 43, and the L section thereof is a data rewritable section T ₂ of each of the latch circuits 41, 42 and 43. Then, the print data held section T ₁ is 4/5 of the printing period T, i.e., will be accounted for 80 percent, so that the time remaining 1/5 is applied to the data rewritable section T ₂ .

[0005] However, the increase in printing speed will become possible to shorten the printing period T, because the increase in the control functions of the printer to increase the processing of CPU, performs rewriting processing of the print data in the short T ₂ times Making it difficult.

For this reason, conventionally, the operating clock frequency of the CPU 2 has been increased, and the print data has been
A method of shortening the processing time of the CPU 2 by conversion to bit processing or the like has been adopted. However, advancing the operation clock of the CPU 2 is naturally limited by the capability of the CPU 2 being used, and changing the data processing from 8-bit processing to 16-bit processing is effective, but increases the cost. With these traditional measures,
Still large printing data holding section T _1, when the head drive circuit 18 is driving the print head, i.e., during the energization of the print head, improving the point of not being able to rewrite the content of the print data holding circuit 4 Unless you do so, there will be no drastic solution.

Therefore, the present invention realizes a print data output process with a margin without increasing the data processing cost by holding data irrespective of the print operation, and increases print speed and reduces complicated processing. It is another object of the present invention to provide a print data output circuit which realizes the above-mentioned correspondence.

[0008]

A print data output circuit according to the present invention generates print data as shown in FIG.
A print data output circuit having data processing means (CPU2) for outputting print data received from said data processing means to a head drive circuit (18) through an output buffer (14); A first data holding unit (print data holding circuit 20) for holding print data, and a second data holding unit for holding the print data received from the first data holding unit and outputting the print data to the output buffer side. Data holding means (print data holding circuit 22) and the output buffer
While print data output to the drive circuit is shut off
The contents held by the first print data holding means are stored in the second print data holding means.
Latched in the print data holding means, and after the latch,
2 before the next latch of the print data holding means.
The next print data is stored from the processing means in the first print data storage.
And a latch control means (latch signal generating circuit 24) for latching to the holding means .

[0009]

[0010]

According to the present invention, the holding of the conventional print data is realized by the first and second data holding means, and the print data is output.
Print data output from buffer to head drive circuit
While the force is interrupted, the second
The data held in the data holding means is latched, and the second mark
Between the latch of the character data holding means and the next latch.
Latch the next print data to the 1 data holding unit
Is going. That is, rewriting of the second data holding means and
The holding is performed while the output buffer is shut off, and the first data is held.
The rewriting and holding of the next print data to the
2 until the next latch of the data holding means. That
As a result, the timing of rewriting and holding of the first data holding means
Flexibility in printing, and the conventional circuit can print data
Data is being supplied while the print head has not been
Latch from the data holding means becomes possible. Therefore, in this print data output circuit, the processing timing on the data processing means side is not restricted by the switching of the output buffer, that is, the printing operation, and the processing timing on the data processing means side is relaxed.

[0011]

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments shown in the drawings.

FIG. 1 shows a first embodiment of a print data output circuit according to the present invention. In this print data output circuit, the same parts as those of the conventional print data output circuit shown in FIG.

The print data output circuit is provided with a central processing unit (CPU) 2 as data processing means for receiving print information from an external data processing device.
A print data holding circuit 20 is provided as first data holding means for print data output by U2, and a print data holding circuit 22 is provided on the output side as second data holding means.

The print data holding circuit 20 comprises 8-bit latch circuits 201, 202 and 203, similarly to the conventional print data holding circuit 4 (FIG. 4). Since the print data is received from the circuit 20 and held, the reset 8-bit latch circuits 221 and 222 having the same data holding capacity
223.

Each of the latch circuits 201, 202, 2
To 03, print data output from the CPU 2 is added through the data bus 5. The address decoder 6 is an address designating means for each of the latch circuits 201, 202 and 203, and includes an address bus 1 together with a write enable signal WI outputted from the CPU 2 through the signal line 8.
0, and receives the address data through the latch signal bus 12
Providing a latch signal LA ₁ in the latch circuits 201, 202, 203 through. That is, each of the latch circuits 201 and 20
Print data from the CPU 2 is written into the CPU 2 and 203 at the timing of the latch signal LA ₁ .

The latch circuits 221, 222, 223
Signal generation circuit 24 as a latch control means for
Is installed. This latch signal generation circuit 24
A drive control signal DC output from the PU 2 through the signal line 16 is received, and a latch signal LA ₂ is generated as a control signal for starting a write operation at a timing when the output buffer 14 is turned off. This latch signal LA
₂ is connected to each of the latch circuits 221, 222,
223, and as a result, the latch circuits 221, 22
In steps 2 and 223, data writing synchronized with the drive control signal DC, that is, latch control is performed.

The address decoder 6 constitutes clear control means on the side of the latch circuits 221, 222 and 223, and generates a clear signal CL in an initial operation.
The clear signal CL is applied to each of the latch circuits 221, 222, and 223 through the signal line 28, and is used for clearing previously held data. The clear signal CL can be generated, for example, during the initial operation, that is, in response to the write enable signal WI.

An output buffer 14 is provided on the output side of the print data holding circuit 22. The output buffer 14 receives a drive control signal D from the CPU 2.
C, the passage of data is permitted, and each latch circuit 22
Print data from 1, 222, 223 is output. The head drive circuit 18 drives the print head based on the print data, and prints on paper (not shown) as in the conventional circuit.

The operation of the print data output circuit will be described with reference to FIG. Each latch circuit 201, 202, 203
From the CPU _{2 at} the timing of the latch signal LA ₁
The print data is written through the data bus 5, and the data is
In the rewritten state, as shown in b, c and d in FIG.
Next latch signal LA ₁ to the print data A, B, C is maintained
Is done. The latch signal LA ₁ is a write enable signal of the CPU 2.
Signal WI and address data from the address bus 10
Generated and latched according to the address of the rewrite data
Instruct the circuits 201, 202, and 203 to rewrite the print data.
Show.

A clear signal CL shown in FIG. 2E is output from the address decoder 6, and the clear signal CL is transmitted through a signal line 28 to each of the latch circuits 221, 222, 22.
Added to 3. That is, each of the latch circuits 221 and 222,
Reference numeral 223 indicates that the previous data is cleared by the clear signal CL, and the data is ready to be written. Then, as shown in f in FIG. 2, the latch signal LA ₂ of the switched point from H section of the drive control signal DC to L section and the rising timing is outputted from the latch signal generation circuit 24, the latch circuit 221, 222, 223. With this timing, each of the latch circuits 221, 22
2 and 223, transfer of print data on the latch circuits 201, 202, and 203 sides, that is, print data A, B, and C from the latch circuits 201, 202, and 203, as shown in g, h, and i in FIG. writing of Ru is carried out. Then, D to each falling of the sequential drive control signal DC, E, F ·
... the writing is going to be done. That is, output buffer 1
When the latch circuit 221 and the latch circuit 221
22 and 223 are performed. The holding section of this data is T _O.

The output buffer 14 shifts to the conductive state at the rising timing of the drive control signal DC from the L section to the H section, and the latch circuits 221, 2
The print data written in 22, 22 is added to the head drive circuit 18 through the output buffer 14 as shown in FIG. 2j, and printing based on the print data is performed.

The latch circuits 201, 202, 203
The print data is stored in the latch circuits 221, 222, 2
After being transferred to 23, the next print data from the CPU2 with a timing of the next latch signal LA ₁ is written. Writing of print data to the latch circuits 201, 202, and 203 is performed irrespective of output control of the output buffer 14. This corresponds to b, c and d in FIG.
It is clear from the fact that the write timings of the print data A, B and C, the print data D, E and F, and the print data G, H and I are asynchronous with the drive control signal DC. Thus, the latch circuits 201, 202, 2
03 is rewritten by the drive control signal D
The drive control signal D is not limited to the L section of C.
It is possible at any time within one cycle starting from the timing of switching the C section from the H section to the L section. However, the latch circuits 221, 222, and 223 are
Out between (LA _2, which reads the data of 202 and 203
It goes without saying the force at the time) is not possible.

In this print data output circuit, the data of the latch circuits 221, 222 and 223 are cleared to "OOH" by the clear signal CL generated by the address decoder 6 and returned to the initial state.
Output buffer 1, which is the rewrite condition of 1, 222, 223
4 can be shifted to a data writable state without waiting, and as a result, the output buffer 14 can prevent output of indefinite data. In FIG.
“Undefined” indicates undefined data.

As described above, the print data holding circuits 20, 2
Since 2 was established, the respective print data holding circuit 20, 22 can be processed by separating the output process CPU2 side of the print data writing and the output buffer 14 in two steps. As a result, the former and the latter can be set asynchronously, the write timing condition on the CPU 2 side is relaxed, and the burden on the CPU 2 of processing at a limited timing is reduced. In other words, the two-stage processing of the print data holding circuits 20 and 22 allows the CPU 2 to operate the latch circuits 201, 202, and 203 while the head drive circuit 18 is operating, that is, while the print head is energized.
It is possible to rewrite the print data to the printer. Therefore, C
With the current processing speed of PU2, it is possible to sufficiently cope with the increase in printing speed and the complexity of processing on the CPU2 side.
This contributes to the high-speed processing on the two sides.

Next, FIG. 3 shows a second embodiment of the print data output circuit of the present invention.

In the first embodiment, the print data holding circuit 22
Is made dependent on the data output of the print data holding circuit 20. In the second embodiment, as a method of determining the initial state of the print data holding circuit 22, data input to the print data holding circuit 22 is performed. It is separated from the output of the print data holding circuit 20 and can be directly executed from the data bus 5 of the CPU 2.

As shown in FIG. 3, the print data holding circuit 2
0 sent to the output side of each of the latch circuits 201, 202 and 203 through the data bus 5 and the latch circuit 20.
Data selectors 31, 32, and 33 corresponding to the respective latch circuits 201, 202, and 203 are provided as data selection means for selecting data on the side of 1, 202, and 203. Then, a 1-bit latch circuit 34 is provided as data selection means for the data selectors 31, 32, and 33.
This latch circuit 34 is applied the control data from the latch signal LA ₁ and the data bus 5 from the latch signal bus 12, the data selection signal is obtained by both.

The data selected by the data selectors 31, 32, and 33 are applied to the latch circuits 221, 222, and 223 of the print data holding circuit 22, respectively. Then, OR circuits 51, 52, and 53 are provided corresponding to the latch circuits 221, 222, and 223, respectively.
Reference numerals 52 and 53 denote a latch signal LA ₂ from the latch signal generation circuit 24 and a latch signal LA from the address decoder 6.
_One has been added. That is, each of the latch circuits 221 and 22
2 and 223, the output data of the data selectors 31, 32 and 33 receive the latch signal LA from the address decoder 6 side.
_1, the latch signal LA ₂ from the latch signal generation circuit 24 side
, The latch operation can be performed.

By doing so, the latch circuits 221 and 2
22 and 223, the data on the CPU 2 side and the latch circuit 20
One of the data can be selectively written from the sides 1, 202, and 203, and the data can be output through the output buffer 14. Therefore, also in this embodiment,
By alternately writing the output data of the CPU 2 using the print data holding circuits 20 and 22, the processing of the CPU 2 and the processing of the output buffer 14 can be performed separately, and the print data can be held even during the processing of the print head. Since the print data can be written to the circuit 20, the timing restrictions on the CPU 2 can be relaxed, and the printing speed can be increased and the CPU 2 can cope with complicated processing without increasing the number of processing bits. it can.

In the embodiment, the latch signal generation circuit 24 and the address decoder 6 are used as the latch control means. However, the latch control means may be constituted by the CPU 2 or may be constituted by an external circuit. .

[0032]

As described above, according to the present invention,
An output buffer is provided by installing first and second data holding means.
Print data output to the head drive circuit from the
While the first print data holding means is
Latching the second print data holding means,
After that, the next print data is sent from the data processing unit until the next latch.
Latching the first print data to the first print data holding means.
Thus, the rewriting and holding timing of the first data holding unit has a high degree of freedom, the processing timing on the data processing unit side can be relaxed, and the operation clock of the data processing unit such as a CPU can be increased in speed. It is possible to cope with an increase in printing speed and complicated processing on the data processing means side without contributing to a high cost such as an increase in the number of processing bits of data, thereby contributing to an increase in processing speed.

[0033]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a print data output circuit according to the present invention.

FIG. 2 is a timing chart showing the operation of the print data output circuit shown in FIG.

FIG. 3 is a block diagram showing a print data output circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional print data output circuit of a serial dot printer.

FIG. 5 is a timing chart showing an operation of the print data output circuit shown in FIG.

[Explanation of symbols]

 2 Central processing unit (data processing means) 6 Address decoder (latch control means) 14 Output buffer 18 Head drive circuit 20 Print data holding circuit (first data holding means) 22 Print data holding circuit (second data holding means) 24 Latch signal generation circuit (latch control means) 31, 32, 33 Data selector (data selection means) 41, 42, 43 Latch circuit

Claims (1)

(57) [Claims] A data processing unit for generating print data;
A, a printing data output circuit for outputting to the head drive circuit through an output buffer the print data received from said data processing means, a first data holding means for holding the print data received from said data processing means, A second data holding unit for holding the print data received from the first data holding unit and outputting the print data to the output buffer side ;
While the print data output is shut off, the first print data
The data held by the data holding means to the second print data holding means.
And after the latch, the second print data holding means
The next print from the data processing means until the next latch of the stage
And a latch control means for latching data in the first print data holding means .