JP2568524B2 - Thermal printer head - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal printer head used for an output device for characters and images.

2. Description of the Related Art Conventionally, a thermal printer head of this type does not include a latch and is constituted only by a shift register, or an integrated circuit having a structure as shown in FIG. (FIG. 4 shows a type equipped with a latch). That is, in the IC chip body 1, serial input / output of the transfer circuit composed of the shift registers 2a to 2h is performed via the input terminal 7c, the inverter 6b and the output terminal 8i, respectively, and clock input is performed via the input terminal 7d. Each is interfaced with an external circuit. Furthermore, the parallel output of each bit of the shift registers 2a to 2h is connected to the data input of a latch circuit composed of memories (hereinafter referred to as latches) 3a to 3h. The latch inputs of the latches 3a to 3h are connected in parallel over all the bits, and interface with an external circuit via the input terminal 7b.

The data output of the latches 3a to 3h is output to the output control gates 4a to 4h together with the output control signal via the input terminal 7a and the inverter 6a.
And the respective outputs of the output control gates 4a to 4h are connected to the corresponding heating resistors of the thermal printer head via output drivers 5a to 5h and output terminals 8a to 8h.

In FIG. 4, serial pixel data input to the input terminal 7c is sequentially transferred into the shift registers 2a to 2h by a clock signal input to the input terminal 7d. The pixel data transferred by the shift registers 2a to 2h is
The pixel data captured and latched by the latch signals input to the input terminal 7b into the corresponding latches 3a to 3h are output control gates 4a to 4h corresponding to the output control signal input to the input terminal 7a only during an active period. Output to output terminals 8a to 8h via 4h and output drivers 5a to 5h.

At this time, the output transistors of the output drivers 5a to 5h are:
It turns on when black pixel data is turned on, turns off when white pixel data and the output control signal are inactive, and energizes and stops the heating resistor.

In general, a thermal printer head arranges a plurality of the ICs in the main scanning direction (horizontal direction with respect to the recording paper), moves the recording paper in the sub-scanning direction (vertical direction with respect to the recording paper), and generates a necessary heat generation resistance. Power is applied only to the body, and printing is performed on the recording paper by Joule heat generated there.

Problems to be Solved by the Invention However, there is a problem that it is difficult to rationalize an IC having such a configuration because of a large number of gate elements, and it is difficult to provide a thermal printer head effective for industrial use. This is for the following reason.

In other words, the logic blocks that constitute the IC chip body 1 are indispensable parts for driving the heating resistor composed of the output drivers 5a to 5h occupying about 1/2 of the chip area and the latches 3a to 3h occupying about 1/6. In addition, shift registers 2a to 2h necessary only for transferring pixel data occupy about 2/6, and this ratio hardly changes unless the internal configuration is significantly changed. Furthermore, since increasing the degree of integration has already reached the limit in terms of manufacturing, it has been difficult to reduce the area of the IC chip body 1, which has been a problem for rationalization. For this reason, it has been difficult to provide a thermal printer head that is effective for industrial use.

Therefore, the present invention aims at rationalizing the reduction of the chip area of the IC, etc., and facilitates the provision of a thermal printer head effective for industrial use.

Means for Solving the Problems In order to achieve the above object, according to the present invention, a plurality of heating resistors each having a common terminal at one end and a heating resistor drive control integrated circuit connected to the other end of the heating resistor are provided. A configuration in which an arbitrary heating resistor is heated by supplying a power supply and a control signal from an external interface, and the same number of heating drivers as the heating resistors that can be driven in the integrated circuit; A memory for storing binary pixel data for a pixel to be printed, and storing the pixel data corresponding to the memory, selecting the memory based on the pixel data, and storing the pixel data in the selected memory. Is provided with a memory address selection circuit provided with a selection means for inputting.

Operation The operation of this technical means is as follows.

That is, what was used for the conventional shift register is
Whereas pixel data was literally “transferred”, the present invention uses a latch circuit as a memory (Random Access Memory).
The pixel data is fetched into the memory by designating an address of an arbitrary memory (latch) using a counter and a decoder. In other words, the pixel data is "delivered". In this case, although the internal operation of the IC is significantly different from that of the related art, the functions, signals, timings, and the like of the IC are compatible with the related art.

Further, the circuit configuration of the present invention can be realized with the number of gate elements of about 40 to 50% of the case where a conventional shift register is used (however, this varies depending on the number of heating resistors to be driven). The circuit operation itself is also simple.

As a result, the IC
Chip area can be further reduced than the current product, so that the number of chips that can be taken from one wafer increases and rationalization can be achieved.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

In Figure 1, the IC chip body 9, in 10 3 bit high binary counter (which was used as an example of a counter, and the number of driving bits of the heating resistor 2 ³ in the drawing), a clock input Input terminal 17c, inverter 16c and decoder gate 12i, and clear input is input terminal 1
It is interfaced with an external circuit through each of 7e. Further, the clear signal line is also connected to the clear input of the D flip-flop 11. Six more counter outputs are
Connected to the latch inputs of the memories 13a to 13h via the decoder gates 12a to 12h (however,
Are further connected to the clock input of the D flip-flop 11 and the latch input via the decoder gate 12h '.

The signal line from the input terminal 17d is connected to the decoder gate 12i.
And the decoder gate 12h '.

The data input of the D flip-flop 11 is a power supply, the Q output is an output terminal 18i, and the output is a decoder gate 12h '.
Each is connected to the input of 12i.

The data inputs of the memories 13a to 13h are connected in parallel over all bits, and are interfaced with an external circuit via the inverter 16b and the input terminal 17b.

The outputs of the memories 13a to 13h are input terminal 17a, inverter 1
Output control gates 14a to 14h together with output control signals via 6a
The outputs of the output control gates 14a to 14h are output to corresponding heating resistors of the thermal printer head via output drivers 15a to 15h and output terminals 18a to 18h.

 Next, the operation of the configuration of the embodiment will be described.

By the clear signal pulses supplied to the input terminal 17e, the counter output signal Q ₀ to Q ₂ of the binary counter 10 is at a low level, the inverted output signal ▲ ▼ ~ ▲ ▼ the high level, also the Q output signal of the D flip-flop 11 And the output terminal 18i is at a low level, the output signal is at a high level,
Each is initialized.

When the signal level of the input signal 17d is at the high level after the end of the initialization, the NAND circuit of the decoder gate 12i becomes logically equivalent to an inverter circuit. After being inverted once at 16c, it is again inverted at the decoder gate 12i and returned to the original logic level, and the CL of the binary counter 10 is reset.
Input to the K input terminal. As a result, binary counter 1
0 starts counting sequentially, but when the signal level of the input terminal 17d is low, the output of the decoder gate 12i keeps the high level regardless of the clock input level of the input terminal 17c. Since the input does not change and the clock signal at the input terminal 17c is not transmitted to the binary counter 10, counting is not performed. Further, when the counter is counted 2 ³ times full count, at the rising edge of the signal of the decoder gates 12h, D was in the initial state
When the flip-flop 11 is triggered and the output signal goes low, the output of the decoder gate 12i also keeps the high level, so that the CLK input of the binary counter 10 does not change, and the clock signal of the input terminal 17c is The counter is stopped because it is not transmitted.

The output and input terminal of the D flip-flop 11
By opening and closing the decoder gate 12 'based on the signal from 17d, the operation of the memory 13h other than when necessary is prohibited.

Further, information on the full count operation is output to the output terminal 18i via the Q output of the D flip-flop 11. If this output signal is externally input to the input terminal 17d of the next IC, it is possible to continue counting over a plurality of ICs.

At this time, when one IC is used, a high-level fixed signal is used as a signal input to the input terminal 17d. Also, in the first IC in the case where a plurality of ICs are connected, a high-level fixed signal is used as a signal input to the input terminal 17d.

Thus, when the output signal of the binary counter 10 is sequentially advanced, the decoder gates 12a to 12h
Only one of the outputs goes high, and the input terminal
The pixel data given to 17b is selectively taken into 13a to 13h. After storing the necessary pixel data in all the memories 13a to 13h, when a signal for permitting print output is given to the input terminal 17a, the output control gates 14a to 14h are opened, and the pixel data stored in the memories 13a to 13h are opened. Output drives the heating resistors via the output drivers 15a to 15h to perform printing.

As described above, in the present embodiment, although the principle and operation are different from those of the thermal printer head using the conventional shift register, the signals to be supplied from the external interface to the IC are the same as those of the conventional thermal printer head. No particular inconvenience occurs.

In addition, a thermal printer head that is composed of only a shift register without a latch needs to divide the shift register due to transfer and printing timings.
Even if it is necessary to prepare a plurality of pixel data input lines of the shift register on at least the head,
In this embodiment, it is only necessary to provide a single pixel data input line. If pixel data is stored in the memory in order from the beginning, it is possible to sequentially print from the area where the storage has been completed. There is no need to switch data or stop storing. Conversely, when it is necessary to provide a plurality of pixel data input lines, such as when the storage time of the pixel data is shortened, it is possible to deal with the same method as in the related art.

Further, when pixel data is stored completely at the same time as printing, a D-latch may be added.

Next, the number of gate elements in the present embodiment will be compared with the conventional case.

When the driveable heating resistor is ²⁶ bits, the number of gate elements in the counter / decoder part is only about 46% of that in the case of using the conventional shift register, so the chip area can be reduced accordingly. In addition, the number of pieces to be taken from one wafer increases.

Further, in the present embodiment, since the number of soots in the gate element is small, the number of defects due to defects and the like is also relatively reduced.

 Next, another embodiment of the present invention will be described.

For the pixel data transfer direction of the IC,
Two types of transfer, rightward transfer and leftward transfer, are required due to differences in mounting methods such as face-down and hardware, but with the conventional technology, two types of ICs corresponding to each type must be developed or Although complicated, there were only two ways to use a bidirectional shift register.

 An embodiment for improving this is shown in FIG.

In this embodiment, the counter unit uses a vinyl up / down counter 10 '. In this case, an operation equivalent to transferring pixel data to the right and left by the signal of the input terminal 17f can be realized. .

In addition, the transfer direction in the above case is generally fixed to one of the two by wiring such as an external printed circuit board, but using transfer gates 19a to 19d as shown in FIG. Input terminal 17d and output terminal 18
If i is the input / output terminal 20a, 20b, the transfer direction can be completely controlled only by the control signal of the input terminal 17f, and when the same thermal printer head performs both rightward transfer and leftward transfer, etc. Very effective.

If the number of heat generating resistors that can be driven is ²⁶ bits, the second
The number of gate elements in the counter / decoder portion in the embodiment shown in the figure is about 42% of that in the case of using the conventional bidirectional shift register.
Therefore, the chip area can be reduced. In addition, even when the circuit of FIG. 3 is added, only about 43% is required as compared with the conventional circuit, and the same effect can be obtained.

In the first and second embodiments, the number of heat-generating resistors that can be driven is 2 ⁶ (64) bits. However, the same effect can be obtained when the number of heat-generating resistors is ²⁵ or ²⁷ bits, for example. However, in each case, the ratio of the number of gate elements is different, and the area ratio varies depending on the circuit configuration, the mask layout, and the like. Therefore, a thorough study is required before implementation.

Further, in this embodiment, a logic circuit composed of a counter and a decoder is used as the selection means of the memory address selection circuit. However, other circuits may store the corresponding pixel data in the storage memory, The same effect can be obtained by providing a selection means for selecting a storage memory based on the above and inputting pixel data to the selected storage memory.

For example, in the present embodiment, the counter circuit is provided for the purpose of maintaining compatibility with the conventional IC chip also in the signal and the timing thereof. An address selection circuit can be configured. In this case, although the signals and their timings are different from those of the conventional IC chip, and the number of input terminals is increased as compared with the above-described embodiment, the function of the thermal printer head is the same as that of the conventional thermal printer head by an appropriate external decoder logic. Can be done, in addition,
Streamlining by further reducing the IC chip area and complete random access are possible.

According to the present invention, the same function can be realized with a smaller number of gate elements by simplifying the circuit configuration of the conventional shift register portion and simplifying the operation. For this reason, the chip area can be relatively reduced, and the number of chips can be increased, so that rationalization can be achieved. Further, the following effects are also obtained.

That is, since the present invention can reduce the number of gate elements in a chip, the number of defects due to defects and the like can be reduced accordingly, and the yield and quality can be improved.

In addition, inversion of the transfer direction and the like can be realized with a smaller number of gate elements than using a conventional bidirectional shift register by only slightly changing the counter section.
It is possible to keep the increase in the chip area for improving the function low.

[Brief description of the drawings]

FIG. 1 shows a thermal printer head according to an embodiment of the present invention.
FIG. 2 is a conceptual diagram of an internal circuit of the IC, FIG. 2 is a schematic diagram of an internal circuit of a counter / decoder part of a thermal printer head IC according to another embodiment of the present invention, and FIG. 3 is a circuit of an additional circuit part of FIG. FIG. 4 is a conceptual diagram of the internal circuit of a conventional thermal printer head IC. In the drawings, however, the number of drivable heating resistors is represented as 8 bits. 9: IC chip body, 10, 10 ': Binary counter, 1
1 ... D flip-flop, 12a-12i, 12h '... Decoder gate, 13a-13h ... Memory (latch), 14a-14h ...
… Output control gates, 15a to 15h …… Output drivers, 16a to 1
6c …… Inverter, 17a-17f …… Input terminal, 18a-18i…
… Output terminals, 19a to 19d …… Transfer gates, 20a, 20
b ... I / O terminal.

Claims (4)

(57) [Claims] 1. A power supply and a control signal are supplied from an external interface having a structure in which a plurality of heating resistors each having one end as a common terminal, and a heating resistor driving control integrated circuit connected to the other end of the heating resistor. A heat-generating resistor, thereby generating heat by heating the heat-generating resistor.
A memory for storing binary pixel data for a pixel to be printed, and storing the pixel data corresponding to the memory, selecting the memory based on the pixel data, and storing the pixel data in the selected memory. A thermal printer head provided with a memory address selection circuit provided with a selection means for inputting an address. 2. The thermal printer head according to claim 1, wherein the memory address selection circuit comprises a counter and a decoder. 3. The thermal printer head according to claim 2, wherein the circuit portions of the counter and the decoder are each constituted by a ^2n- bit binary counter and a multi-input gate having n inputs. 4. The circuit according to claim 2, wherein the circuit portion of the counter is constituted by a 2 ^n- bit binary up / down counter.
The thermal printer head according to the item.