JPS6314501B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a high-power, high-speed semiconductor device, particularly a static induction thyristor.

A conventional electrostatic induction thyristor will be explained using an n-channel type example, and as shown in Figure 1a, 1 is the p ⁺ region of the anode, 2 is the n ^- region between the gate and anode, and 3 is the gate region. p ⁺ region, 4 is n ^- region between gate and cathode, 5 is n ⁺ of cathode
The regions are formed by an anode metal electrode 6, a cathode metal electrode 7, and a so-called channel between gates. Briefly, the conventional method for manufacturing a static induction thyristor is as follows: First, the n ^- region 2 between the gate and anode is used as an n ^- substrate.
Oxidize p ⁺ region 3 of gate, photolithography technique,
It is formed by selective etching, diffusion, ion implantation, etc. At this time, the p ⁺ region 1 of the anode is often formed at the same time. Next, an n ^- region 4 between the gate and cathode is formed by epitaxial growth,
Fill the p ⁺ region 3 of the gate. Next, the cathode
The n ⁺ region 5 is formed by diffusion, epitaxial growth, ion implantation, or the like. Next, by oxidation, photolithography, and selective etching, the n ⁺ region 5 of the cathode and the n ⁻ region 4 between the gate and cathode are removed to expose the p ⁺ region of the gate, thereby forming a contact region for the gate. Next, a metal such as Al is formed by vapor deposition, photolithography, selective etching, etc. to form each metal electrode of the cathode, gate, and anode.

Since the conventional electrostatic induction thyristor shown in FIG. 1a is manufactured by the manufacturing method described above, it has the following drawbacks.

Since the p ⁺ region 3 of the gate is formed by diffusion or ion implantation, the gate resistance is large.
The epitaxial growth of n ^- region 4 between the gate and ^cathode has a relatively high impurity density (~
10 ¹⁵ to 10 ¹⁶ /cm ³ ), and because the facing area of the gate and cathode is large, the capacitance between the gate and cathode is large, which causes problems such as a long turn-off time due to the characteristics of the device. .

An electrostatic induction thyristor as shown in FIG. 1b has been proposed to eliminate these drawbacks. This static induction thyristor has a large maximum forward blocking voltage V _fnax , a small forward drop voltage V _fd , a large voltage gain μ, and a gate turn-off current
This was proposed as a device that provides characteristics such as a large I _a , a small turn-off time T _pff , and a large turn-off current gain G. In the figure, 1 to 8 are the same as in Figure 1a, 9 is an insulator such as an oxide film, 10
is the n area, and 11 is the n ⁺ area.

A method of manufacturing the electrostatic induction thyristor shown in FIG. 1b according to the present invention will be described below.

As shown in FIG. 2a, an oxide film 9 is formed on the surface of the n ^-substrate 4 between the gate and the cathode by thermal oxidation, etc.
A photoresist 13 is formed by photolithography. Depending on the next step, even the broken line portion may be formed.

Next, as shown in FIG. 2b, the n ^- substrate 4 is removed to a depth of about 5 μm using anisotropic etching. or second
As shown in Figure b', the opening of the oxide film ⁹ is
After removing the etch to a certain extent, the opening of the oxide film 9 is enlarged by photolithography and the process of etching the n ^- substrate 4 is repeated, thereby forming an etch hole having an arbitrary slope. The size of the oxide film 9 is about 5 to 10 microns, the distance between the bottoms of the etched holes is about 50 microns, and the depth is about 5 microns.

Next, as shown in FIG. 2c, a p ⁺ region 3 which will become a gate is formed by epitaxial growth. The epi layer thickness is approx.
It should be about 5μ. By epitaxial growth, the entire p ⁺ region can have a high impurity density, and the gate resistance can be reduced.

Next, as shown in Figure 2 d, after polishing it to a flat surface using chemical mechanical polishing technology,
In order to suppress autodoping from the P ⁺ region 3, the n region 14 is formed by epitaxial growth of about 1μ, and then the photoresist 1 is formed using photolithography.
form 3.

Next, as shown in FIG. 2e, after etching the n region 14 and removing the photoresist 13, the n ^- region 2 in the region between the gate and anode is formed by epitaxial growth. At this time, since the surface of the p ⁺ region 3 is covered with the n region 14, no p ⁺ impurity jumps out, the channel 8 is not connected with p type impurities, and the impurity density of the n ^- region 2 is also low. be able to. The thickness of n ^- region 2 is about 70 μm. Next, an n region 10 is grown by epitaxial growth of about 4 μm, and then a p ⁺ region 1, which will become an anode, is formed by epitaxial growth of about 1 to 2 μm. Next, an oxide film 9 is formed by thermal oxidation, etc., and a photoresist 13 is grown by photolithography. form.

Next, as shown in FIG. 2F, after the oxide film 9 is etched away, the photoresist 13 is removed and an n ⁺ region 11 is formed by diffusion or ion implantation. This is connected to the n region 10.

Next, as shown in Fig. 2g, the drawing is turned upside down from here, but n ^- region 4 is the region between the gate and cathode.
Polish away until p ⁺ area 3 is exposed and n ^- area 4
Make the thickness 5μ. Subsequently, a thermal oxide film 9 is formed.

Next, as shown in FIG. 2h, the oxide film 9 is removed by photolithography, ^and the
is formed by diffusion or ion implantation.

Next, as shown in FIG. 2i, the oxide film 9 is removed from the contact hole portions of the n ⁺ region 5 of the cathode region and the p ⁺ region 3 of the gate region by photolithography, and the oxide film 9 of the anode region is removed. After the entire surface is removed, Al electrodes 6 and 15 are formed by vapor deposition or the like over both surfaces of a metal such as Al.

Next, as shown in FIG. 2J, the Al electrode 15 is etched and separated into a cathode electrode 7 and a gate electrode 12 by photolithography.

An electrostatic induction thyristor can be manufactured through the above steps. This thyristor has characteristics such as a small C _GK because the gate and the cathode are far apart, and a large μ because the channel 8 is narrow, and has the excellent characteristics described above. Although an n-channel type will be described here, it is clear that a p-channel type electrostatic induction thyristor can also be produced by changing the conductivity type.

[Brief explanation of the drawing]

FIG. 1a is a sectional view of a conventional electrostatic induction thyristor, FIG. 1b is a sectional view of an electrostatic induction thyristor manufactured according to the present invention, and FIGS. 2a to 2j are process sectional views showing the steps of the present invention. It is. DESCRIPTION OF SYMBOLS 1... Anode, 2... Gate-anode region, 3... Gate, 4... Gate-cathode region, 5... Cathode, 6... Anode metal electrode, 7... Cathode metal electrode, 8... ...Indicates a so-called channel between gates.

Claims (1)

[Claims] 1. Forming a hole whose wall surface is inclined from the main surface using a low impurity density substrate of the first conductivity type as a gate/cathode region, and filling the hole with a high impurity density region of the second conductivity type as a gate. forming a low impurity density region of a first conductivity type on the main surface of the first conductivity type by epitaxial growth and embedding a high impurity density region of a second conductivity type; exposing a second conductivity type high impurity region from the opposite surface of the main surface of the impurity density substrate; and exposing a part of the exposed main surface of the first conductivity type low impurity density substrate as a cathode region. forming a high impurity density region of a second conductivity type on the epitaxial growth surface of the low impurity density region of the first conductivity type as an anode region; and forming a high impurity density region of a second conductivity type as an anode region. A method of manufacturing a semiconductor device, comprising the step of forming a metal electrode on a gate.