JPS63144623A - Frequency dividing circuit - Google Patents

Abstract

PURPOSE:To increase the maximum frequency division frequency by using a frequency divider consisting of two FF circuits and varying the duty ratio of ON/OFF time of the 1st and 2nd transistors (TRs) of a differential amplifiers by a different voltage so as to prolong the read time of data. CONSTITUTION:When the FF of the circuit 1 is in the data read mode, the base bias voltage of a TR 3 is slightly lower than the base bias voltage of a TR 4. Thus, even when the input signal is increased positively and the duty ratio exceeds 50%, the TR 3 is hardly turned on and it takes much time for the TR 3 to be turned on and in the latch mode. With the input signal decreased after in the latch mode once, the TR 3 is turned off before the duty ratio of the input signal reaches 50%, the TR 4 is turned on to form the data read mode. ON the other hand, the circuit block 2 reaches the opposite state as the case with the block 1, and when the input voltage is increased negatively, the read time is extended the same as the case with the FF of the block 1. Thus, the maximum frequency division is increased in both the cases.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a frequency dividing circuit composed of ICCL (emitter coupled logic), and particularly relates to an improvement in frequency dividing ability.

2. Description of the Related Art An example of a frequency divider constructed from a conventional ECL circuit is shown in FIG. 1.2 is a circuit block consisting of equal circuit intercepts,
3.4 is a transistor (hereinafter abbreviated as Tr) constituting an input differential amplifier; s and e are Tr's constituting a flip-flop circuit; 7 and 8 are Tr's constituting a gate for inputting the output of the other block; 9° 1o is the emitter hole)
Tr, 11 is a constant current Tr, 12.degree. 13 is a load resistance. Block 2 also has the same configuration as block 1, so corresponding elements are given the same numbers. 14 is a signal input terminal, 16 is a bias voltage terminal, 16 is a constant current transistor bias terminal, 17 is a power supply terminal, and 18.19 is an output terminal.

Since the input signals are reversely connected in blocks 1 and 2, the operation differs for each half period of the input signal. Block 1 is input 1
4 becomes °'H'', the flip-flop circuits of Tr 5 and Tr 6 are inverted. Similarly, block 2 has input 14
When the signal becomes "L", the flip-flop circuit is inverted. The reason why the blocks can be inverted is because the flip-flop circuit on the other side is inverted half a cycle before, and the gate voltages of Tr7 and Tr8 are inverted. Frequency division is performed by repeating the above operations.

Problems to be Solved by the Invention In the conventional frequency divider circuit, the duty ratio of the input signal clock is 60%, making it impossible to lengthen the reading time. This problem will be explained with reference to FIG. Every half period of the input signal clock from the terminal 14, blocks 1 and 2 alternately repeat a through mode in which data is input and a latch mode in which data is held. That is, when one was in through mode, the other was in latch mode. In this state, the through mode and latch mode require the same amount of time, so only the half periodicity of the input signal clock can be used for data input. Generally, in flip-flops, the time required to latch data is shorter than the time required to read data. Therefore, in conventional frequency dividers, the remaining time of the half period when the latch is stable is wasted time.

In view of these drawbacks of the conventional frequency divider, the present invention improves the frequency division characteristics to the limit of the device.

Means for Solving Mirror Points The present invention provides a frequency divider constituted by first and second flip-flop circuits, the first and second flip-flop circuits constituting a differential amplifier into which a signal to be divided is input. Frequency division in which the bias voltages applied to the bases of the second transistors are different and the duty ratios of the on and off times of the first and second transistors constituting the differential amplifier are varied to lengthen the data read time. It is a circuit.

Effect: The data input time for both of the two flip-flop circuits becomes longer, and the maximum frequency division ability can be improved.

EXAMPLE An example of the present invention is shown in FIG. The same parts as in the conventional example of FIG. 3 are indicated by the same numbers. Blocks 1 and 2 have the same circuit configuration, 3.4 is a transistor (hereinafter abbreviated as Tr) that constitutes an input differential amplifier, 6 and 6 are Tr that constitutes a flip-flop circuit, and 7 and 8 are the outputs of the other block. Tr that constitutes the input gate, 9.10 is the emitter O'7
Tr, 11 is a constant current Tr, 12. '+3 is the load resistance. Block 2 also has the same configuration as block 1, so corresponding elements are given the same numbers. 14 is a signal input terminal, 15 is a bias voltage terminal, 16 is a constant current transistor bias terminal, 17 is a power supply terminal, and 18.19 is an output terminal. 20 and 21 are bias adjustment resistors.

The basic operation is the same as in FIG. Depending on the signal clock input from the terminal 14 and the bias voltage from the terminal 16, the on/off of the differential amplifier 3.4 and the on/off of the flip-flop 5.6 are determined.

Therefore, by adjusting the voltage biased to the differential amplifier 4, the duty ratio of the flip-flop can be changed. This operation will be explained using the input/output waveforms shown in FIG. Flip-flop of circuit block 1 (hereinafter abbreviated as FF1)
Assume that the device is in data reading mode with Tr3 turned off and Tr4 turned on. At this time, terminal 14, that is, T
The base bias voltage of r3 is at terminal 1 due to the resistor 2o.
5, that is, slightly lower than the base bias voltage of Tr+. Therefore, even if the input signal voltage increases in the positive direction and the duty ratio exceeds 50%, Tr3 is difficult to turn on. That is, it takes time for Tr3 to turn on and enter the latch mode. Further, even once the latch mode is entered, if the input signal starts to decrease, Tr3 will be turned off before the duty ratio of the input signal reaches 50%. For this reason, Tr4 is turned on and the data reading mode is entered. In this way, the reading time becomes longer and the latch period becomes shorter within one cycle. Generally, the latch operation is a positive feedback operation, so the latch mode is entered in a shorter time than the read time. Therefore, there is no problem even if the latch mode is shortened. Therefore, since there is a margin in the data reading time, it is possible to improve the frequency limit at which normal input/output operations can be performed. on the other hand.

In the case of the flip-flop (abbreviated as FF2) of circuit block 2, the base bias voltage of Tr3 is slightly higher than that of Tr4 due to the resistor 21, and the input signal voltage increases in the negative direction. Therefore, like FF1, the reading time becomes longer. As described above, the maximum frequency division frequency can be increased, and the frequency division capability can be improved.

Effects of the Invention As described above, according to the present invention, the duty ratio of the flip-flop is increased using the bias adjustment resistor, so that the maximum frequency division ability can be improved and the device characteristics can be utilized to the maximum.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a frequency divider in an embodiment of the present invention, Fig. 2 is an input/output technique diagram to explain the increase in data reading time due to the frequency divider, and Fig. 3 is a conventional frequency divider. FIG. 4 is a waveform diagram for explaining a conventional frequency divider. 1.2...Circuit block, 3.4...
Input differential amplifier, 6,6...Flip-flop, 7.8...Input gate transistor, 9,1
o...Emitter follower transistor, 11...
...constant current transistor, 12.13...
Load resistance, 14...Signal input terminal, 15...
... Bias voltage terminal, 16 ... Bias terminal for constant current transistor, 17 ... Power supply terminal,
18.19... Output terminal, 20.21...
...Resistance for bias adjustment. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure T-m-Through mode Y L-m-Latch t-g--1→Yo-mai 4th figure--Through mode V 1゛°-La Nora mode

Claims (1)

[Claims] A frequency divider circuit configured with a bipolar ECL circuit combining first and second flip-flop circuits, the bases of the first and second transistors forming a differential amplifier into which a signal to be frequency-divided is input. A frequency dividing circuit configured to lengthen the data reading time by varying the bias voltage applied to the differential amplifier and changing the duty ratio of the on/off time of the first and second transistors constituting the differential amplifier.