JP2856102B2 - Flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit, and more particularly to a vertical two-stage emitter coupled logic (ECL; Emit).
The present invention relates to a flip-flop circuit having a function of preventing data through of a master-slave flip-flop circuit having a “ter Coupled Logic” configuration.

[0002]

2. Description of the Related Art Conventionally, a flip-flop circuit having an ECL structure has a first differential circuit for inputting a data signal with respect to a high-potential reference potential and a second differential circuit for holding the data.
And a third differential circuit for inputting a clock signal with respect to a low-potential reference potential for controlling the function of reading and holding data. It is configured as a so-called master-slave flip-flop circuit having a so-called vertical two-stage ECL configuration in which an output signal of the master-side latch circuit is read as a data signal of the slave-side latch circuit.

The master latch circuit and the slave latch circuit alternately perform a data reading function and a data holding function in response to a clock signal, so that input signal data is triggered by a rising or falling edge of a clock. And output.

In the master-slave type flip-flop circuit having such a configuration, when the clock signal moves in the direction opposite to the edge of the trigger, both the master and slave latch circuits determine where to hold their own output signal. In both cases, a data reading state occurs transiently, and a problem of a data through phenomenon that a data signal is output as it is occurs.

[0005] As a conventional master-slave type flip-flop circuit provided with means for avoiding data through, there is a circuit configuration as shown in FIG. 5 (referred to as a "first conventional example").

This flip-flop circuit has a vertical two-stage E
It is composed of a master-slave flip-flop circuit having a CL configuration, and has a clock (CK) input terminal 1 and data (D)
Input terminal 2, Q and QB output terminals 3, 4, VCC power supply terminal 5, VEE power supply terminal 6, npn transistor 1
1 to 29, resistors 31 to 42, and constant current sources 80 to 82.

[0007] Transistors 12, 15, Transistor 1
The emitters of the transistors 3 and 14 and the transistors 16 and 17 are commonly connected to each other, and the first to third transistors of the master side latch circuit are connected.
(Referred to as “first to third”, respectively).
Transistors 18 and 19 constitute a master-side emitter follower circuit, and include resistors 33 and
Reference numeral 34 denotes an emitter follower resistor.
2 is a collector load resistance on the master side. The first constant current source 80 is connected between the commonly connected emitters of the third differential pair transistors 16 and 17 and the VEE power supply terminal 6, and flows the constant current ICS1.

Further, the transistors 20, 23, the transistors 21, 22, and the transistors 24, 25 have their emitters commonly connected to each other to form fourth to sixth differential pair transistors on the slave side ("fourth to sixth", respectively). 6), the transistors 26 and 27 form an emitter follower circuit on the slave side, and the resistors 37 and 38
Is an emitter follower resistance, and the resistors 35 and 36 are collector load resistors on the slave side. Second constant current source 81
Is connected between the commonly connected emitters of the sixth differential pair transistors 24 and 25 and the VEE power supply terminal 6, and flows the constant current ICS1.

The transistor 11 whose base is connected to the clock input terminal 1 forms an emitter follower circuit, and the resistor 41 is an emitter follower resistor.

The transistors 28 and 29 whose bases are connected to the collectors of the transistors 20 and 23 are emitter follower transistors at the output stage, and the resistors 39 and 40 are emitter follower resistors at the output.

A power supply on the high potential side is applied to the VCC power supply terminal 5, and a power supply voltage on the low potential side is applied to the VEE power supply terminal 6.

The data signal input to the data input terminal 2 is input to the base of the transistor 12 of the first differential circuit on the master side, and the clock (CK) input to the clock input terminal 1 causes the emitter follower transistor 11 to operate. The signal is input to the bases of the transistors 16 and 25 of the third and sixth differential circuits through the third and sixth differential circuits. The potential drop appearing on the master-side collector load resistors 31 and 32 is extracted as an output data signal of the master-side latch circuit via the emitter-follower transistors 18 and 19, and the fourth differential pair transistors 23 and 20 on the slave side are extracted. Fill in the base.

The base of the transistor 30 has a reference potential (V
R1), the collector is connected to the VCC power supply 5, and the emitter is connected to a common connection point between the base of the transistor 24 and one end of the resistor 42 of the sixth differential circuit located on the low potential side on the slave side. I have. Note that the reference potential (VR
1) is also connected to the base of the transistor 15 of the first differential circuit, and gives a high-potential-side reference potential. The other end (low potential side) of the resistor 42 is connected to the base of the transistor 17 of the third differential circuit and the third constant current source 82 located on the low potential side of the master side. Is the constant current ICS2
Is shed.

The operation of the conventional master-slave flip-flop circuit shown in FIG. 5 will be described.

A low potential (Low) is applied to the clock signal input terminal 1.
Level), the transistor 17 of the third differential circuit located on the low potential side of the master is on, the transistor 16 is off, and the data signal input terminal Either one of the first differential pair transistors 12 and 15 located on the high potential side on the master side operates according to the potential of the data signal input to 2, and has a data reading function. At this time, since the transistor 16 is in the off state, the current path is cut off and the second path located on the high potential side on the master side is turned off.
The differential pair transistors 13 and 14 are both turned off.

At this time, the transistor 24 of the sixth low-potential differential circuit on the slave side is turned on and the transistor 25 is off, so that the fourth high-potential differential circuit on the slave side is turned off. The paired transistors 20 and 23 are turned off, and the output signal state of the slave side latch circuit is fed back to the bases of the fifth differential paired transistors 21 and 22 by the transistors 26 and 27 having an emitter follower configuration. Either one of them becomes active and has a data holding function.

On the other hand, when the clock signal (CK) input to the clock signal input terminal 1 is at a high potential (High level), the operation opposite to the above-described operation is performed in each of the master and slave latch circuits. More specifically, the output signal state of the master side latch circuit is fed back to the bases of the second differential pair transistors 13 and 14 by the transistors 18 and 19 having an emitter follower configuration, and one of the transistors 13 and 14 is turned on. The fourth differential pair transistor 2 has an operation state, has a data holding function, and has, on the slave side, the base inputs of the outputs of the transistors 18 and 19 having an emitter follower configuration on the master side.
Either one of 0 and 23 becomes an operating state, and has a function of reading output data from the master side latch circuit.

Next, the operation of the first conventional master-slave flip-flop circuit shown in FIG. 5 for preventing data through will be described.

In this conventional example, the resistor 42 is connected to the reference voltage generating circuit (constituted by the transistor 30 having the reference potential VR1 as a base input) of the third and sixth differential circuits on the low potential side.
And the third constant current source 82 are connected in series, the high-potential terminal of the resistor 42 is connected to the base of the transistor 24 of the third differential circuit on the slave side, and a reference potential is applied. Is connected to the base of the transistor 17 of the sixth differential circuit on the master side to apply a reference potential.

With such a circuit configuration, the reference potential of the differential circuit on the low potential side on the master side is supplied to the resistor 42 having a resistance value R42 higher than the reference potential on the slave side.
Potential drop (R42)
× ICS2).

For this reason, as shown in FIG. 6, the clock signal (CK) changes from a high potential to a low potential (High → Low).
In the transition from the data holding operation to the data reading operation in the master-side latch circuit, the clock signal (CK) further increases the potential (=
R42 × ICS2) is performed when the voltage has dropped by the amount of (R42 × ICS2). In other words, between the point in time when the data is read from the slave and the time when the data is read, the time when the data is read from the data in the master and the data is read.
A time difference Δt is provided to prevent both the master and slave latch circuits from being in the read state, thereby preventing data through.

However, the potential drop (= R4
If (2 × ICS2) is, for example, 36 mV, the noise margin (noise margin) on the low potential (Low) side of the clock signal (CK) is reduced by 36 mV, and the operation becomes unstable.

Further, the time difference Δt is generated by lowering the threshold voltage (threshold voltage) from the center of the signal amplitude without adjusting the reference voltage of the third differential circuit on the low potential side on the master side. FIG. 7 shows a configuration of a conventional master-slave type flip-flop circuit configured to prevent the through (referred to as "second conventional example") (see Japanese Patent Application Laid-Open No. 2-135913).

In FIG. 7, elements having the same functions as those in FIG. 5 are denoted by the same reference numerals. In the following, FIG.
Only the structural differences from the first conventional example shown in FIG.

Referring to FIG. 7, the resistor 42 provided in the first conventional example shown in FIG. 5 is omitted, and a plurality of transistors 16 of the third differential circuit on the low potential side on the master side are provided. (For example, three) transistors 16-1 to 16-3 connected in parallel with each other, and a third constant current source 82
Is replaced by a resistor 44. Transistor 16-1
16-3 are the transistors 1 of the clock signal (CK)
1, the emitter follower output signal is commonly input to the base, the collector is commonly connected to the commonly connected emitters of the second differential pair transistors 13, 14, and the emitter is also commonly connected to the first constant It is connected to a current source 80.

The operation of the flip-flop circuit shown in FIG. 7 will be described below.

The first and second constant current sources 80 and 81 on the master side and the slave side cause a constant current ICS1 to flow through the third differential pair transistors 16, 17 and the sixth differential pair transistors 24, 25. Then, the transistor 16 has three transistors 16-1, 16-2, 16- having the same shape (dimensions) as the other transistors 17, 24, 25.
3, the current flowing per one of the transistors 16-1, 16-2, and 16-3 is one third (=) of the current value ICS1 of the first constant current source 80. ICS1 / 3).

The relationship between the operating voltage and the current of the transistor satisfies the following equation (1).

[0029]

(Equation 1)

Where I is the operating emitter current, V is the operating base-emitter voltage, Ie is the saturation current density, q is the charge, n is the emission coefficient, k is the Boltzmann constant,
Indicates a temperature.

As shown in FIG. 7, the transistor 16-
Assuming that the base-emitter voltage when the constant current ICS1 flows through 1, 16-2 and 16-3 is Vf, the current is shunted to the three transistors 16-1, 16-2 and 16-3. And the following equation (2) holds.

[0032]

(Equation 2)

That is, from the above equation (2), the operating voltage of the transistor 16 including the plurality of transistors 16-1, 16-2, and 16-3 is reduced by ΔVf = 28 mV.

Therefore, when the clock signal (CK) transitions from the high potential to the low potential (High → Low), the threshold level of the master side with respect to the clock signal (CK) is changed as shown in FIG. Since ΔVf = 28 mV lower than the threshold level on the slave side, which is the center of the amplitude of (CK), the transition from the data holding on the master side to the data reading operation is shorter than the transition from the data reading on the slave side to the data holding operation. , The time difference Δt, and data through can be prevented.

In this case, however, in the latch circuit on the master side, the low potential (L) of the clock signal (CK) is applied.
There is a problem that the noise margin on the ow) side is reduced by ΔVf (= 28 mV) and the operation becomes unstable.

[0036]

The above-mentioned conventional vertical type 2
The master-slave flip-flop circuit having the stage ECL configuration adjusts the master-side reference potential of the differential circuit that controls the data reading and holding functions to a lower potential side, or shifts the threshold level for the master-side clock signal to the lower potential side. For the adjustment, there is a problem that the noise margin for the clock signal on the master side is significantly reduced.

Accordingly, the present invention has been made to solve the above-mentioned problems, and to provide a master-flavor type flip-flop circuit which prevents data through while securing a noise margin in a vertical two-stage ECL configuration master-slave type flip-flop circuit. With the goal.

[0038]

In order to achieve the above object, the present invention provides a first differential circuit for inputting data, a second differential circuit for holding the data, and the first and second differential circuits. The third controlling the data input and data retention of the second differential circuit
Master-side latch circuit, a fourth differential circuit for inputting output data of the master-side latch circuit, and a fifth differential circuit for holding output data of the fourth differential circuit. And the data of the fourth and fifth differential circuits .
A slave-side latch circuit having a sixth differential circuit for controlling data input and data retention , and a vertical two-stage emitter-coupled logic flip-flop circuit including the third circuit.
Differential circuit, a first predetermined electric 圧離 from the center of the amplitude of the signal
Levels with respect conductive position, said sixth differential circuit is opposite to the first predetermined voltage from the center of the amplitude of the signal of the code
To a second predetermined electric 圧離levels is a voltage with a reference electric position
A flip-flop circuit characterized in that:

In the present invention, preferably, the third
And the sixth differential circuit is composed of a pair of transistors having the same shape. The differential circuit is composed of a pair of transistors having the same shape. A level higher than the center of the amplitude of the signal by the predetermined potential (ΔV2) is set as a reference potential.

In the present invention, preferably, ΔV
1 and ΔV2 are both set in the range of several mV to several tens mV. In the present invention, preferably, ΔV1 and ΔV2 are set to substantially equal values.

According to a preferred embodiment of the present invention, the third
The base of the first transistor on the signal input side of the differential circuit is connected to the base of the second transistor on the signal input side of the sixth differential circuit, and the reference potential side of the third differential circuit is connected. The base of the third transistor is connected to the base of the fourth transistor on the reference potential side of the sixth differential circuit, and the first transistor is composed of a plurality of transistors having the same shape as the third transistor. The fourth transistor is connected in parallel with each other, and the fourth transistor is connected to the second transistor.
And a transistor having the same shape as that of the first transistor and connected in parallel with each other in the same number as the number of transistors constituting the first transistor.

According to a preferred embodiment of the present invention, the third
The base of the first transistor on the signal input side of the differential circuit is connected to the base of the second transistor on the signal input side of the sixth differential circuit, and the reference potential side of the third differential circuit is connected. The base of the third transistor is connected to the base of the fourth transistor on the reference potential side of the sixth differential circuit, and the first transistor has a predetermined multiple (A times) the size of the third transistor. , A> 1), and the fourth transistor may be a transistor having a size A times the size of the second transistor.

In a preferred aspect of the present invention, a circuit for supplying a reference voltage to one input terminal of each of the third and sixth differential circuits is connected in series between a high potential power supply and a low potential power supply. A circuit configured to include a first emitter follower transistor, an emitter follower resistor, and a first constant current source, and to supply a clock signal to the other input terminals of the third and sixth differential circuits, respectively; Comprises a second emitter follower transistor having a clock signal as a base input, and a second constant current source flowing the same current value as the first constant current source. A predetermined reference voltage is input to a base, and a high potential side terminal of the emitter follower resistor is connected to the one input terminal of the sixth differential circuit on the slave side, and the emitter follower is connected to the input terminal. A low-potential-side terminal of the resistor is connected to the one input terminal of the third differential circuit on the master side, and the first emitter follower transistor includes a plurality of transistors having the same shape as the second emitter follower transistor. It is characterized by being connected in a parallel configuration.

Further, the present invention provides, as a preferred embodiment,
A circuit for supplying a reference voltage to one input terminal of each of the third and sixth differential circuits includes a first emitter follower transistor connected in series between a high-potential power supply and a low-potential power supply; And a circuit that supplies a clock signal to each of the other input terminals of the third and sixth differential circuits, the circuit including a clock signal as a base input. Two emitter follower transistors, a second emitter follower resistor, and the first
, And a second constant current source that supplies the same current value. A predetermined reference voltage is input to the base of the first emitter follower transistor, and the first emitter follower resistor is connected to the second emitter. 2 having a resistance value that is a predetermined multiple of the emitter follower resistance of 2, and connecting a high potential side terminal of the first emitter follower resistance to the one input terminal of the sixth differential circuit on the slave side; A low potential side terminal of a first emitter follower resistor is connected to the one input terminal of the third differential circuit on the master side, and the first emitter follower transistor is the same as the second emitter follower transistor A plurality of transistors having different shapes are connected in parallel.

[0045]

According to the present invention, the differential circuit to which the clock is input in the master-side latch circuit has a threshold value which is lower by about several mV to several tens mV than the center of the signal amplitude of the clock, and the clock is input to the slave-side latch circuit. The differential circuit used as the threshold has a level several mV to several tens mV higher than the center of the signal amplitude of the clock, thereby preventing data through and reducing the noise margin of the clock signal by about 1 / 2 to achieve stable operation. In the present invention, when the threshold levels of the third and fifth differential circuits are adjusted only by transistors, a more stable flip-flop circuit can be realized. Further, according to the present invention, even when the current amplification factor hFE of the transistor is significantly reduced, the difference in the level shift amount due to the fluctuation of the current amplification factor hFE is reduced, thereby reducing the variation in transistor manufacturing. A more stable flip-flop can be realized.

[0046]

Embodiments of the present invention will be described below with reference to the drawings.

[0047]

FIG. 1 shows a vertical two-stage E according to a first embodiment of the present invention.
FIG. 3 is a diagram illustrating a circuit configuration of a master-slave flip-flop circuit having a CL configuration. In FIG. 1, elements having the same functions as those in FIG. 5 are denoted by the same reference numerals.

Referring to FIG. 1, in the present embodiment, a CK (clock) input terminal 1, a D (data) input terminal 2, and Q, Q
B output terminals 3 and 4, a VCC power terminal 5, a VEE power terminal 6, npn transistors 11 to 30, resistors 31 to
42 and four constant current sources 80 to 83.

Transistors 12, 15, Transistor 1
The emitters of the transistors 3, 14 and the transistors 16, 17 are commonly connected to each other to form master-side first to third differential pair transistors (also referred to as "first to third differential circuits", respectively). Reference numerals 18 and 19 constitute a master-side emitter follower circuit, resistors 33 and 34 are emitter follower resistors, and resistors 31 and 32 are master-side collector load resistors. The first constant current source 80 is connected between the commonly connected emitters of the third differential pair transistors 16 and 17 and the VEE power supply terminal 6, and has a constant current IC
Flow S1.

The transistors 20 and 23, the transistors 21 and 22, and the transistors 24 and 25 have their emitters commonly connected to each other and have the fourth to sixth differential pair transistors on the slave side (each of which is called the "fourth to sixth differential transistor"). Motion circuit ''
), And transistors 26 and 27 constitute an emitter follower circuit on the slave side, and resistors 37 and 38
Is an emitter follower resistance, and the resistors 35 and 36 are collector load resistors on the slave side. Second constant current source 81
Is connected between the commonly connected emitters of the sixth differential pair transistors 24 and 25 and the VEE power supply terminal 6, and flows a constant current ICS1.

The transistors 28 and 29 are output-follower emitter follower transistors, and the resistors 39 and 40 are output emitter-follower resistors.

The transistor 11 whose base is connected to the clock input terminal 1 forms an emitter follower circuit.
Is a current source of an emitter follower.

In this embodiment, the transistor 30
Is configured by commonly connecting collectors, bases, and emitters of two transistors 30-1 and 30-2 having the same characteristics as the transistor 11, and a base is connected to a reference potential (VR1).

The VCC power supply terminal 5 is supplied with a high-potential-side power supply, the VEE power supply terminal 6 is supplied with a low-potential-side power supply voltage, and the third and fourth constant current sources 82 and 83 have the same constant current. ICS2 is played.

Next, the operation of the master-slave flip-flop circuit of this embodiment will be described.

A low potential (Low) is applied to the clock signal input terminal 1.
Level), the transistor 17 of the third differential circuit on the low potential side on the master side is in the ON state, the transistor 16 is in the OFF state, and the master side latch circuit is Data signal input terminal 2
One of the first differential pair transistors 12 and 15 is activated according to the potential of the data signal (D) input to the first transistor, and has a data reading function.

At this time, the transistor 24 of the sixth differential circuit on the low potential side on the slave side is turned on, and the transistor 2 is turned on.
5 is in the OFF state, and the slave side latch circuit outputs its own output signal state to the emitter follower transistors 26, 2
7, the signal is fed back to the bases of the fifth differential transistors 21 and 22 and one of the fifth differential transistors 21 and 22 is activated, and has a data holding function.

On the other hand, when the clock signal is at a high potential (High level), as described in the first conventional example,
The operation opposite to the above operation is performed in each of the latch circuits on the master side and the slave side. The master side has a data holding function, and the slave side has a data reading function.

Next, the operation of the master-slave type flip-flop circuit of this embodiment for preventing data through will be described.

In this embodiment, the resistor 42 and the third constant current source are connected to the reference voltage generating circuit input to the reference potential side (bases of the transistors 17 and 24) of the third and sixth differential circuits on the low potential side. 82 is connected in series, the high potential side terminal of the resistor 42 is connected to the base of the transistor 24 of the sixth differential circuit on the slave side, and the low potential side terminal of the resistor 42 is connected to the third differential terminal on the master side. The circuit is connected to the base of the transistor 17 of the circuit.

With such a circuit configuration, the reference potential VR
When 1 is set at the center of the amplitude of the clock signal (CK),
The current of the third constant current source 82 is
Since the current is diverted at 0-2, the following equation (3) holds.

[0062]

(Equation 3)

The reference potential (base potential of the transistor 24) of the sixth low-potential side differential circuit on the slave side is a clock signal (CK) input to the base of the transistor 25.
.DELTA.Vf = about 18 mV higher than the center of the amplitude.

The reference potential (base potential of transistor 17) of the third differential circuit on the low potential side on the master side is:
The voltage is lower by a voltage drop (R42 × ICS2) caused by the flow of the constant current ICS2 of the constant current source 83 through the resistor 42 having the resistance value R42 than the slave side.

When the potential drop of the resistor 42 is set to, for example, 36 mV, the reference potential of the third differential circuit on the low potential side on the master side becomes lower by 18 mV than the center of the amplitude of the clock signal (CK).

As shown in FIG. 2, the clock signal (CK)
At the time of transition from High potential to low potential (High → Low), the transition from data holding to data reading operation in the master latch circuit is compared with the transition from data reading to data holding operation in the slave latch circuit. Is performed when the clock signal voltage further decreases by 36 mV, the time difference Δt between the transition from the data reading on the slave side to the data holding and the transition from the data holding on the master side to the data reading on the master side
This prevents both the master and slave latch circuits from being in a read state, thereby preventing data through.

In this embodiment, the difference between the reference voltages of the third and sixth differential circuits on the master side and the slave side for controlling data reading and data holding is, for example, 36 mV.
Even when the data through is prevented, the difference between the center of the amplitude of the clock signal and each reference voltage is adjusted by 18 mV in the low potential direction on the master side and by 18 mV in the high potential side direction on the slave side. Therefore, the reduction of the noise margin of the clock signal (CK) does not become 36 mV as in the first conventional example, but becomes 18 mV on both the low potential side and the high potential side. In comparison, the reduction of the noise margin can be halved, and a stable operation is realized.

[0068]

Embodiment 2 FIG. 3 is a diagram showing a circuit configuration of a flip-flop circuit according to a second embodiment of the present invention. In FIG.
Elements having the same functions as those in FIG. 1 are denoted by the same reference numerals.

In this embodiment, in the flip-flop circuit of the second conventional example shown in FIG. 7, the transistor 16 of the third differential circuit on the master side is replaced by two transistors 16-1 and 16-2. And the transistor 24 of the sixth differential circuit on the slave side is replaced with two transistors 24-
1, 24-2, and the emitter follower resistor 4 shown in FIG.
1 is replaced by a fourth current source 83 that allows a current equal to that of the third constant current source 82 to flow.

The reference voltage VR1 is applied to the clock signal input terminal 1
Clock signal input terminal 1
Clock signal (CK) input to the reference voltage VR1
Are the fourth and third constant current sources 83 and 8 having the same current value.
2 are input to the emitter follower transistors 11 and 30 respectively connected to the emitters and are level-shifted equally. Therefore, the threshold level of the third differential circuit including the differential pair transistors 16 and 17 is determined by the amplitude of the clock signal (CK). 18mV (= ΔVf) lower than the center, and the threshold level of the sixth differential circuit including the differential pair transistors 24 and 25 becomes higher by about 18 mV, thereby securing the same noise margin as in the first embodiment. While preventing data through.

In the first embodiment, the threshold level is adjusted by using transistors (transistors 30-1 and 30-2).
In this embodiment, the transistors (16-1, 16-2, 24-1, 24-2) are used.
Since the operation is performed only by the resistor, a more stable flip-flop circuit can be realized without being affected by manufacturing variations of the resistor.

In the present embodiment, the size of the transistor 16 of the third differential circuit on the master side is set to a predetermined value (for example, the emitter area is twice) the size of the transistor 17 having the reference voltage as the base input, and The size of the transistor 24 of the sixth differential circuit may be configured to be a predetermined multiple (for example, the emitter area is twice) of the transistor 25 having the clock signal voltage as the base input.

[0073]

Third Embodiment FIG. 4 is a diagram showing a configuration of a flip-flop circuit according to a third embodiment of the present invention. In FIG. 4, FIG.
Elements having the same functions as those described above are denoted by the same reference numerals.

In this embodiment, the resistor 42 of the first embodiment shown in FIG. 1 is constructed by connecting two resistors 42-1 and 42-2 having the same resistance value R42 in series. I have. In addition, a transistor 1 having an emitter follower configuration
A resistor 43 having a resistance value R42 is provided between the emitter 1 of the first differential circuit, the bases of the transistors 16 and 25 of the third and sixth differential circuits, and the connection point of the fourth constant current source 83 of the ICS2. It is connected. The transistor 30 is configured by commonly connecting the collectors, bases, and emitters of two transistors 30-1 and 30-2 having the same characteristics as the transistor 11, and the base is supplied with a reference potential (VR1). Is done.

The base potential of the transistor 16 of the third differential circuit on the master side to which the clock signal (CK) is input is level-shifted by ICS2 × R42 = 18 mV by the resistor 43, and the base potential of the transistor 17 is two. ICS2 × R from reference voltage by resistors 42-1 and 42-2
The level is shifted by 42 × 2 = 36 mV, and the level difference becomes 18 mV, as in the first embodiment. The data margin can be prevented while securing the same noise margin as in the first embodiment.

In this embodiment, since the level-shifted signal and the constant potential are connected to the respective bases of the differential pair transistors 16 and 17 on the master side by the resistors 43 and 42, the current amplification factor hFE of the transistors is significantly reduced. In this case, the difference between the respective level shift amounts due to the fluctuation of the current amplification factor hFE is approximately 比較 compared to the first embodiment, and a flip-flop more stable against variations in transistor manufacturing and the like is realized. it can.

Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment, but includes various embodiments according to the principle of the present invention.

[0078]

As described above, according to the present invention, the vertical type 2
In a master-slave flip-flop circuit including a stage ECL, a differential circuit to which a master-side clock is input has a threshold value set at a level several mV to several tens mV lower than the center of the clock amplitude, and a slave-side clock is input. Is several mV from the center of the clock amplitude.
Means for setting a high level to a threshold of several tens of mV to reduce the voltage margin of the clock signal by about 1 /
2, while preventing data through. Further, according to the present invention, even when the current amplification factor hFE of the transistor is significantly reduced, the current amplification factor hFE is reduced.
Is configured to reduce the difference between the respective level shift amounts due to the fluctuation of the transistor, it is possible to realize a flip-flop that is more stable against variations in transistor manufacturing and the like.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart schematically showing an operation of preventing data through in the first embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a third embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a conventional example.

FIG. 6 is a timing chart schematically showing an operation of preventing data through of the circuit of FIG. 5;

FIG. 7 is a diagram showing a circuit configuration of another conventional example.

8 is a timing chart schematically showing an operation of preventing data through of the circuit of FIG. 7;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 clock signal input terminal 2 data signal input terminal 3, 4 output signal terminal 5 high-potential-side power supply voltage terminal 6 low-potential-side power supply voltage terminal 11 input emitter follower transistor 12 to 17 master-side differential transistor 20 to 25 Slave-side differential transistor 18, 19 Emitter follower transistor 26, 27 Emitter follower transistor 28, 29 Emitter follower transistor 31, 32 Collector load resistance 33, 34 Emitter follower resistance 35, 36 Collector load resistance 37, 38 Emitter follower resistance 39, 40 Emitter follower resistance of output 41 Emitter follower resistance of input 42, 43 Level shift resistance 44 Emitter follower resistance of reference potential 80, 81, 82, 83 Constant current source

Claims (4)

(57) [Claims] A first differential circuit for inputting data; a second differential circuit for holding the data; and a data input and data holding for the first and second differential circuits. A master-side latch circuit having a third differential circuit that controls the output voltage of the master-side latch circuit;
A fifth differential circuit that holds output data of the fourth differential circuit , and controls data input and data holding of the fourth and fifth differential circuits. A vertical two-stage emitter-coupled logic flip-flop circuit including: a sixth differential circuit; and a slave-side latch circuit having the same. where <br/> a constant-圧離levels reference potential level, said sixth differential circuits, the the center of the amplitude of the signal first
The second predetermined electric 圧離 a predetermined voltage between the opposite voltage sign
The reference potential level of the level, the flip-flop circuit, characterized in that. 2. An input terminal of one of the third and sixth differential circuits.
The circuits that supply the reference voltage to the
First emitter follower connected in series between potential power supplies
Transistor, an emitter follower resistor, and a first constant
And a current source, and connected to the other input terminals of the third and sixth differential circuits, respectively.
A circuit that supplies the lock signal
A second emitter-follower transistor,
A second constant current source that supplies the same current value as the first constant current source;
At the base of the first emitter follower transistor.
A constant reference voltage is input, and the high potential side terminal of the first emitter follower resistor is connected to the
Connected to the one input terminal of the sixth differential circuit on the slave side
Continued, and the master the low potential side terminal of the emitter follower resistor
Connected to the one input terminal of the third differential circuit on the negative side, and an emitter surface of the first emitter follower transistor.
The product is the emission of the second emitter follower transistor.
2. The flip-flop circuit according to claim 1, wherein the flip-flop circuit is configured to be wider than the data area . 3. The first emitter follower transistor
The flip-flop circuit according to claim 2 , wherein a plurality of transistors are connected in parallel . 4. An input terminal of one of said third and sixth differential circuits.
The circuits that supply the reference voltage to the
First emitter follower connected in series between potential power supplies
Transistor, a first emitter follower resistor, and a
1 constant current source, and is connected to the other input terminals of the third and sixth differential circuits, respectively.
A circuit that supplies the lock signal
A second emitter-follower transistor,
The same as the first constant current source
And a second constant current source through which the current value of the second emitter flows.
The first emitter follower resistor has a resistance value that is a predetermined multiple of a follower resistance, and the high potential side terminal of the first emitter follower resistor is
Connected to the one input terminal of the sixth differential circuit on the slave side
It continued, and the said first low-potential-side terminal of the emitter follower resistor
Connected to the one input terminal of the third differential circuit on the master side
4. The flip-flop circuit according to claim 2 , wherein the flip-flop circuit is configured in a series .