JPS63143659A - Local memory control system - Google Patents

Abstract

PURPOSE:To miniaturize a system by controlling whether the registered contents of a local memory in a shown CPU is to be invalidated or not in accordance with the state of a display element at the time of receiving a rewriting address of another not shown CPU memory. CONSTITUTION:When the other CPU executes memory rewriting and its rewriting address A3 is informed from the other CPU, the sent rewriting address A3 is stored in an address register 45. Then, a check circuit 47 reads out the contents (1 bit) of an entry 55 in a flag register 5 corresponding to the rewriting address A3. When the read contents are '1', the circuit 47 turns the contents of the entry 55 in the register 5 to '0' and turns the effective flag of an entry 23 in an address array 2 specified by specific 3 bits in the rewriting address A3 to '0'. Since whether the rewriting address A3 informed from the other CPU is registered in an address array 2 or not can be decided by the contents (1 bit) of the entry 55 of the flag register 5 specified by the address A3, the check circuit 47 can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a measure for matching the stored contents of local memories between CPUs in an information processing apparatus having a multiprocessor configuration.

(Prior Art) FIG. 3 shows the configuration of a local memory in a conventional information processing device, where 1 is a local memory, 2 is an address array that stores addresses of information held in the local memory, and 3 is a diagram showing the configuration of a local memory in a conventional information processing device. Copy of address array 2, 41 is CPU
An address register that holds memory access addresses from each internal control unit, 42 a data register that holds information written to the memory, and 43 a coincidence detection circuit that detects a match between the contents of the address array 2 and the contents of the address register 41. , 44 is a data register that holds read information from the local memory 1, 45 is an address register that holds a memory rewrite address sent from another CPU,
Reference numeral 46 denotes a coincidence detection circuit that detects coincidence between the contents of copy 3 of address array 2 and the contents of address register 45.

When the CPU refers to the memory, an access address (AI) is first stored in the address register 41.

Next, the match detection circuit 43 selects the access address (A1).
The entry 21 of the address array 2 specified by the specific three bits is read out and checked to see if it is equal to the access address (A1).

If the access address (A1) is equal to the contents of the address field of the entry 21 and the valid flag of the entry 21 is "1", the information (Dl) stored in the corresponding entry 11 of the local memory 1 is transferred to the data register 44. and forward it to the requester.

If the access address (Al) is different from the contents of the address field of entry 21 of address array 2, or if the valid flag of entry 21 is LL OI+, the access address (A1) is sent to the main memory and Read the information stored in. The information (Dl) read from the main memory is registered in the entry 11 of the local memory 1 specified by the specific 3 bits of the access address (A1), and is sent to each control unit via the data register 44. It will be done.

Furthermore, the access address (AI) is stored in the address field of the entry 21 of the address array 2 corresponding to the entry 11 of the local memory 1 and the entry 31 of the copy 3 of the address array, and the valid flag of each entry is set to 1'''. shall be.

When rewriting the memory from the CPU, first, the rewriting address (A2) is stored in the address register 41, and the rewriting information (D
2) is stored in the data register 42.

Next, the match detection circuit 43 reads the entry 22 of the address array 2 specified by the specific three bits of the rewritten address (A2), and checks whether it is equal to the rewritten address (A2).

Rewrite address (A2) and address array 2 en = 3
- If the internal addresses of the memory register 22 are equal and the valid flag of the entry 2I is 1'', the contents of the corresponding entry 12 of the local memory I are transferred to the contents of the data register 42 (D
Rewrite according to 2).

Also, the address register 41. The contents of the data register 42 are sent to the main memory, and the stored contents of the main memory are rewritten.

Further, the contents of the address register 41 (rewrite address (Al)) are notified to other CPUs so that there is no mismatch in the contents stored in local memories between CPUs.

When the rewrite address (A3) is notified from another CPU, the sent rewrite address (A3) is first stored in the address register 45.

Next, the coincidence detection circuit 46 detects copy 3 of the address array specified by the specific 3 bits of the rewrite address (A3).
The entry 23 is read and checked to see if it is equal to the rewrite address (A3).

If the rewritten address (A3) is equal to the contents of the address field of entry 33 and the valid flag of entry 33 is "1", the valid flag of entry 33 and the corresponding entry 23 of address field Ray 2 are set to "0". .

In this way, in conventional computers, in order to check whether the information of the rewritten address notified from another CPU is registered in the local memory 1, a copy 3 of the address array and a match detection circuit are installed for each connected CPU. 46 to check whether the rewritten address notified from another CPU is equal to the contents of the entry in copy 3 of the address array.

Therefore, as the number of connected CPUs increases, the hardware scale required for the address array copy 3 and the match detection circuit 46 increases, which poses a problem in reducing the size of the system.

(Object of the Invention) The present invention divides the main memory into a plurality of blocks, provides an indicator for each block to indicate whether the memory contents of that block are registered in the local memory of the CPU, and
The system is characterized by controlling whether or not to invalidate the stored contents of the local memory according to the state of the indicator when rewriting the memory from the local memory. The aim is to downsize the

(Structure and operation of the invention) FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

1 is a local memory, 2 is an address array, 5 is a flag register indicating for each block of the main memory whether the contents of that block are registered in the local memory 1, 4
1 is an address register that holds the access address, 4
2 is a data register that holds write information, 43 is a coincidence detection circuit that detects a match between the contents of address array 2 and the contents of address register 4J, 44 is a data register that holds read information from local memory 1, and 45 is another C
The address register 47 that holds the rewrite address sent from the PU is a check circuit that checks the state of the entry in the flag register 5 corresponding to the rewrite address sent from another CPU.

The flag register 5 stores main memory (for example, 16MB),
For example, the size of one entry in local memory 1 is 6.
4B) entries (256 bits), each entry 51.52. . . . are addresses 0, 64, . . . respectively. Corresponds to...

The content of the entry in the flag register 5 corresponding to the address registered in the local memory is tt 1 hp.

In the memory rewriting operation and memory reference from the CPU, when the access address and the contents of the address field of the corresponding entry in address array 2 are equal and the valid flag of that entry is 1'1'', the operation is conventional. is the same as

In memory reference, if the access address (A1) and the contents of the address field of entry 21 of address array 2 are different, or if the valid flag of entry 21 is "0", the access address (A1) is sent to the main memory. , reads information stored in main memory.

The information (Dl) read from the main memory is registered in the entry 11 of the local memory 1 specified by the specific 3 bits of the access address (A1), and is sent to each control unit via the data register 44. It will be done. In addition, the access address (A
1), the valid flag is set to "1", and the entry 53 of the flag register 5 corresponding to the access address (A1) is set to tt 1 rt.

Furthermore, address array 2 of access address (AI)
When registering to entry 21, check the contents previously stored in entry 21 and check if it is valid (valid flag is "
1'') address information (A4) is stored, the flag register 5 corresponding to that address (A4)
The entry 56 of is set to 0''.

When another CPU rewrites the memory and a rewrite address (A3) is notified from the other CPU, first the sent rewrite address (A3) is stored in the address register 45. Next, the check circuit 47 checks the rewrite address (
A3) Entry 55 of flag register 5 corresponding to L
Read the contents (1 bit).

If the read content is "1", the check circuit 47 sets the content of the entry 55 of the flag register 5 to "O", and the entry of the address array 2 specified by the specific 3 bits of the rewrite address (A3). Let the valid flag of No. 23 be gL O”.

In this way, in the present invention, based on the contents (1 bit) of the entry 55 of the flag register 5 specified by the rewrite address (A3) notified from another CPU, it is possible to determine whether the address is registered in the address array 2 or not. can be determined, the configuration of the check circuit 47 is simpler than that of the conventional coincidence detection circuit 46.

FIG. 2 is a diagram showing the configuration of another embodiment of the present invention.

The three CPUs a, b, and c each have a local memory 1, an address array 21, an address register 41 that holds access addresses, a data register 42 that holds write information, and the contents of address array 2 and address register 41. , a data register 44 that holds information read from the local memory 1, and an address register 45 that holds rewritten addresses by other CPUs. These operations are the same as the embodiment shown in FIG. 6 is a flag control unit, CP
Flag register 5 corresponding to U a, b, c
a, 5b, 5c, CPUa, b.

Circuits 47 a , 47 b , 47 that check the states of entries in the address register 48 that holds the address sent from C, and the flag registers 5 a, 5 b, and 5 c.
CPU c and the contents of the address register 48
, b, c gate circuit 49 a
, 49 b and 49 c.

In CPU a, a memory reference is made and the access address (A1) and the information read from the main memory (D
l) is registered in the address array 2 and local memory 1 of CPU a, the access address (A1
) and address information invalidated upon registration (A
4) is notified, and the flag control unit 6 sets the access address (A1) of the flag register 5a corresponding to CPUa.
) is set to "1", and
Entry 56 corresponding to the invalidated address (A4)
Let a be ((071. At this time, CPU b ,
The contents of flag registers 5b and 5c corresponding to c do not change.

When memory rewriting is performed in CPU a, the rewriting address (A3) is notified to the main memory, as well as to the flag control unit 6 and stored in the address register 48.

In the flag control unit 6, check circuits 47b and 47c corresponding to CPUs b and c check the rewrite address (
The contents (1 bit each) of entries 55b and 55c of flag registers 5b and 5c corresponding to A3) are read.

If the content read from entry 55b is "1", check circuit 47b reads entry 55 of flag register 5b.
The contents of address register b are set to 110'', and the contents of address register 48 [rewrite address (A3)] are notified to CPUb via circuit 1 to circuit 49b.CPU b, which has received the notification of rewrite address (A3), Address array 2 specified by specific bits of rewrite address (A3)
The valid flag of the entry is set to II O71.

If the content read from entry 55c is 0'', entry 55'c of flag register 5c is updated and CPUc
Contents of address register 48 to [Rewrite address (A
3))) will not be notified.

In this way, in the present invention, it is possible to determine which CPU's local memory holds the block information corresponding to the rewrite address notified from the CPU based on the entry contents (1 bit) of the flag register, and check The configurations of the circuits 47a, b, and c are simpler than the conventional coincidence detection circuit 46.

■ When memory is rewritten, the notification of the rewrite address between CPUs is sent from the flag control unit only to the CPU that has registered the information corresponding to the rewrite address in its local memory, so the inter-CPU erase interface signal line is reduced. , it is possible to prevent disturbance to a CPU whose local memory does not have information corresponding to the rewritten address.

(Effects of the Invention) As explained above, according to the present invention, the circuit (check circuit 47, inter-cpU iffinta face signal line) related to rewrite address notification between CPUs when memory is rewritten from the CPU can be easily configured. This makes it possible to reduce the hardware scale and downsize the system.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a diagram showing the configuration of another embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of a conventional information processing device. FIG. 2 is a diagram showing a control method of an address array in FIG. 1...Local memory, 2...Address array, 3...Copy of address array 2, 5 (5a,
5b, 5c) -Flag register, 6...Flag control unit, 41,'45.48...Address register, 42.4
4...Data register, 43.46...-Number construction circuit, 47 (47a, 47b, 47c)-Check circuit, 49
a, 49 b, 49 c-Goo1-circuit.

Claims (2)

[Claims] (1) In an information processing device that has multiple CPUs and each CPU has a local memory that holds a copy of the storage contents of the main memory, the main memory is divided into multiple blocks, and each block is An indicator is provided to indicate whether the memory contents of the CPU are held in the local memory of the CPU concerned, and when the CPU receives a memory rewriting address from another CPU, the state of the indicator indicates whether the contents of the local memory of the own CPU are retained. A local memory control method characterized by controlling whether or not registered contents are invalidated. (2) In an information processing device that has multiple CPUs and each CPU has a local memory that holds a copy of the storage contents of the main memory, the main memory is divided into multiple blocks, and each block is An indicator is provided to indicate which CPU's local memory holds the memory contents, and when any CPU rewrites the memory, the block corresponding to the rewrite address is set depending on the state of the indicator. CPU held in local memory
A local memory control method characterized in that the rewritten address is notified only to.