JPS63142906U

JPS63142906U -

Info

Publication number: JPS63142906U
Application number: JP3530887U
Authority: JP
Priority date: 1987-03-11
Filing date: 1987-03-11
Publication date: 1988-09-20

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示す回路図、第２
図は接合型ＦＥＴの特性図である。主な図番の説明、１０……プリドライバトラン
ジスタ、１８，１９……ドライバトランジスタ、
２１，２２……出力トランジスタ、２７……電圧
増幅段、２８……電力増幅段、２９……ＦＥＴ、
３０……ダイオード。 Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a characteristic diagram of a junction type FET. Explanation of main figure numbers, 10... pre-driver transistor, 18, 19... driver transistor,
21, 22... Output transistor, 27 ... Voltage amplification stage, 28 ... Power amplification stage, 29... FET,
30...Diode.

Claims

[Scope of utility model registration request]

A low frequency amplifier that drives a speaker by power amplifying a signal voltage amplified in a voltage amplification stage in a power amplification stage, the FET having a drain and source connected between the voltage amplification stage and the power amplification stage; A reverse current prevention diode is provided to prevent reverse current in the transistor of the complementary push-pull circuit that constitutes the first stage of the power amplification stage, and the constant current characteristic of the FET prevents the power amplification stage from flowing in the event of an abnormality. The diode prevents a reverse current from flowing between the base and emitter of the transistor of the push-pull circuit by limiting the inflowing current and increasing the voltage between the drain and source of the FET at the time of a large input signal. Characteristic current limiting circuit for low frequency amplifiers.