JPH02123147U - - Google Patents
Info
- Publication number
- JPH02123147U JPH02123147U JP3086989U JP3086989U JPH02123147U JP H02123147 U JPH02123147 U JP H02123147U JP 3086989 U JP3086989 U JP 3086989U JP 3086989 U JP3086989 U JP 3086989U JP H02123147 U JPH02123147 U JP H02123147U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- switching transistor
- turned
- resistor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第1図はこの考案の一実施例を示す接続図、第
2図は従来の回路を示す接続図。
1……第1の定電流回路、2……第2の定電流
回路、3……第3の定電流回路、4……増幅用ト
ランジスタ、5……接続点、6……負荷抵抗、7
……増幅器、8,9……ダーリントン回路、10
……出力点、12……スピーカ、13……第1の
スイツチングトランジスタ、14……抵抗、15
……キヤパシタ、16……抵抗、17……第2の
スイツチングトランジスタ、19……電圧点。な
お、図中同一符号は同一または相当部分を示す。
FIG. 1 is a connection diagram showing an embodiment of this invention, and FIG. 2 is a connection diagram showing a conventional circuit. DESCRIPTION OF SYMBOLS 1... First constant current circuit, 2... Second constant current circuit, 3... Third constant current circuit, 4... Amplifying transistor, 5... Connection point, 6... Load resistor, 7
...Amplifier, 8,9...Darlington circuit, 10
... Output point, 12 ... Speaker, 13 ... First switching transistor, 14 ... Resistor, 15
... Capacitor, 16 ... Resistor, 17 ... Second switching transistor, 19 ... Voltage point. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
接続されコレクタが第2の定電流回路2を介して
接地される増幅用トランジスタ4のベースに信号
を入力し、出力点10が第3の定電流回路3を介
して上記電源に接続され、該出力点と接地間とに
接続されるダーリントン回路の入力ベース端子を
上記増幅用トランジスタ4のコレクタ側の端子5
に接続し、上記端子5と10との間に負荷抵抗6
を接続し、上記ダーリントン回路の該出力点10
と接地との間にスピーカ回路を接続するよう構成
された半導体集積回路において、 コレクタが上記増幅用トランジスタ4のコレク
タ側端子5に接続され、エミツタが抵抗14を介
して接地される第1のスイツチングトランジスタ
13、 上記抵抗14に並列に接続されるキヤパシタ1
5と抵抗16を直列接続した外付回路、 コレクタが上記端子5とほぼ同一電位の電圧点
に接続されエミツタ側の端子が上記第1のスイツ
チングトランジスタ13のエミツタに接続される
第2のスイツチングトランジスタ17、 上記第1のスイツチングトランジスタ13がオ
ンの間は上記第2のトランジスタ17はオフとな
り、13がオフの間は17がオンとなるよう制御
する手段、 を備えたことを特徴とする半導体集積回路。[Claims for Utility Model Registration] A signal is input to the base of an amplifying transistor 4 whose emitter is connected to a power supply via a first constant current circuit 1 and whose collector is grounded via a second constant current circuit 2. , the output point 10 is connected to the power supply via the third constant current circuit 3, and the input base terminal of the Darlington circuit connected between the output point and the ground is connected to the terminal 5 on the collector side of the amplification transistor 4.
and a load resistor 6 between the terminals 5 and 10.
and connect the corresponding output point 10 of the above Darlington circuit.
In a semiconductor integrated circuit configured to connect a speaker circuit between the amplifying transistor 4 and the ground, a first switch whose collector is connected to the collector side terminal 5 of the amplifying transistor 4 and whose emitter is grounded via a resistor 14 is provided. a capacitor 1 connected in parallel to the resistor 14;
5 and a resistor 16 connected in series; a second switch whose collector is connected to a voltage point having almost the same potential as the terminal 5, and whose emitter side terminal is connected to the emitter of the first switching transistor 13; a switching transistor 17, means for controlling the second transistor 17 so that it is turned off while the first switching transistor 13 is turned on, and that the switching transistor 17 is turned on while the switching transistor 13 is turned off. semiconductor integrated circuits.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3086989U JPH071871Y2 (en) | 1989-03-20 | 1989-03-20 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3086989U JPH071871Y2 (en) | 1989-03-20 | 1989-03-20 | Semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02123147U true JPH02123147U (en) | 1990-10-09 |
JPH071871Y2 JPH071871Y2 (en) | 1995-01-18 |
Family
ID=31256304
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3086989U Expired - Fee Related JPH071871Y2 (en) | 1989-03-20 | 1989-03-20 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH071871Y2 (en) |
-
1989
- 1989-03-20 JP JP3086989U patent/JPH071871Y2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH071871Y2 (en) | 1995-01-18 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |