JPS5859214U - amplifier bias circuit - Google Patents
amplifier bias circuitInfo
- Publication number
- JPS5859214U JPS5859214U JP11722782U JP11722782U JPS5859214U JP S5859214 U JPS5859214 U JP S5859214U JP 11722782 U JP11722782 U JP 11722782U JP 11722782 U JP11722782 U JP 11722782U JP S5859214 U JPS5859214 U JP S5859214U
- Authority
- JP
- Japan
- Prior art keywords
- emitters
- transistors
- amplifier
- voltage
- bias circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の発端となった増幅器を示す回路図、第
２図は本考案の一実施例を示す回路図である。
１は入力端字、２は検波器、８．９は出力トランジスタ
、１８は負荷、２４．２５は差動増幅器である。FIG. 1 is a circuit diagram showing an amplifier that is the origin of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1 is an input terminal, 2 is a detector, 8.9 is an output transistor, 18 is a load, and 24.25 is a differential amplifier.
Claims (1)
導電型の異なる第１及び第２のトランジスタのエミッタ
を、それぞれ第１及び第２の抵抗器を介して負荷に接続
するＡ級又はＡＢ級プッシュプル増幅器において、入力
信号レベルに応じた直流信号を発生する手段と、上記第
１及び第２のトランジスタの両エミッタ間の電圧を差動
増幅する差動増幅器と、上記直流信号と上記差動増幅器
の出力との差分を増幅して上記第１及び第２のド ラ
ンジスタの両ベース間にベースバイアス電圧として印加
するバイアス手段とを有し、上記直流信号に応じて上記
第１及び第２のトランジスタの両エミッタ間電圧を制御
することを特徴とする増幅： 器のバイアス回路。A class A or class AB push type in which the emitters of first and second transistors of different conductivity types, whose collectors are connected to the positive and negative power supplies, respectively, are connected to the load via the first and second resistors, respectively. In the pull amplifier, means for generating a DC signal according to an input signal level, a differential amplifier for differentially amplifying the voltage between the emitters of the first and second transistors, and the DC signal and the differential amplifier. bias means for amplifying the difference between the output of the transistor and the output of the transistor and applying it as a base bias voltage between the bases of the first and second transistors; Amplification characterized by controlling the voltage between both emitters of: the bias circuit of the amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11722782U JPS605622Y2 (en) | 1982-07-30 | 1982-07-30 | amplifier bias circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11722782U JPS605622Y2 (en) | 1982-07-30 | 1982-07-30 | amplifier bias circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5859214U true JPS5859214U (en) | 1983-04-21 |
| JPS605622Y2 JPS605622Y2 (en) | 1985-02-21 |
Family
ID=29911417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11722782U Expired JPS605622Y2 (en) | 1982-07-30 | 1982-07-30 | amplifier bias circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS605622Y2 (en) |
-
1982
- 1982-07-30 JP JP11722782U patent/JPS605622Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS605622Y2 (en) | 1985-02-21 |
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