JPS58107609U - Amplifier muting circuit - Google Patents
Amplifier muting circuitInfo
- Publication number
- JPS58107609U JPS58107609U JP415482U JP415482U JPS58107609U JP S58107609 U JPS58107609 U JP S58107609U JP 415482 U JP415482 U JP 415482U JP 415482 U JP415482 U JP 415482U JP S58107609 U JPS58107609 U JP S58107609U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- differential amplifier
- input terminal
- amplifier
- muting circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は来者−の一実施例を示す回路図、第２図は本考
案の他の実施例を示す回路図である。
歯巾、３及び１１はコンデンサ；４．５．１２及び１０
は抵抗器、６．８及び２５はトランジス 夕、２８はミ
ューティング制御回路である。FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram showing another embodiment of the present invention. Tooth width, 3 and 11 are capacitors; 4.5.12 and 10
is a resistor, 6.8 and 25 are transistors, and 28 is a muting control circuit.
Claims (1)
スタのエミッタに電流源を接続した差動増幅器と、上記
差動増幅器の出力を増幅する後段増幅器と、上記差動増
幅器の第１の入力端子に第１のコンデンサを介して入力
信号を印加する手段と、上記第１の入力端子を第１の抵
抗器を介して接地する手段と、上記差動増幅器の第２の
入力端子に第セの抵抗器を介して負帰還信号を印加する
手段と、上記第２の入力端子を第３の抵抗器と第２のコ
ンデンサの直列回路で接地する手段とを有し、上記第１
と第２の抵抗器の抵抗値同志及び上記第１と第２のコジ
デンサの容量値同志をそれぞれ等しく設定すると共に上
記電流源を１ンオフ制御する様にしたことを特徴とする
増幅器のミューティング回路。a differential amplifier in which first and second transistors are differentially connected and a current source is connected to the emitter of the transistor; a post-stage amplifier that amplifies the output of the differential amplifier; and a first input terminal of the differential amplifier. means for applying an input signal to the differential amplifier via a first capacitor; means for grounding the first input terminal via a first resistor; means for applying a negative feedback signal via a resistor; and means for grounding the second input terminal with a series circuit of a third resistor and a second capacitor;
and the second resistor, and the capacitance values of the first and second cosidensors are respectively set to be equal, and the current source is controlled to be turned off. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP415482U JPS58107609U (en) | 1982-01-16 | 1982-01-16 | Amplifier muting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP415482U JPS58107609U (en) | 1982-01-16 | 1982-01-16 | Amplifier muting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58107609U true JPS58107609U (en) | 1983-07-22 |
Family
ID=30017030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP415482U Pending JPS58107609U (en) | 1982-01-16 | 1982-01-16 | Amplifier muting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58107609U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56162510A (en) * | 1980-05-20 | 1981-12-14 | Nec Corp | Amplifier |
-
1982
- 1982-01-16 JP JP415482U patent/JPS58107609U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56162510A (en) * | 1980-05-20 | 1981-12-14 | Nec Corp | Amplifier |
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