JPS63140485A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To speed up a serial access without increasing the action speed of a shift register by dividing plural bits constituting the shift register into plural groups, storing a selecting signal into one bit of respective groups and selecting simultaneously plural memory cells with it. CONSTITUTION:In a semiconductor memory device equipped with 2l pieces of memory cells, a start pointer 5 receives the leading address of a memory cell 1 to execute a serial access, sets two bits corresponding to the address designated among the bits of a shift register 4 to positions So and Sl apart from them by an acute angle bit the data in memory cells MC0 and MC1 selected by this are read to a data line pair and the data of the data line pair are written into the memory cells MC0 and MC1. When a shift pulse PHI is given to the shift register 4, the designated bit is shifted to the adjoining bit one by one respectively and a corresponding memory cell 1 is successively accessed two by two. Thus, without changing the action speed of the shift register 4, the cycle of the serial access can be doubled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device having a serial access function.

[Prior Art] FIG. 2 is a circuit diagram showing a conventional semiconductor memory device having a serial access function.

This semiconductor memory device includes a plurality of memory cells 1, and a pair of input/output lines 2, 2 of each memory cell 1 is connected to a data line pair I10. I
10. In addition, each memory cell 1 (MC
, -MCn) are connected to the gates of the transfer gate transistors 3, 3, respectively, with selection lines S Eo -S En connected to them.
This selection line 5Eo-SE is connected to each bit SO to So of the shift register 4. A start pointer 5 is connected to the shift register 4, and the start pointer 5 sets a signal of "0" or "1" in each bit 5o-5n of the shift register 4.

Next, the operation of this semiconductor memory device will be explained. When the start pointer 5 receives the first address of the memory cell 1 to be serially accessed, it sets the bit of the shift register 4 corresponding to that address to "1" and the other bits to "0".
Set to . Here, "1" is used as the selection signal for selecting memory cell 1. Subsequently, when serial access is started, bit S is set to "1".

The selection line SEO connected to becomes "1", and the data in the memory cell MCO selected by the selection line SE is transferred to the data line pair I via the transfer gate transistors 3, 3.
10. data line pair I10.
Data in I10 is written to memory cell MCO. Then, by the shift operation of the shift register 4, the "1" bit is sequentially shifted to the adjacent bit, and the "1" bit is sequentially shifted to the adjacent bit.
'' memory cells 1 corresponding to the bits are sequentially accessed.

[Problems to be Solved by the Invention] The conventional semiconductor memory device described above performs serial access to each memory cell by the shift operation of the shift register, so the speed of serial access depends on the operating speed of the shift register. In order to perform serial access at high speed, a high-speed shift register is required.

However, since there is a limit to the operating speed of the shift register, there is a limit to speeding up serial access.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that can speed up serial access without increasing the operating speed of a shift register.

[Means for Solving the Problems] The present invention includes a shift register consisting of a plurality of memory cells and a plurality of bits associated with the plurality of memory cells, and the shift register includes a plurality of bits selected in a predetermined bit of the shift register. A signal is stored, and memory cells are sequentially selected by sequentially moving the selection signal to adjacent bits by a shift operation of a shift register, and information is sequentially input to the selected memory cell via a data line. The semiconductor memory device that performs output is configured as follows.

That is, a plurality of bits constituting the shift register are divided into a plurality of groups, a selection signal is stored in one bit of each group, and a plurality of memory cells are thereby selected simultaneously.

[Operation] In the semiconductor memory device according to the present invention, selection signals are output from a plurality of bits of the shift register, so a plurality of memory cells are selected at the same time. Therefore, even if the operating speed of the shift register is the same, the information input/output cycle can be made faster.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the semiconductor memory device of the present invention. This semiconductor memory device is equipped with two memory cells 1, of which 0
th to Q, -1st memory cell M Co-M CL
The pair of input/output lines 2, 2 of -r are connected to the data line pair l10o, l10o via the transfer gate transistor 3.3, and the memory cells M
A pair of input/output lines 2, 2 of C, -MC2, and A are connected to data lines through transfer gate transistors 3, 3! 10. ．． I10
．． It is connected to the. In addition, each memory cell Mco -M
The selection lines 5Eo-SE and ρ-l are connected to the gate of the transfer gate transistor 3.3 of C2゜21, and the selection lines SE(1-SEzA-+ are connected to each pit S t of the shift register 4). )-5xt2-r.

A start pointer 5 is connected to the shift register 4, and the start pointer 5 sets each bit 5o-32σ-I of the shift register 4 to "0" or "0".
1" is set. In this embodiment, memory cell 1
"1" is used as a selection signal for selecting.

Next, the operation of this semiconductor memory device will be explained. When the start pointer 5 receives the first address of the memory cell 1 to be serially accessed, it sets two bits of the shift register 4 corresponding to the specified address to "1" and sets the other bits to "0". Set to . These two bits are, for example, the 0th bit So and the store number bit S.
It is set at a position separated by α bits, such as cL.

Subsequently, when serial access is started, the selection lines SEo, S connected to the bits So, S set to "1"
Et becomes "1", and data in memory cells MC and MCA selected by select lines SE and SE are transferred to data line pair l100. through transfer gate transistors 3.3. The data of data line pair l100, I/'Oo and Ilo, , Ilo, is read to memory cells M Co and MCl1. That is, α− from the 0th
One of the memory cells MCO-M Ce-t up to the first and 1. - one of the memory cells M CL to MC21L-/ is simultaneously selected, and each separate data line pair I10. ．． 10o
Data is input/output via Ilo, , I10+.

Then, when a shift pulse Φ is applied to the shift register 4, each "1" bit is shifted to the adjacent bit one by one, and the memory cells 1 corresponding to the "1" bits are sequentially accessed two by two. I'm going to go.

By time-divisioning the 2-bit data that is simultaneously input and output bit by bit as described above, the serial access cycle can be doubled without changing the operating speed of the shift register 4.

Note that in the above embodiment, a case is shown in which the multiple bits of the shift register are divided into two groups and one bit of each group is set to "1", but the multiple bits of the shift register are may be divided into three or more groups, one bit of each group may be set to "1", and a number of data line pairs corresponding to that number may be provided.

Further, in the above embodiment, the case where the memory cell 1 is directly accessed by the shift register 4 has been described, but the present invention can also be applied to the case where the sense amplifier in the dynamic RAM is accessed. The same effect as in the above embodiment can be obtained.

[Effects of the Invention] As described above, according to the present invention, a selection signal is output from a plurality of bits of a shift register for serial access,
Since multiple memory cells will be selected at the same time,
High-speed serial access is possible without increasing the operating speed of the shift register.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the main parts of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the main parts of a conventional semiconductor memory device. In the figure, 1 and M Co = M C2 (1-(
is a memory cell, 4 is a shift register, So -5zL-
+ is each bit of the shift register. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (4)

[Claims] (1) A shift register including a plurality of memory cells and a plurality of bits associated with the plurality of memory cells, a selection signal being stored in a predetermined bit of the shift register, and a shift register of the shift register. In the semiconductor memory device, the shift register sequentially selects memory cells by sequentially moving the selection signal to an adjacent bit by operation, and sequentially inputs and outputs information to and from the selected memory cells via a data line. A semiconductor memory device characterized in that a plurality of bits constituting the memory cell are divided into a plurality of groups, and a selection signal is stored in one bit of each group, whereby a plurality of memory cells are simultaneously selected. (2) A claim characterized in that a number of data lines corresponding to the plurality of groups are provided, and information is input and output to and from a plurality of simultaneously selected memory cells via separate data lines. 2. The semiconductor memory device according to item 1. (3) The semiconductor memory device according to claim 1 or 2, wherein the plurality of groups include the same number of bits. (4) The invention further comprises means for serially inputting and outputting information by time-sharing information that is simultaneously inputted and outputted via the separate data lines.
3. A semiconductor memory device according to any one of Items 3 to 3.