JPS6313578A - Multivaluing method - Google Patents

Abstract

PURPOSE:To obtain a high quality image even when respective types of the processing such as reducing, expanding, gamma transformation, and edge emphasizing with a high grade picture quality by mixing the output of a filter having plural different frequency characteristics. CONSTITUTION:Data 21 of a dither or a density pattern expressed by 0/1 are converted to 8-bit data by a multivaluing converting device 22, and after the data are processed by an image processing circuit 23, a converting circuit 24 executes the converting processing. An edge detecting device (a) of the image processing circuit 23 detects a character, a line drawing, the edge of an image, has a space frequency characteristic in which the network point of a network point image is not detected as an edge, an edge emphasizing device (b) outputs an original image or an edge emphasizing image signal to mix the original image and the edge by a certain ratio, and a smoothing device (c) smoothes the image. A mixer (d) changes a mixing ratio of an edge emphasizing image and a smoothing image and outputs it in accordance with the signal of the edge detecting device (a). The space filter of the edge detecting device (a), the edge emphasizing device (b) and the smoothing device (c) is made into the frequency characteristic to satisfy the special condition.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a preprocessing device for image conversion, and particularly to a multi-value conversion method for converting bit-compressed image data using a dither method, density pattern method, etc. into multi-value data. Regarding.

[Prior art]

Generally, devices that sample an image and output the digitized data from a digital printer such as a laser beam printer are becoming widespread due to the development of digital equipment. Such images are often extracted, and the image data is often bit-compressed using a dither method or a density pattern method due to storage capacity. When outputting an image using this method, there are major problems in the following points.

(1) When an image is enlarged, the dither or density pattern also becomes larger and the roughness becomes more noticeable.

(2) When the image is reduced, the dither or density pattern also becomes smaller, making it impossible for the printer to reproduce sufficient gradation.

(3) When trying to change the image density, dithered or density patterned data cannot be converted using an arbitrary comma curve.

(4) Processing such as edge enhancement cannot be performed.

Because of the above problems, when converting and outputting an image, the image quality usually deteriorates considerably.

〔the purpose〕

The present invention eliminates the above-mentioned problems and provides a multi-value conversion method that can obtain high-quality images even when various processes such as reduction/enlargement, γ conversion, and edge enhancement are performed. intended to provide.

〔Example〕

It is assumed that the binarized data of the image to be processed has been binarized using the dither method or the density pattern method. Binarization is performed by comparing threshold matrix data and image data. There are two types of threshold matrix shapes: a dot concentrated type and a dot dispersed type, but the dot concentrated type is usually used. In this method, binary data is converted into white/black binary data using pseudo halftone dots.

Therefore, the basic principle of this embodiment is to process the binarized data, convert it to the original multi-level signal, perform conversion such as scaling, and then binarize it again using the dither method or density pattern method. It is something to do.

FIG. 1(A) is a diagram of the principle of this embodiment, and the dither or density pattern data 21 expressed in 0/1 is transferred to the multi-value converter 22.
It is converted into 8-bit data of 0014/FF++. That is, O→00 r+, l→PI”,
It becomes H.

Here, H does not represent a hexadecimal number.

Thereafter, the image processing circuit 23 performs processing.

After processing in the processing circuit 23, the conversion circuit 24 performs scaling processing. The processing method of the processing circuit 23 will be explained below. Here, we will proceed with the case where the image data 21 has been binarized using the aforementioned dot concentration dither or density pattern method (.

At this time, the image data becomes a halftone image, which will be referred to as halftone image data from now on.

(Basic Configuration) FIGS. 1 to 6 The basic configuration of the image processing circuit 23 in FIG. 1(C) of this embodiment is shown in FIG. 1(B). This image processing circuit is composed of an edge detector a, an edge enhancer, a smoother C, and a mixer d. The edge detector a detects the edges of characters, line drawings, and images as described later, and the halftone dots of the halftone image are given a spatial frequency characteristic that does not detect them as edges. The edge enhancer outputs an original image or an edge-enhanced image signal obtained by mixing the original image and edges at a certain ratio. The smoother C smoothes the image. In mixer d,
Depending on the signal from the edge detector, the mixing ratio of the edge-enhanced image and the smoothed image is changed and output.

In this way, the halftone dots of the halftone image data are determined to be non-edge areas, and smoothing is performed.

The basic principle is to smooth the input image data, average and smooth the halftone image data, and convert it into multivalued data proportional to the density value, as described above. At this time, it is preferable that the smoothing area be as large as possible. However, since the resolution is lowered, the edge portions of the image are treated with the same signal or edge-enhanced signals, and the non-edge portions are smoothed to obtain multivalued data.

The frequency characteristics of such halftone image data have peaks at the fundamental frequency and its high frequencies, as shown in FIG. 2a.

The frequency characteristics of text images and continuous tone photographic images are as shown in Figure 2, c. For such mixed images of text, photographs, and halftone dots, the edge detector of this embodiment,
The spatial filters of the edge enhancer and smoother should have frequency characteristics that satisfy the following conditions.

Condition 1. The peak frequency of the spatial filter of the edge detector is set to be lower than the first harmonic frequency of the halftone image.

Condition 2. The peak frequency of the spatial filter of the edge enhancer is set to be higher than the peak frequency of the spatial filter of the edge detector.

Condition 3. The frequency characteristics of the spatial filter of the smoother are sufficiently reduced at the first harmonic frequency of the halftone image.

There are various types of spatial filters for edge detection, but if the matrix size, which affects the scale of the hardware circuit, is held constant, a first-order differential filter has a peak at a lower frequency than a second-order differential filter. However, the second-order differential filter does not have directionality, but the first-order differential filter does. It is necessary to take the sum of the absolute values of the slopes, or the maximum value of the absolute values of the slopes in at least two directions. Furthermore, the first-order differential is more resistant to point noise than the second-order differential. As described above, it is better to use a first-order differential filter as the spatial filter for the edge detector a.

Furthermore, as a spatial filter for an edge enhancer, a second-order differential filter, which has no directionality and has a peak at a higher frequency, is better than a first-order differential filter.

For simplicity, the relationship between the frequency characteristics of the various spatial filters as described above is calculated using one-dimensional fast Fourier transform (FFT). As an example, assume that the sampling interval of the input system is l/l 6 mm.

When the matrix size is 5 x 5, the one-dimensional FFT of the second-order differential filter (-1, 0, 2, O, -1) is shown in Figure 3, and the first-order differential filter (-1, 0, 0゜0, l) 1
The dimensional FFT is shown in Figure 4, and another one-dimensional differential filter (-
1, -1, 0, 1, 1) is shown in FIG.

The peak positions are 4 1/mm and 2 1/m, respectively.
m.

2.5 1/mm.

Comparing two types of first-order differential filters, the one with a larger pulse width (-1, -1, 0, l, l) is better. This is because the larger the pulse width, the smaller the intensity of the second peak, and the wider the pulse width, the wider the edge region (edge emphasis applied to this region) can be detected.

Edge detection is performed using a first-order differential filter (-1, -1, 0°1
, l) and the edge emphasis is set to a second-order differential filter (-1°0, 2.0.-1), the respective peak frequencies are 2.5 1/mm and 4 1/mm, satisfying condition 2. ing. In other words, edge detection is used to extract a wide area for edge enhancement, and edge enhancement uses a spatial filter that produces sharp edges.

Next, a 5×5 smoothing filter (1, l.

1, 1. The one-dimensional FF'F of l) is shown in FIG.

In this embodiment, by using spatial filters with frequency characteristics such as the above-mentioned lines 4111 to 3 in the edge detector, edge enhancer, and smoother, flat parts and halftone dot images are determined to be non-edge areas and smoothed. The edges of characters, line drawings, and images are determined to be edge areas, and the edges are emphasized. Further, the boundary between the edge region and the non-edge region is continuously connected by changing the mixing ratio in the mixer according to the signal from the edge detector. Through the above steps, multivalued data of halftone image data is obtained. Furthermore, since the matrix size of the spatial filter does not need to be large, the scale of the hardware circuit can be reduced, which is advantageous for LSI implementation.

FIG. 7 is a detailed blower diagram of the image processing circuit according to the embodiment of the present invention, where Sl is an input image signal, and ■ is a differential value detection section that detects the absolute value of the first differential value of the input image signal S1. Diagram a
corresponds to S2 is a differential signal connected to the output of the differential value detector l, 2 is a control signal generator that generates control signals S3 and 34 from the differential signal S2, S3 is the output of the control signal generator 2 and is a control signal, and S4 is also a control signal. The output of the signal generator 2 is a complementary control signal to the control signal S3, and 3 is the input image signal S.
1 corresponds to FIG. 1C. S
6 is a smoothed image signal smoothed by the smoothing processing unit 3; 4 is a multiplier for calculating the arithmetic product of the smoothed image signal S6 and the control signal S3; S7 is the output of the multiplier 4; is an edge enhancement unit that emphasizes the edge portion of the input image signal S1, S8 is an edge signal of the edge enhancement unit 5, S9 is a constant given from the outside, and 6 is an arithmetic product of the edge signal S8 and a constant 89. 7 is an adder which calculates the arithmetic sum of the edge signal SIO and the input image signal Sl; The adder 7 constitutes the edge emphasizing device shown in FIG.

Sll is an edge-enhanced image signal which is the output of the adder 7; 8 is a multiplier for calculating the arithmetic product of the edge-enhanced image signal Sll and the control signal S4; S12 is the output of the multiplier 8;
9 is an adder that takes the arithmetic sum of output S7 and output 812, S1
3 is the output of the adder 9 and is a processed image signal. Here, the multipliers 4 and 8 and the adder 9 constitute the mixer d in FIG.

Here, an edge emphasizing unit 302 corresponding to the edge emphasizing device l]
In this case, a multiplier 6 multiplies the output of the edge amount (edge detect) detection section 5 and the aforementioned control signal S9. It goes without saying that the multiplication unit 6 can be constructed from a ROM or the like, and the control signal S9 may be a coded signal instead of the multiplication coefficient itself.

When the pixel of interest in image processing is A, an adder 7 adds the pixel of interest and a value multiplied by a certain coefficient of edge detection, and edges of the pixel of interest are emphasized. Mixing section 305
In the following, the output of the edge enhancement unit 302 and the smoothing process 3
A circuit unit that mixes the outputs of
S3. S4 is output. 33. As described below. S4 is a complementary control signal, but is not necessarily limited thereto. S
3. The characteristics of S4 can be freely selected and set using the control signal S5. The output of the edge emphasis section is multiplied by S4 in the multiplier 8, the output of the smoothing processing section is multiplied by S3 in the multiplier 4, and the output of the multipliers 4 and 8 is multiplied by the output of the multiplier 8. are added together by the adder 9, and this becomes the image processing output.

The block diagram of FIG. 7 can also be expressed by the following equation.

First, the differential value detection unit l and the control signal generator 2 are expressed by the following formula l
Perform calculations such as.

11111) Here, 1 is the input image data, and E is the control signal S4.

5 is a normalization function that normalizes the control signal S4 to a maximum value of 1.

The following output is obtained from the adder 7.

G is the output of the adder 7, and kl is a constant of the constant signal S9. Then, the following output is obtained from the smoothing processing section 3.

H is the output of the smoothing processing section 3. Therefore, the value Out of the output S13 of the adder 9 can be expressed by the following equation 2.

The part in [ ] shown in the above equation is a kernel that performs convolution with the image signal I. Kernels *l to *4 can be modified in various ways, examples of which are shown in Table 2.

*1 Tree 2 Tree 3 *4 Table 2 FIG. 8 shows an example of the characteristics of the function f of the control signal generating section 2.

E=f (x) where E=Of or O< x < 0.2E=1
．． 67x −0,33for 0.2<x<0.8E
=l for 0.8<x<1. However, both input and output signals will be normalized to θ˜1 for explanation.

FIG. 9 and FIG. 1θ show the edge detection section l (
FIG. 2 is a diagram illustrating the operation of the differential value detection section (hereinafter referred to as a differential value detection section), and is shown in one-dimensional main scanning.

As already explained, the differential value detection unit 1 is a kind of band-pass filter, so that the input image signal S such as the halftone image data having high frequency components shown in FIG.
When l is convolved in the main scanning direction with a kernel (-1, -1, 0°l, 1), the output signal S2 becomes 0.

On the other hand, in the case of a relatively low-frequency input image signal (for example, a vertical line of a character), the output signal S2 takes a large value due to similar convolution as shown in FIG.

Here, the control signal generating section 2 that performs gamma conversion sets the control signal S3 to 1 and the control signal S4 to 0 when the differential signal S2 is smaller than 0.4, as shown in FIG. Also, if the differential signal S2 is larger than 1.6, the control signal S3 is set to 0,
Set the control signal S4 to 1. Furthermore, the differential signal S2 is 0.4
~1.6, the differential signal S is set so that the sum of the control signal S3 and the control signal S4 always becomes 1, as shown in FIG.
2.

On the other hand, the input image signal S1 is connected to the input of the differential value detection section 1, and is also connected to the inputs of the smoothing processing section 3 and the edge detection section 5 at the same time.

FIG. 11 shows the operation of the smoothing processing section 3.
For this purpose, a one-dimensional example in the main scanning direction is shown. In this case, the kernel is a low-pass filter (1,], I, l, l) whose contents are all 1 and configured to output the average of 5 pixels, and the input image signal Sl is a smoothed image signal. It will look like S6.

Further, FIG. 12 shows the operation of the edge emphasizing section 5, and also shows one dimension in the main scanning direction for the sake of explanation. The kernel is (-1, 0, 2, O, -1) and is good (it has the known edge detection characteristics of second-order differential, and the output S8 is 0 at the flat part and has positive and negative peaks at the edge part). Motsu.

Further, the edge signal S8 is multiplied by a constant 89 by a multiplier 6, and is added to the image input signal Sl by an adder 7, thereby producing an edge emphasis signal Sll. Although not shown, since the edge signal SIO is slightly delayed with respect to the input image signal Sl, a delay circuit is actually provided to adjust the timing between the edge signal SIO, which is input to the adder 70, and the input image signal Sl. .

By the way, at the edge portion where the output of the differential detection section l is large, that is, the control signal S3 is small and the control signal S4 is large. Conversely, when the differential signal S2 is small, S3 is large and S4 is small. Further, as described in FIG. 8, 83 and 84 are gamma-converted so that their sum always becomes 1.

Therefore, the sum of the outputs of the multipliers 4 and 8 is controlled so that when the differential signal S2 is large, the edge emphasis signal Sll has a large component, and when S2 is small, the smoothed signal S6 has a large component.

FIG. 13 shows this state, and shows that the differential signal S2 detects edges in a portion of the input image signal S1 excluding short-period vibrations (corresponding to the halftone dot period).

In the figure, the input image data S1 is the halftone image data part (
Suppose that it is made up of A) and line part (B).

A large amount of the first-order differential signal S2 occurs in the portion (11).

The control signal S4 is a gamma-converted version of the differential signal S2. S3 is 1-84. A smoothed signal s6 and an edge enhancement signal 811 are also shown. Therefore, the processed signal S13
As shown in the figure, the smoothed signal power is output in the halftone area (A), and the edge emphasis signal is output in the edge area (11) as multivalued data. However, the maximum value of the output signal here is standardized to 1, and in reality, for example, 8 bits 2
55 data (not a binary value of 0.1).

Next, each block in FIG. 7 will be explained in detail.

(Differential value detection unit l) FIG. 14 is a detailed circuit diagram of the differential value detection section 1.

The differential value detection section l has a 5-line buffer 301 shown in FIG.
The output of is input.

In the figure, 306 is a first-order differentiator, and its output 306
-a is a data section 306-c and a sign section 3 indicating positive/negative.
The sign section 306-b is input to the select signal of the selector 308, and the inverter 30
7, the absolute value of the data is 3 by selecting either the inverted data or the data of 306-c.
08-a is obtained. Similarly, the absolute value of the output of the first-order differentiator 312 is output from the selector 311, and the adder 30
9, 308-a and 311-a are added, and the sum of the first-order differential values in two directions is output from the adder 309.

Next, a block diagram showing details of the first-order differentiators 306 and 312 shown in FIG. 14 is shown in FIG. 15.

First, in order to explain the basic operation of this first-order differentiator circuit, block X in FIG. 15 will be explained.

First, all shift registers in FIG. 15 are shifted in synchronization with an image transfer lock not shown in the figure. To simplify the explanation, all multiplication coefficients of multipliers 243 to 247 are assumed to be 1. According to timing chart Figure 16, t
The output of the shift register 230 at -3 is Sn,m-
1+b The output of the shift register 231 is Sn, m+Sn, m-
3+Sn, m-2, and the output of the shift register 232 at t-1 is Sn, m+1+Sn, m+Sn, m-
1+Sn.

m-2, the output of adder 260 at to is Sn, m
+20Sn, m+, +Sn, m-1-8n, m-1-1
-8n, m-2.

In this way, the added value of 5 pixels in the main scanning direction is calculated for block
Calculate by. Here, by setting the multiplication coefficients of the multipliers 243 to 247 to a, b, c, rl, and e, the output of the adder 260 becomes e a Sn, m+
, +d-3n, m+, +c llSn, m+b ll
Sn, m-1+a*Sn, m-2.

It can also be seen that the circuits after the shift register 223 and the circuits after the shift register 233 operate in the same manner.

By the way, when the first-order differential to be sought is like *l and *2 in Equation 1, and the pixel of interest is on the 0912th day, the kernel elements of the n-2 line and the n-1 line are equal, and the n+1
The kernel elements of the line and n+2 line are also equal. Therefore, the image data is obtained by adding the (n-2)th line and (n-1)th line using the adder 231, and then using the formula 1*1. By performing first-order differential processing as shown in *2, the circuit scale can be reduced to 1/2. The same applies to the (n+1)th line and (n+2)th line. In this way, the adder 400 can obtain addition values corresponding to the kernels for five lines.

In addition, when the multipliers shown in 238 to 252 are as simple as for-1orO, they can be easily constructed with an inverter 291 and a selector 292 as shown in FIG. It can be switched 1 or -1 and set to 0 by CL.

Furthermore, in order to obtain the first derivative of the kernel *1 in Equation 1, the multiplication coefficients of the multipliers 238 to 242 are set to 1, and the multipliers 243 to 242 are set to 1.
The multiplication coefficient of 247 is O, and the multiplication coefficients of multipliers 248 to 252 are -1.

To find the first derivative of the kernel *2 in Equation 1, use multiplier 2
42.238. 239. 240. The multiplication coefficient of 241 is 1. l, O, -1, -1, and the multiplier 24
Multiplying coefficients from 3 to 247 as l, I, 0. -1.
−1, and the multiplication coefficients of the multipliers 248 to 252 are l,
Let 1, O, -1, -1.

In addition, the circuit configuration for calculating first-order differentials such as *l and *2 in Table 2 can be realized using Fig. 18, but since the operating principle is the same as Fig. 15, the method of giving coefficients to the multiplier is Omitted.

(Edge emphasis part 5) Next, FIG. 19 shows the edge emphasizing section 5.

As shown in FIG. 20, the input image signal Sl shown in FIG. 7 consists of data for 5 consecutive lines of image data, and the input image data input to the 5-line buffer 301 is stored in the 5-line buffer. Thereafter, five lines are output simultaneously, and in synchronization with an image transfer lock (not shown), the image data is output one pixel at a time in the main scanning direction.

Further, as shown in FIG. 21, the region of interest S in the image area is further enlarged and the pixel data of interest is Sn.

Consider the surrounding image data when m. 19th
The edge enhancement unit 5 shown in the figure has n out of the input image data S1.
Image data for three lines, the −2nd line, n, and n+2nd line, are input, and the pixels of interest for image processing are set as Sn and m.

In the figure, 201 to 211 are 1-bit shift registers. The image data Sl is shifted by shift registers 201 to 203, 204 to 208, and 209 to 211 in synchronization with an image transfer lock (not shown). this·
The timing chart is shown in FIG. 22. In FIG. 22, the output of the shift register at a certain timing T is shown enclosed in parentheses in FIG.

Adder 213 is shift register 203.204.208
．． 211 output data 5n-2, m, Sn, m-2, S
n, m+2, Sn+2. m is added, and the added data is multiplied by 11 in a multiplier 214. The pixel of interest Sn,m is output from the shift register 206, multiplied by 4 in the multiplier 212, and added in the adder 215.
An edge detect signal G-3ll as shown in Equation 2 and FIG. 7 is output.

In addition, since the kernel elements of the n-2th line and the n+2th line are the same, shift registers 209 to 211 are omitted and the n-
The outputs of the second line and the (n+2)th line may be added and then input to the shift register 201.

It is also clear that the edge emphasizing section 5 can be configured by using the circuit shown in FIG. 18 and inputting the value of kernel *4 to the multiplier.

(Smoothing Processing Unit 3) Next, details of the blocks of the situation processing unit 3 shown in FIG. 7 are shown in FIG. 23.

The image signals S1 each have 5 continuous signals in the sub-scanning direction of the image.
It consists of line data, and is processed by an adder 271 for sub-scanning 5
Pixel addition is performed. This data is input to shift register 272 for one bit delay. The output data of shift register 272 is input to adders 277-280. The adder 272 adds the output of the shift register 272 and the data of one pixel before it. The result of this addition is 2
After being latched in 74 shift registers, it is added to the next pixel in 278 adders. Similarly, from the addition 280 at time T2, as shown in FIG.
+SN, m+1-1-3N.

m + SN, m -, 10SN, m -2
is output (SN, j = sn-2, j + Sn-, , j
10Sn, j10n+1, j10n+2+D.

In this way, when the pixel of interest is Sn, m, the pixel sum shown by *3 in equation 2 is output from the adder 280 and the divider 28
Smoothed data is obtained by dividing the total prime number by 1. FIG. 26 shows a circuit that performs weighted smoothing as shown in FIG. 25. The operation timing etc. are the same as in Fig. 23, but in Fig. 26, each line is weighted by multipliers 351 to 355, and a multiplier 356 is also provided in each column.
By weighting by .about.360, smoothing as shown in FIG. 25 is performed.

This smoothing processing section adds all the added values in the image sub-scanning direction and then adds them in the image main scanning direction, so the circuit size can be reduced.

〔effect〕

The present invention is capable of converting binary image data into multi-value data as described above.

Therefore, various image processing (e.g. scaling, γ conversion).

(edge enhancement, etc.) can be performed in the same way as normal multivalued data.

In the present invention, the original signal may be used instead of the edge emphasis signal. Furthermore, although the explanation deals with binary data, it is also possible to expand the degree of multi-leveling from a low degree of 3-level (2-bit) or 4-level to about 8-bit. Furthermore, this is also possible in the case of a dot-dispersed type.

[Brief explanation of the drawing]

Figure 1 (A) is a principle diagram of an embodiment of the present invention, Figure 1 (B)
1(A) is a basic circuit diagram of the processing circuit 23, FIG. 2 is a frequency characteristic diagram of various images, and FIG. 3 is a basic circuit diagram of the processing circuit 23 shown in FIG. 4 and 5 are frequency characteristic diagrams of various differential filters, FIG. 6 is a frequency characteristic diagram of a smoothing filter, FIG. 7 is an image processing block diagram of this embodiment, and FIG. 8 is a control signal generation unit 2. FIG. 9 and FIG. 1O are diagrams showing an example of the operation of the differential value detection section l that performs first-order differentiation, FIG. 11 is a diagram showing an example of the operation of the smoothing processing section 3, and FIG. A diagram showing an example of the operation of the edge emphasizing section 5, FIG. 13 is a signal waveform diagram of the numbered part in FIG. 7,
Fig. 14 is a detailed circuit diagram of the edge detection section 1, and Fig. 15 is a detailed circuit diagram of the edge detection section 1.
Detailed block diagram of the order differentiator 306 and 312, Figure 16 is a timing chart showing the operation of the first order differentiator, Figure 17 is the absolute value circuit diagram, and Figure 18 is details of another example of the first order differentiator. 19 is a detailed block diagram of the edge detection section 5, FIG. 20 is a buffer circuit diagram, FIG. 21 is a diagram showing the image area, FIG. 22 is a diagram showing the operation of the edge detection section, and FIG. 23 is a block diagram. is a detailed block diagram of the smoothing processing unit 3, the second
4 is a diagram showing the operation of the smoothing processing section, FIG. 25 is a diagram showing a kernel for other smoothing processing, and FIG. 26 is a block diagram for performing the smoothing shown in FIG. 25.

Claims (1)

[Claims] (1) In a multi-value conversion method that inputs binary or multi-value image data with a small number of bits and converts it into multi-value data with a larger number of bits, the input data is placed in multiple parallel formats. A multilevel conversion method that passes through filters with different frequency characteristics and mixes their outputs.