JPS61157160A - Picture processing device - Google Patents

Abstract

PURPOSE:To reproduce a picture with a high quality and in a high definition by executing the folding up after input picture data corresponding to an equal kernel factor are added beforehand when the factor of the kernel to fold up is equal concerning two rows or above, in the facsimile equipment, etc. CONSTITUTION:When an attention picture element of the picture processing is A, a certain coefficient-fold value of an attention picture and an edge detection is added by an adder 7, and the attention picture element is emphasized by an edge. In a multiplier 4, an edge emphasizing part output executes the multiplying determined by an S4 and in a multiplier 4, a smoothing processing part output executes the multiplying determined by an S3, the output of multipliers 4 and 8 is mutually added by an adder 9, and this goes to be a picture processing output. When the attention picture element is (n)th line, the factor of the kernel of a (n-2) line and a (n+2) line is equal, and also, the factor of the kernel of a (n+1) line and a (n+2) line is equal. Therefore, picture data adds a (n-2)th line and a (n-1)th with the adder and thereafter, the primary differential processing is executed.

Description

[Detailed Description of the Invention] Technical Field> The present invention relates to a digital copying device that handles images as electrical signals;
The present invention relates to an image processing device such as a facsimile machine.

<Prior art> Generally, images are sampled using a COD sensor, etc.
Due to the development of digital equipment, so-called digital copying devices, which reproduce images by outputting digitized data from a digital printer such as a laser beam printer, are becoming widespread in place of conventional analog copying devices.

Since such digital copying devices reproduce halftone images,
Gradation reproduction is usually performed using a dither method or a density pattern method. However, this method has the following two major problems.

(1) If the original is a halftone image, a periodic striped pattern that is not present in the original appears in the copied image.

(2) If the original contains line drawings, characters, etc., the edges will be cut off by the dithering process and the image quality will deteriorate.

The phenomenon (1) is called the moiré phenomenon, and what causes it.

A) AI [Moiré caused by a single-point original and input sampling B) Moiré caused by a halftone original and a dither threshold matrix, etc. can be considered. The phenomenon of A) is the halftone dot frequency 1 O (= ding r) determined from the halftone dot pitch PO (mm) of the halftone original.
(PEL/mm) n times higher frequency nfo
(PEL/mm) and input sensor or pinch PS (m
Input sampling frequency fS (=
) (PEL/mm), a beat frequency of 1 Δf=Ifs-nfol (PEL/mm) is generated, which becomes moiré.

The phenomenon (B) generally occurs when the dither threshold is fattin
When the dots are arranged in a concentrated dot type such as G type, the output image also has a pseudo halftone dot structure, which causes a beat between the input halftone dot document and the moiré phenomenon. If the edge-back cycle pitch of the dither threshold is Pp (mm) on the recording paper, then the spatial frequency is fD = l/Po (PEL/mm).
As a beat frequency, Δf=Ifo-fol (PEL/mm) appears most prominently.

Of the two moiré phenomena mentioned above, the one that occurs most strongly is (B). In the phenomenon (A), this is generally n = 3 to 6, where n is n times higher than the halftone dot original, and the transfer function (MTF) of the optical system leading to the sensor drops considerably at that frequency. Therefore, the contrast of moire fringes is also low.

Moiré phenomena caused by such causes significantly degrade the quality of output images. For this reason, various countermeasures and studies have been carried out for a long time, such as the random dither method, which can remove moiré, but produces grainy graininess and deteriorates the image quality.

J, Opt, Soc, Am,, Vol, 66° Nol0
, 0ctober 1976 A proposed by Paul G. Roetling, shown in P985.
RIES compares the average value of the density before and after binarization and applies a feed bank to the threshold value so that it becomes equal to 1. However, this method requires complicated hardening and has a poor moiré removal effect. not enough.

On the other hand, the re-halftone method found in Takashima et al. Proceedings of the Institute of Imaging Electronics Engineers 83-3 P13'"Hatting of text φ photo mixed image" The dither pattern is used to create dots, so moiré is removed and there is less grainy noise.

However, the resolution cannot be avoided due to reverberation (or averaging with surrounding pixels).In other words, if you try to remove the moire, the resolution will decrease, and if you try to maintain the resolution, the moire will not be removed.Therefore, only the halftone image area can be removed. It is essential to extract it in advance and apply the method only to that part. For this reason, a so-called image area separation technique is required.

This image area separation technology is a highly accurate and fast method at the current level - a method particularly suited for implementation in hardware.
However, even if image area separation technology were to be obtained, such a method would average and smooth even the high frequency components within the image, making it difficult to realize the above method. do not have.

On the other hand, regarding the problem (2), the characters and line drawings on the document are fragmented by dithering, and the edge portions in particular are cut off, resulting in a decrease in print quality. This phenomenon is particularly noticeable when the dither pattern is of a concentrated dot type, such as the aforementioned fat ting type. .

Purpose> An object of the present invention is to eliminate the two drawbacks described above and to provide an image processing device that can reproduce images with high quality and high definition. That is, in the present invention, the moiré phenomenon that occurs in halftone originals is removed, characters and line drawings are prevented from being cut into pieces, and high-frequency components in image areas are prevented from deteriorating. It happened. Furthermore, this method can be realized with a simple circuit configuration and can be provided at low cost.

<Embodiment> (Basic Configuration) FIGS. 1 to 6 The basic configuration of the image processing apparatus of this embodiment is shown in FIG. This image processing device includes an edge detector a.

It consists of an edge enhancer, a smoother C, and a mixer d. Edge detector a uses characters and line drawings 1 as described below.
The edges of the image are detected, and the halftone dots of the halftone image have a spatial frequency characteristic that prevents them from being detected as edges. The edge enhancer outputs an original image or an edge-enhanced image signal obtained by mixing the original image and edges at a certain ratio. The smoother C smoothes the image, and the mixer d changes the mixing ratio of the edge-enhanced image and the smoothed image according to the signal from the edge detector and outputs the image. In this way, the halftone dots of the halftone dot image are determined to be non-edge areas, and smoothing is performed to average them and prevent moiré.

Furthermore, the edges of characters, line drawings, and images are determined to be edge areas, and the edges are emphasized to prevent halftone dotting of characters and reduction in sharpness of images. Furthermore, since the edge area and the non-edge area are continuously connected, no texture changes occur at the boundary.

Next, the principle of this embodiment will be explained from the perspective of frequency characteristics.

First of all, the number of screen lines for the halftone image of the original is usually 1 in black and white.
It ranges from 20 lines to 150 lines, and in color from 133 lines to 175 lines. Moiré is more likely to occur when the screen angle is 0.
This is when the temperature is about 45 degrees. In addition, the halftone dot pitch in the main scanning direction during line reading is maximum when the screen angle is 45 degrees, and the spatial frequency is low, and when it is 0 degrees, the minimum spatial frequency is high, and the spatial frequency is when the screen angle is 0 degrees and 45 degrees. The results obtained are as shown in Table 1.

Table 1 The frequency characteristics of such a halftone image have peaks at the fundamental frequency and its high frequencies, as shown in Figure 2a.
The frequency characteristics of continuous tone photographic images are shown in Figure 2, c.
become that way. An edge detector and an edge enhancer according to this embodiment are used for such mixed images of characters, photographs, and halftone dots.

The spatial filter of the smoother has a frequency characteristic that satisfies the following conditions.

Condition 1. The peak frequency of the spatial filter of the edge detector is set to be lower than the first harmonic frequency of the halftone image.

Condition 2. The peak frequency of the spatial filter of the edge enhancer is set to be higher than the peak frequency of the spatial filter of the edge detector.

Condition 3. The frequency characteristics of the spatial filter of the smoother are sufficiently reduced at the first harmonic frequency of the halftone image. Also, the frequency is sufficiently lowered to correspond to the output dither period.

There are various types of spatial filters for edge detection, but if the matrix size, which affects the scale of the hardware circuit, is held constant, a first-order differential filter has a peak at a lower frequency than a second-order differential filter. However, the second-order differential filter does not have directionality, but the first-order differential filter has directionality, and is expressed as the square root of the sum of the squares of the slopes in at least two directions, or as an approximate expression thereof, the absolute value of the slopes in at least two directions. It is necessary to take the sum of the values or the maximum value of the absolute values of the slopes in at least two directions. Furthermore, the first-order differential filter is better as a spatial filter for the edge detector a, as the first-order differential filter is more resistant to point noise than the second-order differential filter.

Furthermore, as a spatial filter for an edge enhancer, a second-order differential filter, which has no directionality and has a peak at a higher frequency, is better than a first-order differential filter.

To simplify the relationship between the frequency characteristics of various spatial filters, we show the results of calculations using one-dimensional fast Fourier transform (FFT).As an example, the reading sampling interval of the input system is 1/16 mm, and the output system is 1 6 dots
The calculation is performed using a 4×4 dither matrix in s/mm. The period of the dither pattern is 41/mm in terms of spatial frequency. Also, in reading with 1x16mm sampling, 81/
It can only detect frequencies up to mm.

When the matrix size is 5X5, the one-dimensional FFT of the second-order differential filter (-1, 0, 2, 0, -1) is shown in Figure 3, and the first-order differential filter (-1, 0, 0, O, l) 1
The dimensional FFT is shown in Figure 4, and another one-dimensional differential filter (-
A one-dimensional FFT of 1°-i, o, i, i) is shown in FIG.

The position of each peak is 41/mm.

2 1/mm, 2.5 1/mm. Comparing this with the spatial frequency of the halftone image in Table 1, the first-order differential filter satisfies the condition l for all degrees of line numbers in Table 1, but the second-order differential filter satisfies the spatial frequency of 120! , 133 line 4
Condition 1 cannot be satisfied at 5°, and halftone dots are detected as edges.

Comparing two types of first-order differential filters.

It is better to increase the pulse width (-1, -1, 0, 1°1). This is because increasing the pulse width reduces the intensity of the second peak, and increasing the pulse width decreases the intensity of the second peak.
This is because a wide range of can be detected. If you use a first-order differential filter (-1,-1,0,1,1) for edge detection and a second-order differential filter (-1,0°2.0.-1) for edge emphasis, each peak frequency is 2.5 17mm,
4 1/mm satisfies condition 2. In other words, by edge detection, we extract a wide area where edges are emphasized,
Edge enhancement uses a spatial filter that sharpens edges.

Next, apply a 5×5 smoothing filter (1°1, L
, l, 1) is shown in Figure 6.
Fundamental frequency of halftone image of 20 lines 45@ or more, 3.341
At 1/mm or more, the strength decreases. Also 4X4
When the pitch of the dither matrix is 41/mm, the strength is sufficiently small and satisfies condition 3.

In this example, by using spatial filters with frequency characteristics such as the above-mentioned conditions 1 to 3 for the edge detector, edge enhancer, and smoother, flat parts of the image and halftone dot images are determined to be non-edge areas and smoothed. The edges of characters, line drawings, and images are determined to be edge areas, and the edges are emphasized. Further, the boundary between the edge region and the non-edge region is continuously connected by changing the mixing ratio in the mixer according to the signal from the edge detector. The above prevents moiré in halftone images, prevents one character from becoming halftone and reducing the sharpness of the image,
No discontinuous texture change occurs between edge areas and non-edge areas. Furthermore, since the matrix size of the spatial filter does not need to be large, the scale of the hardware circuit can be reduced, which is advantageous for LSI implementation.

FIG. 7 is a block diagram showing an embodiment of the present invention, where Sl is an input image signal and 1 is a differential value detection unit that detects the absolute value of the first differential value of the input image signal S1, which corresponds to FIG. 1a. . S2
is a differential signal connected to the output of the differential value detector 1, 2 is a control signal generator that generates control signals S3 and 84 from the differential signal S2, S3 is the output of the control signal generator 2 and is a control signal, S4
1 is also an output of the control signal generator 2 and is a control signal complementary to the control signal S3, and 3 is a smoothing processing section for smoothing the input image signal S1, which corresponds to FIG. 1C. S6 is a smoothed image signal smoothed by the smoothing processing unit 3; 4 is a multiplier for calculating the arithmetic product of the smoothed image signal S6 and the control signal S3;
S7 is the output of the multiplier 4, 5 is an edge emphasis unit that emphasizes the edge portion of the input image signal Sl, S8 is the edge signal of the edge emphasis unit 5, S9 is a constant given from the outside, and 6 is the edge signal S8. The multiplier that takes the arithmetic product with the constant S9 is a calculator, SI
0 is the edge signal output from the calculator 6; 7 is an adder that takes the arithmetic sum of the edge signal SIO and the input image signal S1; The adder 7 constitutes the edge strong and W unit bt- shown in FIG.

Sll is an edge-enhanced image signal which is the output of the adder 7, and 8 is a multiplier for calculating the arithmetic product of the edge-enhanced image signal S11 and the control signal S4.

S12 is the output of the multiplier 8, 9 is the output S7 and the output S12
An adder S13 which takes the arithmetic sum of is the output of the adder 9 and is a processed image signal. Here, the multipliers 4 and 8 and the adder 9 constitute the mixer d in FIG.

In the edge enhancement section 302 corresponding to the edge enhancement device, the output of the edge amount (edge detect) detection section 5 is multiplied by the aforementioned control signal S9 in a multiplier 6. It goes without saying that the control signal S9 may be a coded signal instead of the multiplication coefficient itself.

When the pixel of interest in image processing is A, an adder 7 adds the pixel of interest and a value multiplied by a certain coefficient of edge detection, and edges of the pixel of interest are emphasized. Mixing section 305
In the following, the output of the edge enhancement unit 302 and the smoothing process 3
A circuit unit that mixes the outputs of
S3. S4 is output. As described later, S4 is a complementary control signal, but is not necessarily limited to S4.
3 and 54 can freely select and set their characteristics using the control signal S5. The output of the edge emphasis section is multiplied by S4 in the multiplier 8, the output of the smoothing processing section is multiplied by S3 in the multiplier 4, and the output of the multipliers 4 and 8 is multiplied by the output of the multiplier 8. are added together by the adder 9, and this becomes the image processing output.

The block diagram of FIG. 7 can also be expressed by the following equation.

First, the differential value detection section 1 and the control signal generator 2 are expressed by the following formula 1.
Perform calculations such as.

Here, E is the input image data and E is the control signal S4.

5 is a normalization function that normalizes the control signal S4 to a maximum value of 1.

The following output is obtained from the adder 7.

G is the output of the adder 7, and kl is a constant of the constant signal S9. Then, the following output is obtained from the smoothing processing section 3.

H is the output of the smoothing processing section 3. Depends on it.

The value Out of the output S13 of the adder 9 can be expressed by the following equation 2.

The part in [ ] shown in the above equation is a kernel that performs convolution with the image signal processing. Various modifications can be considered for kernels 1 to 4, examples of which are shown in Table 2.

Tree 1 Tree 2 Tree 3 Tree 4 Table 2 FIG. 8 shows an example of the characteristics of the function f of the control signal generating section 2. jE=J'(X
) in IE=Ofo
r O<x<0.2 E = 1.67 x -0,33 for 0.2<x<0.8 1E=
1 for 0.8<x<1. However, both input and output signals are standardized to O~1 4
and explain.

Figures 9 and 10 are diagrams for explaining the operation of the edge (detection unit l (hereinafter referred to as differential value detection unit)) based on first-order differentiation, and are shown in one-dimensional main scanning. Since the differential value detection unit l is a kind of band-pass filter as shown in FIG. 1, 0, 1, 1) in the main scanning direction, the output signal S
2 is a small value of 0.1-0.2.

On the other hand, in the case of a relatively low-frequency input image signal (for example, a vertical line of a character), a similar convolution as shown in FIG. 10 takes a larger value than the output signal S2.

Here, the control signal generating section 2 that performs gamma conversion sets the control signal S3 to 1 and sets the control signal S4 to 0 if the differential signal S2 is smaller than 0.2, as shown in FIG. Also, if the differential signal S2 is greater than 0.8 and is 1, the control signal S3 is set to 0,
Set the control signal S4 to HI1. Furthermore, the differential signal S2 is 0.2
As shown in FIG.
2.

On the other hand, the input image signal 9 S1 is connected to the input of the differential value detection section 1, and is also connected to the input of the smoothing processing section 3 and the edge detection section 5 at the same time.

FIG. 11 shows the operation of the smoothing processing section 3, and for explanation, a one-dimensional example in the main scanning direction is shown. In this case the kernel is (1, 1, 1.

L, l), the content is all l, and it is a low bass filter configured to output the average of 5 pixels,
The input image signal Sl becomes a smoothed image signal S6.

Further, FIG. 12 shows the operation of the edge emphasizing section 5, and also shows one dimension in the main scanning direction for the sake of explanation. The kernel is (-1, 0, 2° 0, -1) and has the well-known second-order differential edge detection characteristic, and the output S8 is 0 at the flat part and has positive and negative peaks at the edge part. .

Further, the edge signal S8 is multiplied by a constant 89 by a multiplier 6, and added to the image input signal 51 by an adder 7, thereby producing an edge emphasis signal Sll. Although not shown, since the edge signal S10 is slightly delayed with respect to the input image signal St, a delay circuit is actually provided to adjust the timing between the edge signal SIO, which is input to the adder 7, and the input image signal Sl. It will be done.

By the way, when the output of the differential value detection section l is large, that is, at the edge portion, the control signal S3 is small and the control signal S4 is large. Conversely, when the differential signal S2 is small, S3 is thick and 34 is small, and as described in FIG. 33 and 34 are gamma-converted so that their sum always becomes 1. Therefore, multipliers 4 and 8
The sum of the outputs of is the edge emphasis signal S when the differential signal S2 is large.
When the component of ll is large and S2 is small, control is performed so that the component of the smoothed signal S6 is large.

FIG. 13 shows this state, and shows that the differential signal S2 detects edges in a portion of the input image signal S1 excluding short-period vibrations (corresponding to the halftone dot period).

The control signal S4 is obtained by gamma-converting the differential signal S2, and all but the four peaks of the signal S2 shown in FIG. 13 are set to O. 33 is naturally 1-34. Furthermore, FIG. 13 also shows a smoothed signal S6 and an edge emphasis signal S11. In FIG. 13, the processed signal 513 changes S6 and Sll to S
This is a signal in which the halftone dots added at a ratio of 3 and S4 are smoothed and only the edge portions are emphasized.

Next, each block in FIG. 7 will be explained in detail.

(Wi minute value detection unit 1) FIG. 14 is a detailed circuit diagram of the differential value detection section 1.

The differential value detection section l has a 5-line buffer 301 shown in FIG.
The output of is input.

In the figure, 306 is a first-order differentiator, and its output 306
-a is a data section 306-c and a sign section 3 indicating positive/negative.
06-b.

The sign section 306-b is inputted to the select signal of the selector 308, and by selecting either the +/- inverted data by the inverter 307 or the data of 306-c, the absolute value of the data 30g-a is obtained. Similarly, the absolute value of the output of the first-order differentiator 312 is determined by the selector 31.
1, and the adder 309 outputs 308-a and 31
1-a is added, and the sum of the first-order differential values in two directions is added to adder 3.
Output from 09.

Next, a block diagram showing details of the first-order differentiators 306 and 312 shown in FIG. 14 is shown in FIG. 15.

First, in order to explain the basic operation of this first-order differential circuit, block X in FIG. 15 will be explained.

First, all shift registers in FIG. 15 are shifted in synchronization with an image transfer lock not shown in the figure. To simplify the explanation, all multiplication coefficients of multipliers 243 to 247 are assumed to be 1. According to timing chart Figure 16, t
The output of the shift register 230 at -3 is Sn,m-
1+Sn, m-2, and the output of the shift register 231 at t-2 is Sn.

m+sn, m-1+Sn, m-2, and the output of the shift register 232 at -1 is Sn.

m + 1 + S n , m, + S n , m
−1+S n , m −2 and the output of adder 260 at 10 is Sn.

m42+S n , m+1+S n , m+s n ,
m-1+Sn, m-2. In this way, the sum of five pixels in the main scanning direction is calculated in block X. here,
The multiplication coefficients of the multipliers 243 to 247 are a, b, c, d, e.
By setting eaSn, the output of adder 260 becomes eaSn
, m42+d*Sn, m41+c*Sn, , m+b*S
n, m-1+a*S n , m-2.

Similarly, cars in which the circuits after the shift register 223 and the circuits after the shift register 233 operate can be identified.

By the way, when the first-order differential to be sought is like the book 1 degree tree 2 of formula l, and the pixel of interest is the n-th line, the kernel elements of the n-2 line and the n-1 line are equal, and the kernel elements of the n-2 line and the n-1 line are equal, and The elements of the kernel of line n+2 are also equal. Therefore, the image data is sent to the adder 23 for the n-2nd line and the n-1st line.
Add by 1 and then add 1 formula to 1. By performing first-order differential processing like Tree 2, the circuit scale can be reduced to 1/2. Also, n
The same applies to the +1st line and the n+2nd line.

In this way, the adder 400 can obtain addition values corresponding to the kernels for five lines.

More specifically, in the conventional circuit configuration, the second
When performing first-order differentiation in Figure 8, an addition circuit for the (n-2)th line and an addition circuit for the (n-1)th line are provided separately. An adder circuit for lines and an adder circuit for one (n+2)th line are required.

This is an example of an adder circuit for a block or one line.

The first-order differentiator shown in FIG. 29 has a conventional circuit configuration. In this embodiment, by adopting a configuration as shown in FIG. 30, the number of blocks X is reduced to a circuit scale of about 315.

On the other hand, depending on the coefficient settings of the multiplier in block X, the circuit configuration shown in FIG.
For example, in order to obtain smoothing as shown in Equation 3, after adding 5 lines of data as shown in Figure 31, use only one block X and use a simple circuit configuration to obtain a smoothed output. be able to.

To obtain edge detection as shown in the fourth zero 3 and tree 3 in Table 2, the circuit shown in FIG. 29 can be used as is, but it can also be configured as shown in FIG. 32.

In addition, when the multipliers shown in 238 to 252 are as simple as for-1orO, they can be easily constructed with an inverter 291 and a selector 292 as shown in FIG. For-1 can be switched and set to O by CL.

In addition, to obtain the first derivative of the kernel tree l in Equation 1, the multiplication coefficients of the 1 multipliers 238 to 242 are set to 1, and the multipliers 243 to 2 are
The multiplication coefficient of 47 is set to 0, and the multiplication coefficients of multipliers 248 to 252 are set to -l.

To find the first derivative of kernel tree 2 in Equation 1, multiplier 2
The multiplication coefficient of 42,238,239,240°241 is 1
．． 1,0. -1. -1, and the multiplication coefficients of the multipliers 243 to 247 are set to 1°1.0. -1. -1, and the multiplier 248~
252 multiplication coefficient 1.1, 0. -1. -1.

Also, tree 1 in Table 2. The circuit configuration for calculating the first-order differential as shown in *2 can be realized as shown in FIG. 18, but since the operating principle is the same as in FIG. 15, the explanation of how to give coefficients to the multipliers will be omitted.

be.

As shown in FIG. 20, the input image signal Sl shown in FIG. 7 consists of data for 5 consecutive lines of image data, and the input image data input to the 5-line buffer 301 is stored in the 5-line buffer. Later, 5 lines are simultaneously output and 1. synchronized with the image transfer lock (not shown). Image data is output pixel by pixel in the main scanning direction.

Further, as shown in FIG. 21, the region of interest S in the image area is further enlarged to include pixel data of interest, line n-2 of the image data S1.

Image data for three lines of the (n+2)th line is input, and the pixels of interest for image processing are set as Sn and m.

In the figure, 201 to 211 are 1-bit shift registers. Image data SL is stored in shift registers 201 to 203,
204 to 208 and 209 to 211 are shifted in synchronization with an image transfer lock (not shown). This timing chart is shown in FIG. 22. In FIG. 22, the output of the shift register at a certain timing T is shown enclosed in parentheses in FIG.

Adder 213 is shift register 203, 204, 208
, 211 output data 5n-2, m, Sn, m-2, S
n, m+2, and Sn+2+m are added, and the added data is multiplied by 11 in the multiplier 214. The pixel of interest Sn,m is output from the shift register 206, multiplied by 4 in the multiplier 212, and added in the adder 215.
An edge detect signal G-Sll as shown in Equation 2 and FIG. 7 is output.

In addition, since the kernel elements of the n-2th line and the n+2th line are the same, shift registers 209 to 211 are omitted and the n-
After adding the outputs of the 2nd line and the n+2nd line, the output may be input to the shift register 201, or the value of the kernel tree 4 may be input to the multiplier using the circuit shown in FIG. It is also clear that it is possible to construct

(Smoothing Processing Unit 3) Next, details of the block of the smoothing processing unit 3 shown in FIG. 7 are shown in FIG. 23.

The image signals Sl are each continuous in the sub-scanning direction of the image.
It consists of line data, and is processed by an adder 271 for sub-scanning 5
Pixel addition is performed.

This data is delayed by 1 bit in the shift register 27.
2 is input. The output data of shift register 272 is input to adders 277-280. The adder 272 adds the output of the shift register 272 and the data of one pixel before it. The result of this addition is latched into the 274th shift register and then added to the next pixel by the 278th adder. Similarly, at time T2, the adder 280 outputs SN1m+2+SN1m+1+SN as shown in FIG.
, m+sN.

m-1+SN, m-2 are output (SNIJ=Sn-
2, j+5n-1, j+sn, j+Sn + i I
J ”S n + 21 J ) @Thus, when the pixel of interest is Sn, m, the pixel sum shown in Book 3 of Equation 2 is output from the adder 280 and divided by the total number of primes by the divider 281 to obtain smoothed data. is obtained. Also, the 25th
The second circuit performs weighted smoothing as shown in the figure.
This is Figure 6. The operation timing etc. are the same as in Fig. 23, but in Fig. 26, each line is weighted by multipliers 351 to 355, and each column is also weighted by multipliers 356 to 360, so that the same as in Fig. 25 is achieved. Perform smoothing like this.

This smoothing processing section adds all the added values in the image sub-scanning direction and then adds them in the image main scanning direction, so the circuit scale can be reduced.

(Other Embodiments) In this embodiment, the kernels of the differential value detection section, smoothing processing section, and edge enhancement section were set to 5×5, but depending on the number of lines aimed at removing moiré, it may be 3×3 or 5×5. ×5 or more may be required in some cases. Also, depending on the purpose, a differential value detection section,
The smoothing processing units do not need to use kernels of the same size, and furthermore, the kernels do not need to be square.

Further, in this embodiment, a set of 5-line buffers is provided and edge detection, smoothing, and edge enhancement are performed in parallel processing, but it is not necessarily necessary to perform them in parallel.

Further, in this embodiment, the smoothed signal S6 which is the output of the smoothing processing section 3 and the edge emphasis signal 9 which is the output of the adder 7 are
S11 is added at a rate according to the output of the gamma converter 2, but the input image signal S1 is added instead of the edge emphasis signal Sll.
In this case, although it is somewhat inferior to this embodiment for characters and line drawings, it has the advantage that the device can be greatly simplified and the same effect as this embodiment can be obtained in terms of suppressing moiré. be.

In addition, the edge detection section 5 and multiplication calculator 6 shown in FIG.
If the edge emphasizing unit constituted by the adder 7 and the edge emphasizing unit 5 is constructed so that the center of the kernel tree 4 of the edge emphasizing unit 5 can be varied by a constant 59, the multiplier 6 and the adder 7 are not necessary.

Further, in this embodiment, the constant 59 is variable from the outside, but it may be fixed internally.

Furthermore, in the embodiment of the present invention, the characteristics of the control signal generator 2 that performs gamma conversion have been described as shown in FIG. 8, but FIGS. 27-a-C show modified examples of the characteristics of the gamma converter 2. show.

In FIG. 27, only the characteristics of the control signal S4 are shown, but the control signal S3 is made to be 53=1-S4.

Figure 27-a is 54 = 0 where O<S2<0.5S 4 = 1
．． However, it has a characteristic of 0.5 < 52 < 1.0, and is particularly characterized in that the circuit of the gamma conversion section can be easily constructed.

Figure 27 - S4 = -arct an (k @ S2+k)
In particular, the connection between the smoothed signal and the edge emphasis signal is smooth.

Figure 27-C is 54=0 where 0 <S2<0.25S
4 = 0.33 but 0.25 < 52 <
0.534 = 0.67 However, 0.5 <
S2<0.75S4=1.0 However, 0.
75<92<1.0, the circuit is relatively simpler than the embodiment shown in FIG. 8, and the circuit shown in FIG.
A characteristic of this embodiment is that the connection between the smoothed signal and the edge-enhanced signal becomes smoother than when the characteristics of the gamma conversion section shown in a are used.

More specifically, for example, Prewitt's edge detection or Sobel's edge detection method, which is well known as a differential value detection section, may be used.

Furthermore, the Laplacian may be used as the edge detection section, and the Prewitt edge detection method, the Sobel edge detection method, or the Laplacian is usually
Spatial filter processing is performed using a x3 kernel, but the essence of the present invention will not be affected even if the kernel size is expanded to a size other than 3x3.

Effects> As described above, according to the present invention, when the kernels that perform convolution have the same elements in two or more lines, the input data corresponding to the elements of the equal kernels are added in advance and then the convolution is performed. It is possible to reduce the number of product-sum operation circuits for convolution, and the circuit scale can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic concept of an embodiment of the present invention, FIG. 2 is a frequency characteristic diagram of various images, and FIG. 3 is a diagram showing the basic concept of an embodiment of the present invention. 4 and 5 are frequency characteristic diagrams of various differential filters, FIG. 6 is a frequency characteristic diagram of a smoothing filter, FIG. 7 is an image processing block diagram of this embodiment, and FIG. 8 is a control signal generation unit 2. FIGS. 9 and 10 are diagrams showing an example of the operation of the differential value detection unit l that performs first-order differentiation, FIG. 11 is a diagram showing an example of the operation of the smoothing processing unit 3, and FIG. A diagram showing an example of the operation of the edge emphasizing section 5, FIG. 13 is a signal waveform diagram of the numbered part in FIG. 7,
Fig. 14 is a detailed circuit diagram of the edge detection section 1, and Fig. 15 is a detailed circuit diagram of the edge detection section 1.
Detailed block diagram of the first-order differentiator 306°312, FIG. 16 is a timing chart showing the operation of the first-order differentiator, FIG. 17 is an absolute value circuit diagram, and FIG. 18 is details of another example of the first-order differentiator. 19 is a detailed block diagram of the edge detection section 5, FIG. 20 is a buffer circuit diagram, FIG. 21 is a diagram showing an image area, and FIG. 22 is a diagram showing the operation of the edge detection section. FIG. 23 is a detailed block diagram of the smoothing processing section 3. Fig. 24 is a diagram showing the operation of the smoothing processing section, Fig. 25 is a diagram showing the kernel for other smoothing processing, and Fig. 26 is a diagram showing the operation of the smoothing processing section.
Block diagram for smoothing in Figure 5, Figure 27<a),
(b) and (c) are diagrams showing other gamma conversion characteristics of the control signal generation section 2, Figure 28 is a diagram showing a first-order differential kernel, Figure 29 is a conventional convolution circuit diagram, and Figures 30-30. FIG. 32 is a convolution circuit diagram of this embodiment. In the figure, a is an edge detector, b is an edge enhancer, C is a smoother, and d
is a mixer, l is a differential value detection section, 2 is a control signal generation section, 3
4, 6 and 8 are multipliers, 5 is an edge detection unit, and 7 and 9 are adders, respectively.

Claims (1)

[Claims] In an image processing device that obtains output image data of a pixel of interest by performing convolution on two-dimensional input image data, when the kernel that performs the convolution has equal elements for two or more lines, the elements of the equal kernel An image processing device characterized in that it performs convolution after adding input image data corresponding to in advance.