JPS63135016A - Trigger signal generator - Google Patents

Abstract

PURPOSE:To maximize the data processing time after trigger signal output by retarding a reference clock inputted to a gate circuit for a glitch period of an output of a passive element being other input to the gate circuit so as to output the trigger signal not including the glitch. CONSTITUTION:A ROM address signal 2 is supplied from an address generating counter 6 and a change point retarded by a delay of the element from the leading of a reference clock signal 1 is provided. A ROM 7 is mapped so as to output an 'H' level with a specific address given and then an output signal 3 of the ROM is obtained. Then the said ROM output signal 3 is inputted to the other input terminal of the gate circuit 8 to output a trigger signal 5. The glitch period of the ROM output signal 3 and the 'H' period of the delay reference clock signal 4 are not overlapped and the trigger signal 5 includes no glitch, a latch circuit 11 latches a data 12 in a specific timing and the time from the leading of the trigger signal 5 till the leading of a reference clock 1 just after is maximized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a trigger signal generator that generates a trigger signal based on a reference clock signal.

[Prior Art] Generally, when a trigger signal generator in a digital circuit latches data using a trigger signal at a specific timing, the trigger signal is inputted with an address that changes with a reference clock signal. This often occurs when activated by the ROM output and the above clock. FIGS. 2 and 3 show conventional examples of the above trigger signal generator. Second
In figure (a), (1) is the reference clock signal, (2) is the ROM address signal, (3) is the ROM output signal, and (5)
is the trigger signal, (6) is the address generation counter, (7
) is a ROM, (8) is a gate circuit, (1o) is a trigger signal generator, (11) is a latch circuit, (12) is data, and (b) is a timing diagram thereof.

In FIG. 3(a), (1) is a reference clock signal, (2) is a ROM address signal, (3) is a ROM output signal, (3a) is an inverted clock signal, (5) is a trigger signal, and (6) is a ROM output signal. ) is the address generation counter, (7) is the ROM
, (8) is the gate circuit, (9) is the inverter, (lO
) is a trigger signal generator, (11) is a latch circuit, (12) is a latch circuit, and (12) is a latch circuit.
) data, and FIG. 6(b) is its timing diagram. Note that the same reference numerals in the figures indicate the same parts.

Next, the operation of each of the above conventional devices will be explained.

In FIG. 2(a), a trigger signal (5) generated from a trigger signal generator (10) causes data (12) to be latched by a latch circuit (11) at the rising edge of the trigger signal (5). The ROJ address signal (2) input to the ROM (7) is supplied from the address generation counter (6). FIG. 2(b) shows how the ROM address signal (2) changes. The reason why the change point of the ROM address signal (2) lags behind the rising phase of the reference clock signal (1) is due to element delay.

Here, ROM (7) has “H” at a specific address.
Suppose you want to map it so that it outputs .

The ROM output signal (3) has the waveform shown in FIG. 2(b). The ROM output signal (3) generates a glitch immediately after the change point of the ROM address signal (2) due to the delay of the address decoder inside the ROM (7). The ROM output signal (3) containing this glitch is input to the gate circuit (8) together with the reference clock signal (1), and the ROM (
A trigger signal (5) is generated to be output at a specific timing determined by 7), and is input to a trigger terminal of a latch circuit (11) to latch data (12).

However, the trigger signal includes a glitch because it overlaps the glitch period of the ROM output signal (3) and the "H"'' period of the reference clock signal (1).

As another conventional example, FIG. 3(a) shows a reference clock signal (1) input to a gate circuit (8) inverted by an inverter (9). The timing is shown in the figure (b). Here, the "H" period of the inverted clock signal (4) which is the output of the inverter (13) is the ROM output signal (3).
The output trigger signal (5) does not include glitches because it does not overlap with the glitch period of time until)
is a half period of the reference clock signal (1).

[Problems to be Solved by the Invention] Since the conventional trigger signal generator is configured as described above, the output trigger signal may include glitches, which may cause malfunction in the circuit on which the trigger signal acts. There are two problems: (see FIG. 2), and a problem that the data processing time after outputting the trigger signal becomes short (see FIG. 3).

This invention was made in order to solve the above problems, and provides a trigger signal generator that can generate a trigger signal that does not include glitches and can maximize the data processing time after outputting the trigger signal. The purpose is to obtain.

[Means for Solving the Problems] A trigger signal generator according to the present invention receives a reference clock signal as input, performs a plurality of processes with different operating times in a passive element based on the reference clock signal, and The reference clock signal is delayed by a delay circuit connected in parallel, and each AND condition of the delayed reference clock signal outputted from the delay circuit and the output signal of the passive element is determined by a gate circuit, and the signal is This is the configuration to create.

[Operation] The trigger signal generator of the present invention generates a glitch-free trigger signal by delaying the reference clock input to the gate circuit by the glitch period of the output of the passive element that is the other input to the gate circuit. 6. [Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1(a) and 1(b). In FIG. 1(a), (1) is a reference clock signal that is a reference for trigger signal generation, (2) h is a ROM address signal output based on the reference clock signal (1), and (3) is the ROM address. ROM output signal of the content stored at the address specified by signal (2),
(4) is a delayed reference clock signal obtained by delaying the reference clock signal (1) by a predetermined time, (5) is a trigger signal finally obtained, and (6) is a delayed reference clock signal obtained by delaying the reference clock signal (1) by a predetermined time. (7) is a ROM that permanently stores predetermined data; (8)
is a gate circuit that takes the AND condition of input signals and outputs it, (
9) is a delay circuit that delays the reference clock signal (1) by the glitch period caused by the processing delay of the ROM (7), and (10) is the address generation counter (8).
, ROM (7), gate circuit (8) and delay circuit (
A trigger signal generator (11) is formed in (9) and generates a trigger signal, and (11) generates data (1) based on the trigger signal (5).
2), (12) is the data to be held, and FIG. 6(b) is a timing diagram thereof.

Next, trigger signal generation and
The operation of the device will be explained. In FIG. 1(a), the trigger signal from the trigger signal generator (10) is the data (12
) as an example. ROM input to ROM (7) in the same way as described in the explanation of the operation of the conventional technology
The address signal (2) is supplied from an address generation counter (6), and the ROM address signal (2) has a change point that lags the rise of the reference clock signal (1) by an amount of element delay. The ROM (7) is mapped to output “Ho” at a specific address, and the first
The above RO obtains the ROM output signal (3) shown in Figure (b).
The M output signal (3) generates a glitch immediately after the change point of the ROM address signal °(2). A delay circuit 9) delays the reference clock signal (1) and inputs the delayed reference clock signal (4) to one input terminal of the gate circuit (8). The delay provided by the delay circuit (9) is at least
The glitch period characteristic of the output signal (3) is assumed. Now, the ROM output signal (3) is input to the other input terminal of the gate circuit (8), and a trigger signal (5) is output. R
Since the glitch period of the OM output signal (3) and the "H" period of the delayed reference clock signal (4) do not overlap, and the trigger signal (5) does not include a glitch, the latch circuit (11) is unable to output the data (12). is latched at a specific timing, and the data processing time after latching (trigger signal (5
) from the rising edge of the reference clock (1) to the rising edge of the reference clock (1) immediately thereafter) is maximum.

Note that in the above embodiment, the reference clock signal (1)
Although the passive element that operates based on the above is formed using a ROM (?), any other element that causes a delay in operation time, such as a semiconductor element or a capacitor, may be used.

[Effects of the Invention] As described above, according to the present invention, a reference clock signal is input, and based on this reference clock signal, a plurality of processes having different operating times are performed by a passive element, which is connected in parallel to the passive element. The reference clock signal is delayed in the delay circuit, and the trigger signal is created by determining the AND conditions of the delayed reference clock signal output from the delay circuit and the output signal of the passive element in the gate circuit. , the effect is that a signal can be generated without glitches caused by passive elements. This prevents malfunctions from occurring in the circuits that act on it. Another advantage is that the processing time after the trigger signal is output can be maximized.

[Brief explanation of the drawing]

FIG. 1(a) is a configuration diagram of a trigger signal generator according to an embodiment of the present invention, FIG. 1(b) is a timing diagram in the embodiment of FIG. )as well as. FIGS. 3(a) and 3(b) are a configuration diagram and a timing diagram of a conventional example of a trigger signal generator. In the figure, (6) is the address generation counter, (7) is the ROM, (8) is the gate circuit, and (9) is the address generation counter.
is a delay circuit, and (10) is a trigger signal generator. In each figure, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 (a) (b) Figure 2 (a) (b) Figure 3 (a) (b) Procedural amendment (voluntary) Showa year, month, day 2, title of invention Force signal generator 3, relationship with the amended person case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 1 Agent address Detailed description of the invention in the specification of No. 2-2-3 Marunouchi, Chiyoda-ku, Tokyo. 6. Contents of the amendment (1) “(9) is an inverter” on page 3, line 7 of the specification
The statement "r (13) is an inverter" is corrected. (2) The statement "'H' period is an overlap" on page 4, line 14 of the specification is corrected to "'H' period overlap." (3) The description “inverter (9)” on page 4, line 17 to line 18 of the specification is amended to read “inverter (13) J.”

Claims (4)

[Claims] (1) A passive element to which a reference clock signal is input and performs multiple processes with different operating times based on the reference clock signal, a delay circuit connected in parallel to the passive element to delay the reference clock signal, and the delay circuit. 1. A trigger signal generator comprising: a gate circuit that generates a trigger signal by determining an AND condition of a delayed reference clock signal output from the circuit and an output signal of a passive element. (2) The trigger signal generator according to claim 1, wherein the passive element is formed of a semiconductor fixed memory device. (3) Trigger signal generation according to claim 1 or 2, wherein the passive element is configured such that the input reference clock signal is input as a value integrated by an integration circuit. vessel. (4) The trigger signal generator according to any of claims 1 to 3, wherein the delay circuit is configured to delay at least a glitch period occurring in a passive element.