JPS63133195A - Liquid crystal driving system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a liquid crystal driving method in a multiplex driving liquid crystal display device.

[Prior art and its problems] Conventionally, in a liquid crystal television receiver, when driving a liquid crystal display panel in a multiplex manner, two common sides are simultaneously selected for data on the segment side.
Efforts have been made to lower the duty ratio and increase contrast.

Then, using the above method, 3 lines are added to one common line.
FIG. 7 shows an arrangement in which image data for lines is displayed and the number of lines to be scanned is effectively thinned out to 2/3. Each common electrode is driven with a time width of 3H (IH is one horizontal period) and displays three lines of image data. The common electrodes are sequentially shifted and driven while alternately overlapping each other by time widths of 1H and 2H. With the above driving method, the number of scanning lines can be thinned out to 2/3. This 2/3 thinning operation can be easily understood from the fact that the common side shift clock CK is thinned out to 2/3.

The method described above is suitable for thinning out scanning lines to 2/3, but if extended as is, when performing 3/4 thinning processing, it will reduce the number of scan lines to one common line as shown in Figure 8. Since four lines of data are displayed and three common lines are selected at the same time, the vertical resolution is significantly degraded.

Similarly, it can be inferred that the scanning line cannot be naturally expanded for arbitrary thinning, such as 8/9.

In addition, conventionally, in the multiplex type liquid crystal driving system, as shown in Fig. 9(a) to (C), the vertical resolution UN is set to 262.5 lines, and the common side scan is applied to the entire one field. If you set the vertical resolution M to] 92 lines and perform common side scanning for the entire field, ■) Finish common side scanning halfway through the field, and after that, the common side voltage Vcom and segment Side voltage Vse
Continue to make g equal.

There are cases where this happens. In this case, when the vertical period is T, the drive signal width of each common electrode is T/N for ■, and T/M for ■.

For the second case below, the effective value V is given as the bias ratio a.
Calculating on, Voff, and operating margin P yields the following.

, °, when a = -rFr +1, P■ takes the maximum value.

(17N duty), ", when a = JT; r + 1, P■ takes the maximum value.

(1/M duty), °, When a = J'KI +1, P■ takes the maximum value.

(1/M duty) Conventionally, in the case of a vertical resolution of 192 lines, if the design cannot be designed to have the optimum duty as shown in FIG. 9(b), rVcom=Vs as shown in FIG. 9(c).
Efforts have been made to lower the actual duty ratio by providing an e gJ state, that is, an O bias state during a period including vertical synchronization.

This has been achieved by keeping the data of the common side driver always at "0" and the data of the segment side driver also always at "0".

However, due to the structure of the driver, this method can only be implemented when all the data of the common side driver has been shifted, that is, within a continuous period including the vertical synchronization interval. Therefore, when thinning out scanning lines,
It was not possible to prevent the duty ratio from increasing by using the 0 bias period for that line.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and provides a liquid crystal driving method that can display thinned images on a liquid crystal screen without increasing the duty ratio or reducing the contrast. The purpose is to

[Summary of the Invention] The present invention makes it possible to set the 0 bias state for each common line at any timing, so that a thinned-out image of scanning lines can be displayed on a liquid crystal screen without reducing the duty ratio. This is what I did.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall schematic configuration. In FIG. 1, reference numeral 11 denotes a liquid crystal driving voltage generation circuit, which generates liquid crystal driving voltages from vO to V4 and Vl.

V2. V3 is supplied to the segment driver 12, and VO
, V2. V4 is supplied to the common driver 13. "Two-layer liquid crystal drive voltage VO~■4 is VO, centering on V2,
Vl is positive, V3. V4 is set on the negative side with a certain voltage difference between them. The above segment driver 12
and the common driver 13 will be described in detail later.

In addition, the segment driver I2 is supplied with zero control signals EC,
A common inversion signal CKF and a control signal SP are inputted to the common driver 13, and a two-layer control signal EC and a common inversion signal CKF are inputted from the controller 14 to the common driver 13, and a control signal CP is also inputted thereto. Ru. 1. The common inversion signal CKF is a signal that is inverted in synchronization with the common shift clock and selects the common drive voltage of VO or (4). The zero bias control signal EC is set according to the number of scan lines to be thinned out, and is normally at a "1" signal level, but is set at a "0" signal level every preset horizontal period. becomes. Further, 15 is an A/D conversion circuit that converts the video signal sent from the video amplification circuit (not shown) into, for example, 4
It is converted into bit digital data and output to the segment driver 12. This segment driver 12 outputs a segment drive signal according to the video data sent from the A/D conversion circuit 15, and outputs a segment drive signal to the liquid crystal display panel 16.
drive the segment electrodes for display.

On the other hand, the common driver 13 is equipped with a shift register for generating a scanning signal, and the common driver 13 is equipped with a shift register for generating a scanning signal.
The common data sent from the shift register is shifted in synchronization with the common shift clock, and the common electrodes of the liquid crystal display panel 16 are sequentially driven in accordance with the data shifted in the shift register.

Thus, the segment driver 12 is configured as shown in FIG. FIG. 2 shows the main parts of the one-segment drive system of the segment driver 12. The segment driver 12 receives liquid crystal drive voltages Vl, V2 . V3
The liquid crystal drive voltage V1 is output to the output line 21 via the gate circuit G1, and the liquid crystal drive voltage V2 is output to the output line 21 via the gate circuit G2, and the liquid crystal drive voltage V2 is output to the output line 21 via the gate circuit G3. It is output to the output line 22. Further, the liquid crystal drive voltage V3 is outputted to the output line 22 via the gate circuit G4. The zero bias control signal EC applied from the controller 14 is level-shifted by the level shifter 23, and then is level-shifted by the gate circuit G1. , G4 as a gate signal, and is further supplied to the gate circuit G2 via the inverter 24.
．． It is supplied to G3 as a gate signal. Then, the voltage taken out from the output line 21 or the liquid crystal driving voltage V]'
Also, the voltage taken out from the output line 22 is sent to a multiplexer (not shown) as the liquid crystal drive voltage V3'. The output voltage of this multiplexer is A/
It is selected according to the video data from the D conversion circuit 15 and sent to the liquid crystal display panel 16 as a segment electrode drive signal. Then, during the vertical retrace period (VD) and the duty free period in which the O bias is applied, the zero bias control signal EC is at a low level, and the inverter 2
The output of gate circuit G2.4 becomes high level, and the output of gate circuit G2. G3 is on, gate circuit Gi, G4 is off, output line 21
．． 22 both output a voltage of V2. This voltage V2 is the voltage level at which rVseg-VcomJ gives 0 bias. In addition, except for the vertical % line period and the duty free period, that is, during normal operation, the cello bias control signal EC is at a high level and the output power of the inverter 24.

- level, and the gate circuit G2. G3 is off, game I
・Circuit Gi and G4 are turned on, and output line 21 outputs Vl.
, V3 is output from the output line 22.

Therefore, the segment trinotor 2 outputs the voltage V'' or V3 as the segment drive voltage in accordance with the data from the A/D conversion circuit 15. That is, the two-layer segment driver 121 performs voltage output operations as shown in Table 1 below in response to the 7' bias control signal EC.

On the other hand, the main parts of the two-layer common driver 13 shown in Table 1 are constructed as shown in FIG. The common driver 13 has
Liquid crystal drive voltages VO and V2 are generated from the liquid crystal drive voltage generation circuit 11.
．． V4 is given or ■0 is input to the signal line 33 via the P-type -]1- MO8+- transistor 31 and the gate circuit Gll, and V4 is input to the signal line 33 via the N-type MO3+- transistor 32 and the gate circuit Gll. V2 is input to the signal line 33, and V2 is input as is to the signal line 34. ” Biped signal line 33. 34 are connected by a gate circuit G1.2. The signal line 33 includes gate circuits G13a, G], 3b.

. . . respectively via the scanning signal output terminal 0UTI.

Connected to 0UT2, . In addition, the signal line 34
are gate circuits G 14a , G 14b ,...
respectively through the scanning signal output terminals 0UTI and 0UT.
2. Connected to...

The common inverted signal CKF is sent to the level shifter 35.
It is input to the gate I of MO8+- transistor 31.32 through MO8+-. Further, the cell bias control signal EC sent from the controller 14 is level-shifted by a level shifter 36, and then input to the gate of the gate circuit Gll, and further inputted to the gate of the gate circuit G12 via the inverter 37. Ru. Furthermore, in the common driver 13, scanning signals INI, IN2 . ...is created. These scanning signals INI, IN2 . - is level shifter 3
8a.

After being level shifted by 38b, . . . , it is manually applied to the gates of gate circuits GI3a, 13b, . The gate is man-powered.

Next, the operation of the above embodiment will be explained. First, regarding the operation when performing 2/9 thinning processing with the number of common electrodes being 168 lines, the timing chart I shown in FIGS. 4 and 5 will be explained.
・Explain with reference to. When thinning out by 2/9, that is, when scanning lines are thinned out at a ratio of 2 out of 9 lines, the time width of the common signal is set to 2H as shown in FIG. 4, and the common signal is sequentially shifted while overlapping the time of ①H. In addition, the zero bias control signal EC always maintains the “]” signal level,
Each time the time between 2H and 5H elapses, the signal level is set to "H &0".The common shift clock CCP is output every horizontal period as shown in FIG. Zero bias control] roll signal EC is “0”
Output is prohibited at the timing of . And”-
When the zero bias control signal EC goes to the "O" level, the common shift clock CCP is not output, so that the common signal is delayed by 1H and is held in the 0 bias state during that time.

Accordingly, in the common driver 13 whose details are shown in FIG. 3, when the zero bias control signal EC is at the "1" signal level, the gate circuit GIL is in the on state, the gate circuit GI2 is in the off state, and the liquid crystal drive A voltage (1) of 0 or V4 is output to the signal line 33. In this case, the common inversion signal CK_F is inverted in synchronization with the common shift clock CCP, as shown in FIG. 5, and turns on the MOS transistors 31 and 32 alternately. As a result, when the zero bias control signal EC is "1", the liquid crystal drive voltages VD and V4 are alternately output to the signal line 33 according to the common inversion signal CKF. The liquid crystal drive voltages VO and V4 outputted to this signal line 33 are connected to the scanning signal INI.
, IN2. Gate circuit G 13a according to...
Scanning signal output terminal 0UTI via I3b,...
, 0UT2, . . This scanning signal output, that is, the common signal is 2H as shown in FIG.
It has a time width of ]H, and is output sequentially while overlapping for a time of ]H. When the above common signal is in the non-selected state, the gate circuits G ], 4a, i4b, . . . are turned on and V
The voltage level becomes 2.

Therefore, the zero bias control signal EC becomes "0" every time 2H or 5H passes, but as shown in FIGS. 4 and 5, for example, in the 3rd line row, the zero bias control signal EC becomes When it becomes "O", the gate circuit Gll of the common driver 13 is turned off, and the gate I circuit G12 is turned on, and the 2 voltage is outputted to the signal line 33. Therefore, all common signals are at the V2 voltage level. At this time, the segment driver 12 whose details are shown in FIG. 2 is connected to the gate circuit G2. G
3 is turned on, and the V2 voltage is output from the output lines 21 and 22 as the segment drive voltage. As a result, as shown in FIGS. 4 and 5, 2 voltages are supplied to the segment electrodes and common electrodes of the liquid crystal display panel 16, resulting in the O bias state a. Furthermore, when the O bias is applied, the common shift clock CCP is not outputted from the controller 14, so the common data in the shift register in the common driver 13 is not shifted. Therefore, after the IH 0 bias period is finished, the controller 1
When the next common shift clock CCP is sent from No. 4, the common data of the shift register No. 1 is shifted, and the process moves to the selection operation of the next No. 4 line. At this time, segment]...The driver 12 outputs the average value of the video data of these 4 lines and the video data of the previous 3 lines to the liquid crystal display panel 16 as a segment signal. In this way, in the line following the O bias line, by driving the segment electrodes by averaging two lines of video data, it is possible to prevent a line of missing data. Thereafter, 0 bias processing is similarly performed alternately at time intervals of 2H and 5H.

FIG. 6 also shows that the present invention has 192 lines of common electrodes.
This example shows a case where scanning lines are thinned out to 1/9. In this case, the common electrode drive signal has a time width of 3H, and is set to be shifted sequentially from 2H times overlapping. Then, the timing to apply 0 bias with both the voltage applied to the segment electrode and the common electrode as v2 is as follows.
Each time the time of 8H elapses, the time of ]H is set. The above O bias is set by setting the zero bias control signal EC to the "0" level as described in "-". By making the above settings, it is possible to perform the thinning process to 1/9 in the same manner as in the case of FIGS. 4 and 5.

Therefore, the effective value in the case of the ``--named embodiment'' is ``-2 As is clear from the calculation formula in the conventional example shown in FIG. 9,
For the voltage V at the time of optimized half-side selection in equation (2-1), if ■ in equation (3-1) is set as V' and "V' - αV", ■ V ■ - □ a → -M-1 On F" Therefore, by inserting the line Vcom=Vseg, the duty ratio will not drop, but the effective value will drop. In order not to lower this effective value, It is necessary to increase the driving voltage by 1-1 so that the output voltage becomes 1 -, and the details thereof will be explained below.

Now, in the conventional example shown in FIG. 9, V when half-selected is determined according to the properties of the liquid crystal used in the liquid crystal display panel.
(2), Vorf (2) is assumed to be a voltage optimized to provide the best contrast.

Here, if we set "V' = α■" for the voltage V' at the time of half selection in the above equation (3-1), then the following equation is obtained. Here, in order to make the effective values of FIG. 9(b) and (C) equal, the following is established. And since rM<NJ, the ninth
It can be seen that by comparing with FIG. 9(b) and increasing the drive voltage in FIG. 9(c), the effective value can be optimized.

[Effects of the Invention] As described in detail above, according to the present invention, in a multiplex type liquid crystal drive system, display data is provided to the common side and segment side drivers, and a zero bias control signal is also provided to perform arbitrary operation. Since 0 bias can be applied to the time, it is possible to thin out an arbitrary number of scanning lines without increasing the duty. For this reason, in the case of multiplex type LCD TVs where the number of vertical scanning lines is determined by the duty ratio, number of output lines, and manufacturing issues, the driving method according to the number of scanning lines is determined. Yes, it is very advantageous.

[Brief explanation of the drawing]

1 to 6 show embodiments of the present invention. FIG. 1 is a block diagram showing the overall schematic configuration, FIG. 2 is a circuit diagram showing details of the segment driver, and FIG. 3 is a common・Circuit diagram showing driver details, Figures 4 and 5 are timing charts to explain the operation when thinning out to 2/9 with 168 lines of common electrode, and Figure 6 is a timing chart with 192 lines of common electrode. Timing chart 1 to explain the operation when performing 1/9 thinning processing in
, FIGS. 7 to 9 are timing charts for explaining the scanning line thinning operation in the conventional liquid crystal driving system. 11...Liquid crystal drive voltage generation circuit, 12...Segment driver, 13...Common driver, 14...
・Controller, 15... A/D conversion circuit, 16...
Liquid crystal display panel, 23, 35.31'i, 38a,
38b, -, - Level shifter. Applicant's agent Patent attorney Takehiko Suzue Figure 1 r - Figure 2

Claims (1)

[Claims] In the multiplex type liquid crystal driving system, the data output means and the zero bias voltage output means provided in the common side driver and the segment side driver, and the data output means and the zero bias voltage output means are selectively controlled by a zero bias control signal. and a switching means for switching to the zero bias voltage, and the output of the zero bias voltage in the common side and segment side drivers can be set at any time according to the number of scan lines thinned out using the zero bias control signal. LCD drive system.