JPH0981092A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device in which an after-image and a flicker or the like are not present and with which a high picture quality is obtained. SOLUTION: A tuner 3 receives a desired television broadcasting radio wave and converts the received signal into an intermediate frequency signal to supply it to an IF circuit 4 and the intermediate frequency signal is amplified and detected in the circuit 4 and then a video signal and synchronizing signals are respectively supplied to a chroma circuit 5 and a controller 6. The controller 6 shifts a common voltage VCOM to be supplied to the common electrode 10a of a liquid crystal display panel 10 to a negative side by making it respond to the falling of a gate voltage VG.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device.

[0002]

2. Description of the Related Art A liquid crystal display device using a conventional switching element includes, for example, a thin film transistor (TFT).
There is known an active matrix type TFT-LCD panel that drives a liquid crystal by writing a video signal according to a scanning timing for each pixel using a film transistor). This active matrix type liquid crystal display device is generally provided with scanning lines (gate lines) Xn in the row direction and signal lines (drain lines) in the column direction as an equivalent circuit for each pixel, as shown in FIG. ) Ym is provided. The video signal is input to the signal line Ym, and the gate voltage signal VG is sequentially input to the scanning line Xn in accordance with the horizontal scanning timing.

A thin film transistor (TFT) 30 as a switching element is connected to each pixel portion corresponding to the intersection of the scanning line Xn and the signal line Ym. This TF
The liquid crystal capacitance CL is connected to the source electrode S of T30,
The scanning line Xn is connected to the gate electrode G, and the signal line Ym is connected to the drain electrode D. Here, TFT
An n-channel MOS is used for 30.

When the high level VGH of the gate voltage VG is applied to the scanning line Xn of the TFT 30, the TFT 30 is turned on to be in the selected state. At this time, after the drain voltage VD as a video signal as shown in FIG. 6 is written from the signal line Yn to the liquid crystal capacitance CL in the form of electric charge, the next scanning line Xn
While +1 is selected, the previous scanning line Xn is set to the non-selected state and the TFT 30 is turned off, so that the pixel is driven by the charges already written.

[0005]

However, in such a conventional liquid crystal display device, as shown in FIG. 5, since the TFT 30 has a gate-source parasitic capacitance CGS, the TFT 30 is switched. When the pixel is driven in this way, the waveform of the source voltage VS applied to the liquid crystal capacitance CL becomes a distorted waveform that is shifted to the negative side by ΔVGS when the gate voltage VG falls as shown in FIG. 6 (p In the channel MOS TFT, when the gate voltage VG rises, ΔVGD shifts to the positive side.)

This is because the gate voltage VG changes from "High" to "Lo" due to the influence of the gate-source parasitic capacitance CGS.
w "(" Low "to" High "for p-channel TFT)
)), The source voltage VS (drain voltage VD in the p-channel TFT) changes sharply due to the jump-in characteristic.
GD) is called the plunge voltage. The .DELTA.VGS component in the source voltage VS waveform (.DELTA.VGD component in the drain voltage VD waveform in the p-channel TFT) causes a residual image or flicker, which deteriorates the image quality.

Therefore, in order to reduce the above-mentioned adverse effect of ΔVGS, in the conventional example shown in FIG. 7, the auxiliary capacitance electrode is provided in the liquid crystal display panel to form the auxiliary capacitance CS. That is, the above ΔVGS is the gate-source parasitic capacitance CG
S, liquid crystal capacity CLC, high level VGH to low level VG
If the value obtained by subtracting the gate voltage VD of L is VGHL, it can be expressed by the following equation (1).

ΔVGS = {CGS / (CGS + CLC + CS)} VGHL ... (1) From the above equation (1), the jump voltage ΔVGS can be reduced by
It is understood that the auxiliary capacitance CS should be increased. However, if the auxiliary capacitance CS is made too large, there is a problem that the aperture ratio becomes small, the writing time becomes long, and the power consumption becomes large. Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a liquid crystal display device that can obtain high image quality without an afterimage or flicker.

[0009]

According to another aspect of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal cell in which liquid crystal is sealed between a pair of substrates; a plurality of signal lines arranged in a matrix in the liquid crystal cell; Common electrode driving means for supplying a common signal to a scanning line, a switching element connected to a pixel electrode constituting each pixel at each intersection of the signal line and the scanning line, and a common electrode arranged to face the pixel electrode. A scanning side driving means for supplying a scanning signal to each scanning line connected to the gate electrode of each switching element at a predetermined scanning timing, and each signal line connected to the drain or source of the switching element, A liquid crystal display device comprising: a signal-side driving unit that supplies a display signal that changes in an alternating manner, wherein the common electrode driving unit sets a potential of a common signal that is supplied to the common electrode. Serial by response to rising or falling timing of the scanning signal supplied to the scan line by shifting to the negative side or the positive side, to achieve the above object.

That is, according to the first aspect of the invention, the common electrode driving means causes the potential of the common signal supplied to the common electrode to respond to the falling or rising timing of the scanning signal supplied to the scanning line. Then, the so-called jump-in voltage (ΔVGS) is reduced by shifting to the negative side or the positive side. Therefore, it is possible to obtain good image quality without flicker and afterimage, and it is possible to prevent deterioration of the liquid crystal.

In this case, the common electrode driving means supplies the common signal supplied to the common electrode to each signal line connected to the drain or the source of the switching element. It is effective to invert the polarity alternately with the displayed signal.

That is, according to the second aspect of the invention, the common electrode driving means alternately inverts the polarity of the common signal supplied to the common electrode together with the display signal supplied to the signal line.

Therefore, the change in the voltage of the display signal can be made smaller than that in the case where the common signal is constant, and a signal side drive circuit having a low breakdown voltage can be used, so that the liquid crystal display device is inexpensive. Can be one.

Further, in this case, the switching element is an N-channel MOS type T-type.
FT, the signal side driving means supplies a display signal whose polarity is inverted with respect to the common signal to each signal line connected to the drain of the switching element, and the common electrode driving means controls the common electrode driving means. It is effective to shift the potential of the common signal supplied to the scanning line to the negative side in response to the falling timing of the scanning signal supplied to the scanning line.

That is, according to the third aspect of the present invention, the N-channel MOS type TFT is used as the switching element, and the signal side driving means is connected to each signal line connected to the drain electrode of the switching element by the common signal. A display signal whose polarity is inverted with respect to the common electrode driving means, and the common electrode driving means responds the potential of the common signal supplied to the common electrode to the falling timing of the scanning signal supplied to the scanning line,
Shift to the negative side. Therefore, since the N-channel MOS type TFT is used as the switching element, the switching operation can be performed at high speed.

Further, in this case, it is effective that the common electrode driving means changes the potential of the common signal common to the common electrodes at the four-value level.

That is, according to the invention described in claim 4, it is effective that the common electrode driving means changes the potential of the common signal supplied to the common electrode in four-valued level. Therefore, the common signal supplied to the common electrode can accurately follow the change (falling timing) of the scanning signal supplied to the gate electrode of the switching element, and the plunge voltage (ΔVGS) can be further reduced. Becomes

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION A liquid crystal display device of the present invention will be described below based on embodiments. FIG. 1 is a diagram showing a configuration example of a liquid crystal display device of the present invention. FIG. 2 is a diagram showing a specific configuration example of a controller in the liquid crystal display device of FIG. FIG. 3 is a timing chart showing the operation timing of the liquid crystal display device of FIG. FIG. 4 is a schematic view of one pixel of the liquid crystal display panel in the liquid crystal display device of FIG.

First, the structure will be described. 1, the liquid crystal display device 1 includes a rod antenna 2, an electronic tuning tuner 3, an IF circuit (interface circuit) 4, a chroma circuit 5, a controller 6, a drive voltage generation circuit 7, a signal side drive circuit 9, and a scanning side drive circuit. 8 and the liquid crystal display panel 10 and the like.

The liquid crystal display panel 10 adopts an active matrix type, and a scanning line (gate line) Xn and a signal line (drain line) Ym are formed on a substrate (not shown).
Are arranged in a matrix, and the scan line X
An n-channel MOS type T is provided at each intersection of n and the signal line Ym.
It has a switching element composed of an FT (thin film transistor) element and a pixel in which a pixel electrode is connected to the source side of the switching element to form a liquid crystal capacitor.

Each TFT element (not shown) has its gate corresponding to a corresponding scanning line (gate line) X1 to Xn.
And the drains thereof are connected to the corresponding signal lines (drain lines) Y1 to Ym, respectively.
In each TFT element, a liquid crystal capacitor is connected to its source, and a common line (not shown) to which a common voltage (common voltage) VCOM is supplied is connected to the other electrode constituting the liquid crystal capacitor. Have been.

In the liquid crystal display panel 10, the scanning side drive circuit 8 and the signal side drive circuit 9, which will be described later, sequentially drive the scanning lines Xn and the signal lines Ym to select them, and the liquid crystal capacity of each of the sequentially selected pixels, etc. A source voltage corresponding to the video signal is applied to the pixel and the electric charge is held, so that the video signal is displayed. The rod antenna 2 receives television radio waves and supplies the received radio waves to the tuner 3.

The tuner 3 selects a designated channel according to a tuning signal input from the controller 7, converts a desired television broadcast radio wave supplied from the rod antenna 2 into an intermediate frequency signal, and outputs it to the IF circuit 4. Output. The IF circuit 4 includes an intermediate frequency amplification circuit, a video detection circuit,
It is composed of a video amplification circuit, an AFT detection circuit, a sync signal separation circuit, and the like. After the intermediate frequency signal input from the tuner 3 is amplified by the intermediate frequency amplification circuit, the AFT is performed.
AFT detection is performed by the detection circuit, color detection is performed by the video detection circuit to extract a color video signal, and the video signal output by the video detection circuit is amplified by the video amplification circuit and then output to the chroma circuit 5. To do. The sync separation circuit also extracts the sync signal CSYNC from the color video signal and outputs it to the controller 6.

The chroma circuit 5 separates the color video signals supplied from the IF circuit 4 into R, G and B video signals and outputs them to the signal side drive circuit 9. Drive voltage generation circuit 7
Is a driving voltage applied to the scanning side driving circuit 8 and the signal side driving circuit 9.
Further, the drive voltage generation circuit 7 supplies four types of common drive voltages VCOMH, VCOML, ΔVCOMH, and ΔVCOML.
Is supplied to the controller 6.

The scanning side drive circuit 8 scans the liquid crystal display panel 10 for a predetermined number of times with a gate voltage VG as shown in FIG. 3, for example, based on a scanning side drive control signal supplied from a controller 6 described later. It is applied to the line Xn for selective driving. When VGH is applied as the gate voltage VG, the scanning line Xn is in the selected state.

The signal side drive circuit 9 is supplied with R, G, and B video signals from the chroma circuit 5, the signal side drive control signal supplied from the controller 6, and R supplied from the chroma circuit 8. , G, and B, the drain voltage VD whose polarity is inverted every horizontal scanning period (1H) as shown in FIG. 3 is sequentially selected and applied to the signal line Ym of the liquid crystal display panel 10. . As a result, the source voltage V as shown in FIG.
S is held in the liquid crystal capacitance CL connected to the selected scanning line Xn, and the video signal is displayed on the liquid crystal display panel 10.

Further, in this case, the voltages of opposite polarities are applied to the adjacent scanning lines Xn, and the positive and negative voltages can be evenly distributed over the entire liquid crystal display panel 10. That is, since the voltage of each pixel can be evenly distributed in the vertical direction, the occurrence of flicker can be suppressed.

The controller 6 generates a scan side drive control signal and a signal side drive control signal based on the synchronization signal C-SYNC input from the IF circuit 4, and the scan side drive circuit 8
And to the signal side drive circuit 9, respectively. Further, the controller 6 selects the common drive voltages VCOMH, VCOML, ΔVCOMH, and ΔVCOML supplied from the drive voltage generation circuit 7 based on the composite synchronization signal C-SYNC input from the IF circuit 4 to display a TFT liquid crystal display. It is supplied to the common electrode 10a of the panel 10.

Here, FIG. 2 shows a concrete example of the configuration of the controller 6. 2, the controller 6 includes a horizontal / vertical separation circuit 61, a basic clock generation circuit 62, a horizontal decoder 63, a horizontal counter 64, a vertical decoder 65,
Vertical counter 66, control signal generation circuit 67, and VCOM
It is composed of a signal generation circuit 68.

The horizontal and vertical separation circuit 61 is the IF circuit 4
Horizontal sync signal HSYNC from sync signal CSYNC supplied from
And the vertical synchronizing signal VSYNC are separated, and the horizontal counter 64
And to the vertical counter 66. The basic clock generation circuit 62 generates the basic clock signal CK and supplies it to the horizontal counter 64 and the vertical counter 66, respectively.

The horizontal counter 64, based on the horizontal synchronizing signal HSYNC supplied from the horizontal / vertical separation circuit 61,
The basic clock CK supplied from the basic clock generation circuit 62 is counted, and the obtained count value is supplied to the horizontal decoder 63. The horizontal decoder 63 uses the horizontal counter 6
The decoded value obtained by decoding the count value supplied from 4 is supplied to the control signal generation circuit 67.

The vertical counter 66, based on the vertical synchronizing signal VSYNC supplied from the horizontal / vertical separation circuit 61,
The basic clock CK supplied from the basic clock generation circuit 62 is counted, and the obtained count value is supplied to the vertical decoder 65. The vertical decoder 65 includes the vertical counter 6
The count value supplied from 6 is decoded, and the obtained decode value is supplied to the control signal generation circuit 67.

The control signal generation circuit 67 includes the horizontal decoder 6
A signal side drive control signal and a scan side drive control signal are generated based on the outputs supplied from the 3 and the vertical decoder 65, and are supplied to the signal side drive circuit 9 and the scan side drive circuit 8, respectively. Further, the control signal generation circuit 67 includes the vertical decoder 6
A control signal for common voltage generation is generated based on the output supplied from No. 5, and is supplied to the VCOM signal generation circuit 68.

The VCOM signal generation circuit 68, based on the common voltage generation control signal supplied from the control signal generation circuit 67, has four types of common drive voltages VCOMH, VCOML, ΔVCOMH supplied from the drive voltage generation circuit 7. And ΔVCOML
Is selected to supply the common voltage VCOM as shown in FIG. 3 to the common electrode 10a of the liquid crystal display panel 10.

That is, as shown in FIG. 3, the common voltage VCOM is set to the drain voltage VD for every one horizontal scanning period (1H).
And the gate voltage VG
The common voltage is shifted by ΔVCOM to the negative side in response to the timing of the falling edge (VGH → VGL).

More specifically, referring to FIG. 3, the common voltage V
When COM is at “Low level”, that is, when VCOML is applied, the gate voltage VG falls (VGH → VGL).
In this case, in order to shift the common voltage VCOM to the negative side by ΔVCOM in response to the falling timing, ΔVCOML
Is applied (point a). Then, after a predetermined time has passed, V
Return the voltage level to COML (point b). Similarly, when the common voltage VCOM is at “High level”, that is, when VCOMH is applied, the gate voltage VG falls (VGH → VG
In the case of L), ΔVCOMH is applied in order to shift the common voltage VCOM to the negative side by ΔVCOM in response to the falling timing (point c). Then, after a lapse of a predetermined time, the voltage level is returned to VCOMH again (point d).

As described above, when the common voltage VCOM is driven, the equivalent circuit of one pixel of the liquid crystal display panel 10 when the gate voltage VG falls can be represented as shown in FIG. That is, when the gate voltage VG falls, TF
Since T is turned off, it can be represented as a circuit in which a TFT is omitted and a path is formed between VG and VCOM as shown in FIG. In FIG. 4, a voltage of magnitude | VG-VCOM- (ΔVCOM) | is applied to the liquid crystal capacitance CL and the auxiliary capacitance CS, and the apparent VG is reduced, so that the capacitance of each pixel ( The jump voltage ΔV without changing the auxiliary capacitance CS, the liquid crystal capacitance CL, and the parasitic capacitance CGS).
GS can be reduced. Therefore, the apparent VG
Can be lowered.

As a result, unlike the conventional source voltage VS waveform having a distortion which is shifted to the negative side by ΔVGS when the gate voltage VG falls as shown in FIG. 6, as shown in FIG. , Source voltage V of proper waveform
S will be applied to the liquid crystal capacitance CLC. Therefore, by changing the common voltage to the negative side in response to the falling of the gate voltage without increasing or decreasing the auxiliary capacitance CS,
The jump-in voltage ΔVGS generated in the parasitic capacitance CGS can be reduced to remove the source voltage VS, and the occurrence of flicker can be prevented.

Although the polarity of the common voltage is inverted for each scanning line in the above embodiment, the polarity may be inverted for each field or frame. Further, in the above-described embodiment, the method of inverting the polarity of the common voltage has been described, but it is also applicable to the method of inverting only the drain voltage VD without changing the polarity of the common voltage, keeping the common voltage constant. You can

Next, the operation of this embodiment will be described. The main power source (not shown) of the liquid crystal display device 1 of the present embodiment is turned on.
Then, a power supply circuit (not shown) supplies a power supply voltage to each block shown in FIG. 1 to start the operation of each block. First, the television wave received from the rod antenna 2 is supplied to the tuner 3, the tuner 3 selects a desired channel according to the tuning signal input from the controller 7, and the desired television supplied from the rod antenna 2 is selected. Broadcast radio waves are converted into an intermediate frequency signal and supplied to the IF circuit 4.

In the IF circuit 4, the intermediate frequency signal input from the tuner 3 is amplified by the intermediate frequency amplifying circuit and then AFT detected by the AFT detecting circuit.
Video detection is performed by the video detection circuit to extract a color video signal, and the video signal supplied from the video detection circuit is amplified by the video amplification circuit and then supplied to the chroma circuit 5. In the IF circuit 4, the sync separation circuit separates the sync signal CSYNC from the composite color video signal and supplies it to the controller 6.

In the drive voltage generation circuit 7, a drive voltage is generated and supplied to the scanning side drive circuit 8 and the signal side drive circuit 9, and four types of common drive voltages VCOMH, VCOML,
ΔVCOMH and ΔVCOML are generated and supplied to the controller 6. In the chroma circuit 5, the R, G and B video signals are separated from the color video signal supplied from the IF circuit 4 and are supplied to the signal side drive circuit 9.

In the controller 6 (its specific structure is shown in FIG. 2), the horizontal and vertical separation circuits 61
The horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSYNC are separated from the synchronizing signal CSYNC supplied from the F circuit 4 and are supplied to the horizontal counter 64 and the vertical counter 66. In the horizontal counter 64 and the vertical counter 66, the basic clock generating circuit is provided. The basic clock CK supplied from 62 is counted based on the horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSYNC, and the obtained count value is the horizontal decoder 63.
After being decoded by the vertical decoder 65, the signal is supplied to the control signal generation circuit 67. In the control signal generation circuit 67, based on the outputs supplied from the horizontal decoder 63 and the vertical decoder 65, the signal side drive control signal and the scanning side are supplied. A drive control signal is generated and supplied to the signal side drive circuit 9 and the scanning side drive circuit 8, respectively, and a common voltage generation control signal is generated based on the output supplied from the vertical decoder 65 to generate VCOM. It is supplied to the signal generation circuit 68.

Then, in the VCOM signal generation circuit 68, based on the common voltage generation control signal supplied from the control signal generation circuit 67, four types of common drive voltages VCOMH, VCOML, supplied from the drive voltage generation circuit 7 are generated. ΔVCOMH and ΔVCOML are selected to reverse the polarity of the common voltage VCOM as shown in FIG. 3, that is, the common voltage VCOM with respect to the drain voltage VD every one horizontal scanning period (1H), and the gate voltage. In response to the fall of VG,
The common voltage VCOM obtained by shifting the voltage to the negative side by ΔVCOM for a predetermined period is the common electrode 10 of the liquid crystal display panel 10.
a.

Specifically, as shown in FIG. 3, when the common voltage VCOM is at "Low level", that is, when VCOML is applied, the gate voltage VG falls (VGH → VG).
In case of L), in order to shift the common voltage VCOM to the negative side by ΔVCOM in response to the falling timing,
Apply COML (point a). Then, after a lapse of a predetermined time, the voltage level is returned to VCOML again (point b). Similarly, when the common voltage VCOM is at “High level”, that is, when VCOMH is applied, the gate voltage VG falls (VGH
In the case of (→ VGL), ΔVCOMH is applied in order to shift the common voltage VCOM to the negative side by ΔVCOM in response to the falling timing (point c). Then, after a lapse of a predetermined time, the voltage level is returned to VCOMH again (point d).

In the scan side drive circuit 8, the gate voltage VG as shown in FIG. 3 is supplied to the scan line Xn and the scan line Xn is selectively driven based on the scan side drive control signal supplied from the controller 6. It In the signal side drive circuit 9, based on the signal side drive control signal supplied from the controller 6, 1 according to each video signal of R, G, B supplied from the chroma circuit 5 as shown in FIG. The drain voltage VD whose polarity is alternately inverted with respect to the common voltage is supplied to the signal line Ym every horizontal scanning period (1H).

In the liquid crystal display panel 10, a common voltage as shown in FIG. 3 is supplied to its common electrode, and
By the gate voltage and the drain voltage as shown in FIG. 3 supplied from the scanning side driving circuit 8 and the signal side driving circuit 9,
The scanning lines X1 to Xm and the signal electrodes Y1 to Yn are selectively driven, and the liquid crystal capacitance CLC corresponds to the color image signal shown in FIG.
A source voltage VS as shown in (1) is applied and a video signal is displayed.

As described above, in the present embodiment, the potential of the common signal supplied to the common electrode is shifted to the negative side in response to the falling timing of the scanning signal supplied to the scanning line. Causes the plunge voltage (Δ
Since the VGS) is reduced to prevent the distortion of the source voltage waveform, it is possible to obtain good image quality without flicker and afterimage, and to prevent deterioration of the liquid crystal. Further, in the present embodiment, since the common signal supplied to the common electrode is alternately inverted with the display signal supplied to the signal line, the voltage change of the display signal is
The common signal can be made smaller than when it is constant, and a signal side drive circuit with a low breakdown voltage can be used, and as a result, the liquid crystal display device can be made inexpensive.

Further, in the present embodiment, since the potential of the common signal supplied to the common electrode is changed in four level, the common signal supplied to the common electrode is supplied to the gate electrode of the switching element. The change (falling timing) of the scanning signal can be accurately followed, and the plunge voltage (ΔVGS) can be further reduced.

In the above-described embodiment, the n-channel MOS type TFT is used as the switching element, but it goes without saying that it can be applied to the p-channel MOS type TFT. In that case, the potential of the common signal supplied to the common electrode may be shifted to the positive side in response to the rising timing of the scan signal supplied to the scan line.

[0051]

According to the liquid crystal display device of the first aspect,
The so-called jump-in voltage (ΔVGS) is reduced by shifting the potential of the common signal supplied to the common electrode to the negative side or the positive side in response to the rising or falling timing of the scanning signal supplied to the scanning line. Let Therefore, it is possible to reduce the DC component of the voltage applied to the liquid crystal, it is possible to obtain a good image quality without flicker, and it is possible to prevent deterioration of the liquid crystal.

According to the second aspect of the invention, the voltage change of the display signal can be made smaller than that in the case where the common signal is constant, and an inexpensive signal side drive circuit having a low withstand voltage is provided. Since it can be used, the liquid crystal display device can be made inexpensive.

According to the third aspect of the invention, since the N-channel MOS type TFT is used as the switching element, high speed switching operation can be performed.

According to the invention described in claim 4, the common signal supplied to the common electrode can accurately follow the change (falling timing) of the scanning signal supplied to the gate electrode of the switching element. , It is possible to further reduce the plunge voltage (ΔVGS).

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device of the present invention.

FIG. 2 is a diagram showing a specific circuit configuration of the controller of FIG.

FIG. 3 is a timing chart showing drive waveforms of the liquid crystal display device of the present invention.

FIG. 4 is a diagram showing an equivalent circuit of one pixel of the liquid crystal display panel of FIG.

FIG. 5 is a first diagram showing an equivalent circuit of one pixel of a conventional liquid crystal display device.

FIG. 6 is a waveform diagram for explaining the problems of the conventional example.

FIG. 7 is a second diagram showing an equivalent circuit of one pixel of the conventional liquid crystal display device.

[Explanation of symbols]

 1 Liquid crystal display device 2 Antenna 3 Tuner 4 IF circuit 5 Chroma circuit 6 Controller 7 Drive voltage generation circuit 8 Scan side drive circuit 9 Signal side drive circuit 10 Liquid crystal display panel 30 TFT 61 Horizontal and vertical separation circuit 62 Basic clock generation circuit 63 Horizontal Decoder 64 Horizontal counter 65 Vertical decoder 66 Vertical counter 67 Control signal generation circuit 68 VC0M signal generation circuit X1 to Xn scanning line Y1 to Yn signal line 101 n-channel MOS type TFT CL liquid crystal capacitance CS auxiliary capacitance

Claims (4)

[Claims] 1. A liquid crystal cell in which liquid crystal is sealed between a pair of substrates, a plurality of signal lines and scanning lines arranged in a matrix in the liquid crystal cell, and each intersection of the signal line and the scanning line. A switching element connected to a pixel electrode forming each pixel, a common electrode driving unit that supplies a common signal to a common electrode arranged to face the pixel electrode, and a gate electrode of each switching element. Scanning side driving means for supplying a scanning signal to each scanning line at a predetermined scanning timing, and signal side driving means for supplying a display signal that changes in an alternating manner to each signal line connected to the drain or source of the switching element, In the liquid crystal display device, the common electrode driving unit changes the potential of the common signal supplied to the common electrode to the fall of the scan signal supplied to the scan line. Or in response to the rising timing,
A liquid crystal display device characterized by shifting to a negative side or a positive side. 2. The common electrode driving means alternately reverses the polarity of a common signal supplied to the common electrode together with a display signal supplied to each signal line connected to the drain or the source of the switching element. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a liquid crystal display device. 3. The switching element is an N channel M
An OS type TFT, wherein the signal side driving means supplies a display signal whose polarity is inverted with respect to the common signal to each signal line connected to the drain of the switching element, and the common electrode driving means comprises: 3. The liquid crystal display device according to claim 1, wherein the potential of the common signal supplied to the common electrode is shifted to the negative side in response to the falling timing of the scan signal supplied to the scan line. . 4. The liquid crystal display device according to claim 2, wherein the common electrode driving means changes the potential of a common signal supplied to the common electrode at four levels.