JPS63132460A - Thin semiconductor module substrate - Google Patents
Thin semiconductor module substrateInfo
- Publication number
- JPS63132460A JPS63132460A JP61279069A JP27906986A JPS63132460A JP S63132460 A JPS63132460 A JP S63132460A JP 61279069 A JP61279069 A JP 61279069A JP 27906986 A JP27906986 A JP 27906986A JP S63132460 A JPS63132460 A JP S63132460A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- resin
- semiconductor module
- thin
- dam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 83
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000005452 bending Methods 0.000 claims abstract description 22
- 229920005989 resin Polymers 0.000 claims abstract description 21
- 239000011347 resin Substances 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000003822 epoxy resin Substances 0.000 claims abstract description 8
- 239000011521 glass Substances 0.000 claims abstract description 8
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 8
- 239000000919 ceramic Substances 0.000 claims abstract description 5
- 230000003014 reinforcing effect Effects 0.000 claims description 8
- 239000000853 adhesive Substances 0.000 abstract description 3
- 229910001111 Fine metal Inorganic materials 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 238000007789 sealing Methods 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、例えばＩＣカードなどに適用される半導体
モジュールにおける薄型半導体モジュールノ、（板に関
し、さらに詳しくは、薄型半導体モジュールノ、（板に
対する曲げ強度を向上させるための改良構造に係るもの
である。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a thin semiconductor module (board) in a semiconductor module applied to, for example, an IC card. This relates to an improved structure for improving bending strength.
従来例による一般的なこの種の薄型半導体モジュールの
４！要構成を第５図および第６図に示しである。4 of this type of conventional thin semiconductor module! The essential structure is shown in FIGS. 5 and 6.
すなわち、第５図はこの従来例構成での薄型半導体モジ
ュールの要部を切り欠いて示す平面図、Ｅｉｆｇ６図は
同上断面図である。これらの従来例各図において、符号
ｌは通常の場合、ガラスエポキシ樹脂、ＢＴ樹脂などに
よって形成した基板本体、１２はこの基板本体１の表面
上に選択的に設けられた同効質のダム基板であり、これ
らの両基板によって薄型多層基板を形成している。That is, FIG. 5 is a cutaway plan view showing essential parts of a thin semiconductor module having this conventional configuration, and FIG. 6 is a sectional view of the same. In each figure of these conventional examples, the reference numeral 1 is usually a substrate body made of glass epoxy resin, BT resin, etc., and 12 is a dam substrate of the same quality selectively provided on the surface of this substrate body 1. These two substrates form a thin multilayer substrate.
また、３は前記基板本体ｌ−Ｈに接着剤４などで接着固
定して搭載した半導体チップ、５はこの半導体チップ３
の表面電極であり、さらに、６は基板本体１の表面に形
成された外部電極、７はこの外部電極６に基板内配線８
で接続された基板本体１の表面リード、９は表面電極５
と表面リード７の端子部とを接続する金属細線、 １０
はこれらの半導体チップ３および金属細線８の部分を封
止するＳｉ市樹脂である。Further, 3 is a semiconductor chip mounted on the substrate main body L-H by adhesively fixing it with adhesive 4, etc., and 5 is this semiconductor chip 3.
Further, 6 is an external electrode formed on the surface of the substrate main body 1, and 7 is a surface electrode formed on the surface of the substrate body 1, and 7 is a surface electrode formed on the surface of the substrate body 1.
The surface lead 9 of the board body 1 is connected to the surface electrode 5.
and a terminal part of the surface lead 7, a thin metal wire, 10
is a Si resin for sealing the semiconductor chip 3 and the thin metal wires 8.
このように、従来例構造による半導体モジュールでは、
外部からの半導体チップ３の部分の腐食防ｌヒ、ならび
に同半導体チフブ３．および金属細線９の露出防止など
のために、封止樹脂１０による樹脂封止をなすと共に、
ダム基板１２によりこの封止樹脂１０の厚さを大きくと
り得るようにしているのである。In this way, in the semiconductor module with the conventional structure,
Prevention of corrosion of the semiconductor chip 3 from the outside, and protection of the semiconductor chip 3. In order to prevent exposure of the thin metal wire 9, resin sealing is performed with a sealing resin 10, and
The dam substrate 12 allows the sealing resin 10 to have a large thickness.
しかしながら、前記構造による従来例で、の薄型半導体
モジュールの場合には、薄型多層基板材料としてのガラ
スエポキシ樹脂、ＢＴ樹脂などの強度が比較的弱く、殊
に曲げ応力に対して非常に弱い性状を有するために、使
用中、この薄型多層基板に何等かの曲げ応力が加えられ
ると、内部に搭載された半導体チップを破損する惧れが
あるなどの問題点を有するものであった。However, in the case of the conventional thin semiconductor module with the above structure, the glass epoxy resin, BT resin, etc. used as the thin multilayer substrate material have relatively low strength, and are particularly weak against bending stress. Therefore, if some bending stress is applied to this thin multilayer substrate during use, there is a risk that the semiconductor chip mounted inside may be damaged.
従って、この発明の目的とするところは、従来例装置で
のこのような問題点に鑑み、曲げ応力を強化した。この
種の薄型半導体モジュール基板を提供することである。Therefore, an object of the present invention is to strengthen the bending stress in view of such problems in the conventional device. An object of the present invention is to provide a thin semiconductor module substrate of this type.
前記目的を達成させるために、この発明に係る薄型半導
体モジュール基板は、基板本体に積層されて薄型多層基
板を構成するダム基板として、樹脂コーティング金属基
板、金属基板、またはセラミック基板などの曲げ強度の
高い補強基板を用いるようにしたものである。In order to achieve the above object, the thin semiconductor module substrate according to the present invention is a dam substrate that is laminated on a substrate body to form a thin multilayer substrate, and is made of resin-coated metal substrates, metal substrates, ceramic substrates, etc. with low bending strength. A highly reinforced substrate is used.
すなわち、この発明においては、薄型多層基板のダム基
板に、曲げ強度の高い補強基板を用いることによって十
分に補強でき、この薄型多層基板に曲げ応力が加えられ
ても、内部に搭載された半導体チップを破損する惧れが
なく、これによって薄型半導体モジュールの信頼性を格
段に向上し得るのである。In other words, in this invention, the dam board of the thin multilayer board can be sufficiently reinforced by using a reinforcing board with high bending strength, and even if bending stress is applied to the thin multilayer board, the semiconductor chips mounted inside can be There is no risk of damaging the thin semiconductor module, thereby significantly improving the reliability of the thin semiconductor module.
以下、この発明に係る薄型半導体モジュール基板の実施
例につき、第１図ないし第４図を参照して詳細に説明す
る。Hereinafter, embodiments of the thin semiconductor module substrate according to the present invention will be described in detail with reference to FIGS. 1 to 4.
第１図、および第２図はこの発明の第１実施例を適用し
た薄型半導体モジュールの概要構成を模式的に示す要部
を切り欠いた平面図、および断面図である。FIGS. 1 and 2 are a plan view and a sectional view, with main parts cut away, schematically showing the general structure of a thin semiconductor module to which a first embodiment of the present invention is applied.
この第１図、第２図に示す第１実施例構造において、前
記第５図、第６図従来例構造と同一符号は同一または相
当部分を示しており、この第１実施例では、前記ガラス
エポキシ樹脂、ＢＴ樹脂などによるダム基板１２に代え
、樹脂コーティング金属基板、金属基板、またはセラミ
ック基板などの曲げ強度の高い補強基板２を用いたもの
である。In the structure of the first embodiment shown in FIGS. 1 and 2, the same reference numerals as in the conventional structure shown in FIGS. 5 and 6 indicate the same or corresponding parts. In place of the dam board 12 made of epoxy resin, BT resin, or the like, a reinforcing board 2 having high bending strength such as a resin-coated metal board, a metal board, or a ceramic board is used.
従って、この第１実施例構造の場合には、基板本体１に
積層されて薄型多層基板を構成するダム基板として１曲
げ強度の高い補強基板２を用いているために、従来例で
のガラスエポキシ樹脂、ＢＴ樹脂などによるダム基板１
２とは異なって、使用中などに、たとえこの薄型多層基
板に曲げ応力が加えられたとしても、内部に搭載された
半導体チップを破損する惧れかない。Therefore, in the case of the structure of the first embodiment, since the reinforcing substrate 2 with high bending strength is used as the dam substrate laminated on the substrate body 1 to form a thin multilayer substrate, the glass epoxy Dam board 1 made of resin, BT resin, etc.
Unlike 2, even if bending stress is applied to this thin multilayer substrate during use, there is no risk of damaging the semiconductor chip mounted inside.
また次に、第３図、および第４図はこの発明の第２実施
例を適用した薄型半導体モジュールの概要構成を模式的
に示す要部を切り欠いた平面図。Next, FIGS. 3 and 4 are plan views with main parts cut away, schematically showing the general structure of a thin semiconductor module to which a second embodiment of the present invention is applied.
および断面図であり、この第２実施例構造においては、
前記第１実施例構造でのダム基板に代えた曲げ強度の高
い補強基板２に併せて、基板本体１の裏面に対しても、
同様な曲げ強度の高い補強基板１１を積層させたもので
、この場合には、この補強基板１１に外部電極Ｂを設け
ている。and a sectional view, and in this second embodiment structure,
In addition to the reinforced substrate 2 with high bending strength, which replaced the dam substrate in the structure of the first embodiment, the back surface of the substrate main body 1 was also
The reinforcing substrates 11 having similar high bending strength are laminated, and in this case, the reinforcing substrates 11 are provided with external electrodes B.
すなわち、この第２実施例構造では、基板本体１の表裏
両面に補強基板２．１１を設けて薄型多層基板を構成さ
せているために、第１実施例構造よりも一層曲げ強度を
高くでき、さらに一方で、このようにガラスエポキシ樹
脂、ＢＴ樹脂などによる基板本体１を１曲げ強度の高い
補強基板２，１１で挟持させであることから、これらの
両基板ｌおよび２゜１１相互の熱膨張係数の差による基
板自体の反りなどの不利をも、良好に緩和し得ると云う
利点もある。That is, in the structure of the second embodiment, since the reinforcing substrates 2.11 are provided on both the front and back surfaces of the board body 1 to form a thin multilayer board, the bending strength can be made higher than that of the structure of the first embodiment. Furthermore, since the substrate body 1 made of glass epoxy resin, BT resin, etc. is sandwiched between the reinforcing substrates 2 and 11 with high bending strength, the mutual thermal expansion of these two substrates 1 and 2. Another advantage is that disadvantages such as warping of the substrate itself due to the difference in coefficients can be alleviated.
以上詳述したように、この発明によれば、ガラスエポキ
シ樹脂、ＢＴ樹脂などによる基板本体、およびこの基板
本体の表面上に選択的に設けられる同効質のダム基板か
らなる薄型多層基板を用い、基板本体とに半導体素子を
搭載して構成する薄型半導体モジュールにおいて、基板
本体と共々に薄型多層基板となるダム基板を、樹脂コー
ティング金属基板、金属基板、またはセラミック基板な
どの曲げ強度の高い補強基板により形成させているので
、従来のようにガラスエポキシ樹脂、８丁樹脂などによ
るダム基板を用いる場合とは異なって、使用中などに、
たとえこの薄型多層基板に曲げ応力が加えられたとして
も、内部に搭載された半導体チップを破損する惧れがな
く、この結果、薄型半導体モジュール自体の信頼性を格
段に向上し得ると共に、その耐用寿命を効果的に延長で
きるのであり、しかも構造的にも頗る簡単で、容易かつ
安価に実施し得るなどの優れた特長を有するものである
。As detailed above, according to the present invention, a thin multilayer substrate is used, which is composed of a substrate body made of glass epoxy resin, BT resin, etc., and a dam substrate of the same quality selectively provided on the surface of this substrate body. In a thin semiconductor module consisting of a substrate body and a semiconductor element mounted on it, the dam substrate, which together with the substrate body forms a thin multilayer substrate, is reinforced with a resin-coated metal substrate, a metal substrate, or a ceramic substrate with high bending strength. Since it is formed from a substrate, unlike the conventional case where a dumb substrate made of glass epoxy resin, 8-piece resin, etc. is used,
Even if bending stress is applied to this thin multilayer substrate, there is no risk of damaging the semiconductor chips mounted inside, and as a result, the reliability of the thin semiconductor module itself can be significantly improved, and its durability can be increased. It has excellent features such as being able to effectively extend the lifespan, being extremely simple in structure, and being able to be implemented easily and inexpensively.
第１図、および第２図はこの発明に係る薄型半導体モジ
ュール基板の一実施例を適用した薄型半導体モジュール
の概要構成を模式的に示す要部を切り欠いた平面図、お
よび断面図、第３図、および第４図は同上能の実施例に
よる薄型半導体モジュール基板を適用した薄型半導体モ
ジュールの概要構成を模式的に示す要部を切り欠いた平
面図。
および断面図であり、また第５図、および第６図は従来
例による薄型半導体モジュール基板を適用した薄型半導
体モジュールの概要構成を模式的に示す要部を切り欠い
た平面図、および断面図である。
ｌ・・・・基板本体、２・・・・ダム基板としての基板
本体表面の曲げ強度の高い補強基板、３・・・・半導体
チップ、４・・・・接着剤、５・・・・半導体チップの
表面電極、６・・・・外部電極、７・・・・基板本体の
表面リード、８・・・・基板内配線、９・・・・金属細
線、１０・・・・封止樹脂、１１・・・・基板本体裏面
の曲げ強度の高い補強基板。
代理人 大 岩 増 雄
第１図
第２図
第３図
第４図
１１：甚１反本イ本亥面←繍伸基根
第５図
第６図
手続補正書（自発）
１、事件の表示 特願昭 ６１−２７９０６９号２
、発明の名称 。
薄型半導体モジュール基板
３、補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目２番３号名
称 （６０１）三菱電機株式会社代表者志岐守哉
４、代理人
住 所 東京都千代田区丸の内二丁目２番３号
三菱電機株式会社内
氏名 （７３７５）弁理士大岩増雄
（連絡先０３（２１３）３４２１持許部） ′ パ
５、補正の対象
メ
ロ、補正の内容
（１）明細書４頁１５行の「十分に」を削除する。
（２）同書４頁１７行の「チップを破損する慣れがなく
、」を「チップが破損し難く、」と補正する。
（３）同書５頁２０行の「たとえ」を削除する。
（４）同書６頁２行の「破損する惧れがない。Ｊを「破
損し難い。」と補正する。
（５）同書７頁１４行の「たとえ」を削除する。
（６）同書７頁１６行の「チップを破損する惧れがなく
、」を「チップが破損し難く、」と補正する。
以 上1 and 2 are a plan view and a sectional view schematically showing the general structure of a thin semiconductor module to which an embodiment of the thin semiconductor module substrate according to the present invention is applied; 4 and 4 are plan views with main parts cut away, schematically showing the general structure of a thin semiconductor module to which the thin semiconductor module substrate according to the embodiment of Noh is applied. 5 and 6 are a cutaway plan view and a cross-sectional view schematically showing the general structure of a thin semiconductor module to which a conventional thin semiconductor module substrate is applied. be. l...Substrate body, 2...Reinforced substrate with high bending strength on the surface of the board body as a dam board, 3...Semiconductor chip, 4...Adhesive, 5...Semiconductor Chip surface electrode, 6... External electrode, 7... Surface lead of board body, 8... In-board wiring, 9... Fine metal wire, 10... Sealing resin, 11... Reinforced board with high bending strength on the back side of the board main body. Agent Masuo Oiwa Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 11: Jin 1 anti-hon I original face ← Suinobu Gen Gen 5 Fig. 6 Procedural amendment (voluntary) 1. Indication of the incident Patent Application No. 61-279069 2
, title of the invention. Thin semiconductor module substrate 3, relationship with the amended case Patent applicant address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Moriya Shiki, representative of Mitsubishi Electric Corporation 4, agent address: Address: Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (7375) Patent Attorney Masuo Oiwa (Contact information: 03 (213) 3421, Licensing Department) ) Delete "sufficiently" on page 4, line 15 of the specification. (2) On page 4, line 17 of the same book, ``I'm not used to damaging chips,'' has been amended to ``I don't easily damage chips.'' (3) Delete the ``parable'' on page 5, line 20 of the same book. (4) In the same book, page 6, line 2, "There is no risk of damage. J has been amended to read "Hard to damage." (5) Delete "parable" on page 7, line 14 of the same book. (6) "There is no risk of chip damage" on page 7, line 16 of the same book is amended to "chip is unlikely to be damaged."that's all
Claims (2)
体、およびこの基板本体の表面上に選択的に設けられる
同効質のダム基板からなる薄型多層基板を用い、前記基
板本体上に半導体素子を搭載して構成する薄型半導体モ
ジュールにおいて、前記ダム基板として、樹脂コーティ
ング金属基板、金属基板、またはセラミック基板などの
曲げ強度の高い補強基板を用いたことを特徴とする薄型
半導体モジュール基板。(1) Using a thin multilayer substrate consisting of a substrate body made of glass epoxy resin, BT resin, etc., and a dam substrate of the same efficiency selectively provided on the surface of this substrate body, semiconductor elements are mounted on the substrate body. 1. A thin semiconductor module substrate comprising: a reinforced substrate having high bending strength, such as a resin-coated metal substrate, a metal substrate, or a ceramic substrate, as the dam substrate.
とする特許請求の範囲第１項に記載の薄型半導体モジュ
ール基板。(2) The thin semiconductor module substrate according to claim 1, characterized in that a reinforcing substrate is provided on the back surface of the substrate body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61279069A JPS63132460A (en) | 1986-11-21 | 1986-11-21 | Thin semiconductor module substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61279069A JPS63132460A (en) | 1986-11-21 | 1986-11-21 | Thin semiconductor module substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63132460A true JPS63132460A (en) | 1988-06-04 |
Family
ID=17605979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61279069A Pending JPS63132460A (en) | 1986-11-21 | 1986-11-21 | Thin semiconductor module substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63132460A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58138057A (en) * | 1982-02-12 | 1983-08-16 | Dainippon Printing Co Ltd | Integrated circuit card |
| JPS61217298A (en) * | 1985-03-25 | 1986-09-26 | 日立マイクロコンピユ−タエンジニアリング株式会社 | Integrated circuit card |
| JPS62135395A (en) * | 1985-12-09 | 1987-06-18 | 松下電器産業株式会社 | Integrated circuit module for integrated circuit card |
-
1986
- 1986-11-21 JP JP61279069A patent/JPS63132460A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58138057A (en) * | 1982-02-12 | 1983-08-16 | Dainippon Printing Co Ltd | Integrated circuit card |
| JPS61217298A (en) * | 1985-03-25 | 1986-09-26 | 日立マイクロコンピユ−タエンジニアリング株式会社 | Integrated circuit card |
| JPS62135395A (en) * | 1985-12-09 | 1987-06-18 | 松下電器産業株式会社 | Integrated circuit module for integrated circuit card |
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