JPS63131545A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS63131545A JPS63131545A JP27641986A JP27641986A JPS63131545A JP S63131545 A JPS63131545 A JP S63131545A JP 27641986 A JP27641986 A JP 27641986A JP 27641986 A JP27641986 A JP 27641986A JP S63131545 A JPS63131545 A JP S63131545A
- Authority
- JP
- Japan
- Prior art keywords
- film
- excimer laser
- psg film
- silicon oxide
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims 3
- 238000000034 method Methods 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000011574 phosphorus Substances 0.000 claims abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 4
- 239000011229 interlayer Substances 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 4
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000001678 irradiating effect Effects 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000674 effect on sodium Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置の多層配線の眉間絶縁膜お
よび表面保護膜として用いるリンを添加した酸化シリコ
ン膜の表面段差を緩やかに平坦化を行なう方法に関する
。[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a method for gently flattening the surface steps of a phosphorus-doped silicon oxide film used as an insulating film between the eyebrows and a surface protective film of multilayer wiring of a semiconductor integrated circuit device. Concerning how to do it.
半導体集積回路装置の多層配線の層間絶縁膜および表面
保護膜としては、ナトリウムイオンに対してゲッタリン
グ効果を持つリンを添加した酸化シリコン膜（以下ＰＳ
Ｇ膜と記す）が用いられている。ＰＳＧＫＫ上に形成す
る配線金属膜の被覆性を改善し段差部での配線金属の断
線を防止し、半導体集積回路装置の信頼性を向上させる
必要がある。このためＰＳＧ膜の急峻な段差部の傾斜を
緩やかに平坦化するため、いわゆるリフローと呼ばれる
１ ０００℃程度の高温熱処理を拡散炉で行なっている
。As interlayer insulating films and surface protective films for multilayer wiring in semiconductor integrated circuit devices, silicon oxide films doped with phosphorus (hereinafter referred to as PS), which have a gettering effect on sodium ions, are used
G film) is used. It is necessary to improve the coverage of the wiring metal film formed on the PSGKK, to prevent disconnection of the wiring metal at the step portion, and to improve the reliability of the semiconductor integrated circuit device. Therefore, in order to gently flatten the steep slope of the PSG film, a high-temperature heat treatment of about 1000° C., called reflow, is performed in a diffusion furnace.
以下ＭＯ８）ランジスタを例に用いて説明する。 The following explanation will be given using MO8) transistor as an example.
１０００℃程度の高温熱処理を行なうとＰＳＧ膜の段差
部での傾斜は緩やになるが、不純物原子がさらに拡散し
再分布するという問題点がある。不純物原子が再分布す
ることによる最も大きな問題点は、ＭＯＳトランジスタ
のソースおよびドレイン領域の不純物原子の横方向拡散
により実効チャネル長が短くなり、ゲートしきい値電圧
が低下する短チヤネル効果が発生することである。When high-temperature heat treatment of about 1000° C. is performed, the slope of the PSG film at the step portion becomes gentle, but there is a problem that impurity atoms are further diffused and redistributed. The biggest problem caused by the redistribution of impurity atoms is that the lateral diffusion of impurity atoms in the source and drain regions of MOS transistors shortens the effective channel length, causing a short channel effect that lowers the gate threshold voltage. That's true.
本発明の目的は、半導体集積回路装置の眉間絶縁膜およ
び表面保護膜のりフローにおいて、不純物原子の再分布
が発生しない方法を提供することにある。An object of the present invention is to provide a method in which redistribution of impurity atoms does not occur in the glabellar insulating film and surface protective film glue flow of a semiconductor integrated circuit device.
上記目的のため本発明においては、ＰＳＧ膜が波長２０
０ｎｍ以下の光を吸収するという特性を利用する。すな
わち波長２００ｎｍ以下のエキシマレーザ−光をＰＳＧ
膜に照射することにより加熱し、リフローを行ない急峻
な段差部の傾斜を緩やかに平坦化する。For the above purpose, in the present invention, the PSG film has a wavelength of 20
It utilizes the property of absorbing light of 0 nm or less. In other words, excimer laser light with a wavelength of 200 nm or less is used as PSG.
The film is heated by irradiation, and reflow is performed to gently flatten the steep slope of the step.
以下図面を用いて本発明の詳細な説明する。 The present invention will be described in detail below using the drawings.
第１図（ａ） （ｂ） （Ｃ）は本発明の実施例の各工
程におけるＭＯＳ）ランジスタの断面図を示したもので
ある。FIGS. 1(a), 1(b), and 1(c) show cross-sectional views of a MOS transistor at each step in an embodiment of the present invention.
まず第１図（ａ）に示すように、第１導電型の半導体基
板１０の表面に酸化性雰囲気中で厚さ４Ｑｎｍ程度の、
二酸化シリコン膜からなるゲート絶縁膜１２を形成する
。その後ＣＶＤ法（Ｃｈｅｍｉ ｃａ ｌ Ｖａｐｏ
ｒＤｅｐｏｓｉｔｉｏｎ）にて全面に多結晶シリコン膜
を５００ｎｍ程度の厚さで堆積し、フォトエツチング技
術を用いてゲート電極１４を形成する。さらにゲート電
極１４をマスクとして４Ｘ１０ｃｍ 程度のイオン注
入量で４オン注入することにより、第２導電型のソース
領域１６およびドレイン領域１８を形成する。次にリン
を３〜８ｗｔ％含有した厚さ５００ｎｍ程度のＰＳＧ膜
２膜上０ＶＤ法で全面に堆積し層間絶縁膜とする。First, as shown in FIG. 1(a), a film with a thickness of about 4 Qnm is deposited on the surface of a first conductivity type semiconductor substrate 10 in an oxidizing atmosphere.
A gate insulating film 12 made of a silicon dioxide film is formed. After that, CVD method (Chemical Vapo
A polycrystalline silicon film is deposited on the entire surface to a thickness of about 500 nm using a photoetching technique, and a gate electrode 14 is formed using a photoetching technique. Furthermore, a source region 16 and a drain region 18 of the second conductivity type are formed by implanting four ions at a dose of approximately 4×10 cm 2 using the gate electrode 14 as a mask. Next, it is deposited over the entire surface of two PSG films containing 3 to 8 wt % of phosphorus and having a thickness of about 500 nm by a 0VD method to form an interlayer insulating film.
次に第１図（ｂ）に示すように、エキシマレーザ−光２
２として例えばアルゴンフロライド（ＡｒＦ）エキシマ
レーザ−光（波長１９３ｎｍ）を、例えば光強度１０〜
２００ ｍ Ｊ／ＣｒＡで全面に照射する。Next, as shown in FIG. 1(b), the excimer laser beam 2
As 2, for example, argon fluoride (ArF) excimer laser light (wavelength 193 nm) is used, for example, with a light intensity of 10~
The entire surface is irradiated with 200 m J/CrA.
第２図にＰＳＧ膜における波長と透過率の関係のグラフ
を示す。第２図で明らかなように２００１ｍ以下の波長
は、ＰＳＧ膜に吸収される。従ってＰＳＧ膜は加熱され
リフローが行なわれ段差部２１の傾斜が緩やかになり平
坦化される。この時ル
ＰＳＧ膜２膜上０差部２１は、平台部２６に比較して、
ＰＳＧ膜が厚いこと、およびＰＳＧ膜２℃の表面反射光
によりＰＳＧ膜２０単位面積当りのエキシマレーザ−光
２２吸収量が多いことにより。FIG. 2 shows a graph of the relationship between wavelength and transmittance in a PSG film. As is clear from FIG. 2, wavelengths of 2001 m or less are absorbed by the PSG film. Therefore, the PSG film is heated and reflowed, and the slope of the stepped portion 21 is made gentler and flattened. At this time, the zero difference part 21 on the PSG film 2 is compared to the flat part 26,
This is because the PSG film is thick and the amount of excimer laser light 22 absorbed per unit area of the PSG film is large due to the light reflected from the surface of the PSG film at 2°C.
段差部２１は平坦部２６と比べるとより一層加熱され、
より一層リフローが進行する。またエキシマレーザ−光
はほとんどＰＳＧ膜に吸収されるためＰＳＧ膜の下層ま
でエキシマレーザ−光は到達しない。The stepped portion 21 is heated more than the flat portion 26,
Reflow progresses further. Furthermore, since most of the excimer laser light is absorbed by the PSG film, the excimer laser light does not reach the lower layer of the PSG film.
次に第１図（Ｃ）に示すように、フォトエツチング技術
を用いてコンタクト窓２゛４を形成し、真空蒸着法・ス
パッタリング法等を用いて全面にアルミ ′ニウム膜を
形成し、フォトエツチング技術を用いて配線金属膜２６
を形成する。Next, as shown in FIG. 1(C), a contact window 2-4 is formed using a photo-etching technique, an aluminum film is formed on the entire surface using a vacuum evaporation method, a sputtering method, etc., and then a photo-etching process is performed. Wiring metal film 26 using technology
form.
以上ＭＯ８）ランジスタの眉間絶縁膜を例として説明し
てきたが、表面保護膜・バイポーラトランジスタ等にも
エキシマレーザ−光を用いるＰＳＧ膜のりフローは応用
可能である。。Although the explanation has been given above using the glabella insulating film of MO8) transistor as an example, the PSG film bonding flow using excimer laser light can also be applied to surface protection films, bipolar transistors, etc. .
またリフロ一温度を１００〜２００℃下げる目的でポロ
ンを添加したＢＰＳＧ膜が用いられるが、とのＢＰＳＧ
膜を層間絶縁膜や表面保護膜として用いた場合でも、エ
キシマレーザ−光の照射によるリフローを行なうことが
できる。In addition, a BPSG film doped with poron is used to lower the reflow temperature by 100 to 200°C.
Even when the film is used as an interlayer insulating film or a surface protection film, reflow can be performed by irradiation with excimer laser light.
キシマレーザー光がＰＳＧ膜に吸収されＰＳＧ膜下層の
半導体集積回路装置まで透過しないためＰＳＧ膜下層に
作製された半導体集積回路装置の特性変化を最小限に押
える方法として応用可能である。Since the Kisima laser light is absorbed by the PSG film and does not pass through to the semiconductor integrated circuit device below the PSG film, this method can be applied as a method for minimizing changes in the characteristics of the semiconductor integrated circuit device fabricated below the PSG film.
以上ＡｒＦエキシマレーザ−を用いた例で説明してきた
が波長２００ｎｍ以下のエキシマレーザ−光であればＰ
ＳＧ膜に吸収されるのでｓＦ２エキシマレーザ−（波長
１５７ ｎｍ）、Ｘｅ２−１−１＋−シマレーザー（波
長１７２ｎｍ）、ＡｒＣｌエキシマレーザ−（波長１７
５ｎｍ）等でもＰＳＧ膜のりフローを行なうことができ
る。The above has been explained using an example using an ArF excimer laser, but if the excimer laser light has a wavelength of 200 nm or less, P
Because it is absorbed by the SG film, sF2 excimer laser (wavelength 157 nm), Xe2-1-1+-simmer laser (wavelength 172 nm), ArCl excimer laser (wavelength 17 nm)
5 nm) etc., PSG film deposition flow can be performed.
以上の説明で明らかなように、ＰＳＧ膜にエキシマレー
ザー光を照射することにより加熱されＰＳＧ膜がリフロ
ーされ段差部の傾斜が緩やかに平坦化される。エキシマ
レーザ−光はＰＳＧ膜−に吸収されるため、エキシマレ
ーザ−光はＰＳＧ膜下層の半導体基板に到達せず不純物
原子の再拡散による再分布は発生せず信頼性の高い半導
体集積回路装置を得ることができる。As is clear from the above description, the PSG film is heated by being irradiated with excimer laser light, the PSG film is reflowed, and the slope of the stepped portion is gently flattened. Since the excimer laser light is absorbed by the PSG film, the excimer laser light does not reach the semiconductor substrate underlying the PSG film, and redistribution due to re-diffusion of impurity atoms does not occur, resulting in a highly reliable semiconductor integrated circuit device. Obtainable.
第１図（ａ） （ｂ） （Ｃ）は本発明の詳細な説明す
るためのＭＯＳ）う／ジスタの各工程における断面図、
第２図はＰＳＧ膜における波長と透過率の関係を示すグ
ラフである。
２０・・・・・・ＰＳＧ膜、
２２・・・・・・エキシマレーザ−光。
第１図FIGS. 1(a), 1(b), and 1(C) are cross-sectional views at each step of the MOS transistor for detailed explanation of the present invention;
FIG. 2 is a graph showing the relationship between wavelength and transmittance in a PSG film. 20...PSG film, 22...Excimer laser light. Figure 1
Claims (2)
した酸化シリコン膜の表面段差を緩やかに平坦化を行な
う方法において、波長２００ｎｍ以下のエキシマレーザ
ー光を前記リンを添加した酸化シリコン膜の全面に照射
することにより加熱し、このリンを添加した酸化シリコ
ン膜の表面段差を緩やかに平坦化を行なうことを特徴と
する半導体集積回路装置の製造方法。(1) In a method of gently flattening the surface steps of a phosphorus-doped silicon oxide film used as an interlayer insulating film and a protective film, excimer laser light with a wavelength of 200 nm or less is applied to the entire surface of the phosphorus-doped silicon oxide film. 1. A method of manufacturing a semiconductor integrated circuit device, which comprises heating by irradiation to gently flatten surface steps of a silicon oxide film doped with phosphorus.
キシマレーザー光を用いたことを特徴とする特許請求の
範囲第１項記載の半導体集積回路装置の製造方法。(2) The method for manufacturing a semiconductor integrated circuit device according to claim 1, characterized in that argon fluoride excimer laser light is used as the excimer laser light.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27641986A JPS63131545A (en) | 1986-11-21 | 1986-11-21 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27641986A JPS63131545A (en) | 1986-11-21 | 1986-11-21 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63131545A true JPS63131545A (en) | 1988-06-03 |
Family
ID=17569145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27641986A Pending JPS63131545A (en) | 1986-11-21 | 1986-11-21 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63131545A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1139404A1 (en) * | 2000-03-31 | 2001-10-04 | Applied Materials, Inc. | Low thermal budget solution for PMD application using SACVD layer |
-
1986
- 1986-11-21 JP JP27641986A patent/JPS63131545A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1139404A1 (en) * | 2000-03-31 | 2001-10-04 | Applied Materials, Inc. | Low thermal budget solution for PMD application using SACVD layer |
| US6703321B2 (en) | 2000-03-31 | 2004-03-09 | Applied Materials Inc. | Low thermal budget solution for PMD application using sacvd layer |
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