JPS63131068A - Speed detection circuit - Google Patents

Abstract

PURPOSE:To enable the impartment of general-purpose applicability, by comparing revolutions detected with a set allowable limit value within a specified time as predetermined to detect abnormality of a rotor according to the results of comparison. CONSTITUTION:When a speed detection circuit is put into operation, data from a data bus 22 is set on a register 2 by an instruction pulse 23. At the same time, a counter 1 and a frequency division circuit 4 are brought to an initial state by a clear signal 38 from an OR circuit 11 while a register 5 gets valid by an input of the pulse 23. When counts 26 from the counter 1 are smaller than a set value from the register 2 or not equal thereto until a pulse signal 28 from the circuit 4 goes to a high level, a comparison signal 31 outputted from a comparator 3 is '1'. Here, as the signal 28 from the circuit 4 to be inputted into an AND circuit 7 and a delay signal 33 via a register 5 and a delay circuit 6 are both valid, the results 34 of computation from the AND circuit 7 become valid and are inputted into a register 8 to make a deceleration detection signal 35 from the register 8 valid.

Description

TECHNICAL FIELD The present invention relates to a speed detection circuit, and more particularly to a speed detection circuit that detects an abnormal state of a rotating body such as a fan that rotates at high speed.

Conventional technology Conventionally, this type of speed detection circuit detects deceleration of the fan by comparing the pulses of the motor that drives the fan with the oscillation pulses from the CRR oscillation circuit. In other words, the minimum value of the rotational speed, which is the deceleration limit, was fixed.

Furthermore, it has not been possible to vary the oscillation pulses from the CRR oscillation circuit using a microprocessor, and it has been impossible to control detection of deceleration using a microprocessor.

In such conventional speed detection circuits, the deceleration limit value is fixed by the CRR oscillation circuit, and the deceleration limit value cannot be easily set because the Cr (oscillation circuit operates asynchronously with the microprocessor and cannot be controlled by the microprocessor. It has the disadvantage that it cannot be changed to the current state.It also has the disadvantage that it cannot be synchronized with the microprocessor, making it difficult to use when building a system.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and it is possible to synchronize with a microprocessor and easily change the permissible limit value of the rotation speed of a rotating body. The purpose of the present invention is to provide a speed detection circuit that can be constructed and has general versatility.

Composition of the Invention The speed detection circuit according to the present invention includes: a detection means for detecting the rotation speed of a rotating body; a setting means capable of arbitrarily setting an allowable limit value of the rotation speed of the rotary body according to an external instruction; The number of rotations detected by the detection means within a predetermined period of time is compared with the allowable limit value set by the setting means, and an abnormality in the number of rotations of the rotating body is detected according to the comparison result. It is characterized by having an abnormality detection means.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, one embodiment of the present invention includes a counter 1 that detects the number of rotations of a fan 12, and a register 2 that stores a set value of the minimum number of rotations as a deceleration limit, which is a deceleration detection range.
, a comparator 3 that compares the count value of the counter 1 and the set value of the register 2, a frequency dividing circuit 4 that divides the frequency of the system clock 24, a register 5 that stores the instruction pulse 23, a delay circuit 6, and It is composed of a circuit 7.10, a register 8 for storing a detection result of deceleration, and an OR circuit 9.11.

The counter 1 receives a pulse signal 21 indicating the number of rotations of the fan 12.
is received, the number of rotations of the fan 12 is counted, and the count value 26 is outputted to the comparator 3 (8).

The comparator 3 compares the count value 26 of the counter 1 inputted to A and the set value 27 of the register 2 inputted to B, and sets the comparison signal 29 outputted to the OR circuit 9 as "1" when A=8. When A>8, the comparison signal 30 output to the OR circuit 9 is set to "1", and when A<8, the comparison signal 30 is output to the AND circuit 7.
It is assumed that the comparison signal 31 outputted to is "1".

The frequency dividing circuit 4 is composed of a combination of counters,
A system clock 24 is input, and the frequency of this system clock 24 is divided to output a pulse signal 28 with a frequency of 112T to the AND circuits 7 and 10.

A command pulse 23 indicating whether the speed detection circuit is operating or not is input to the register 5 and stored therein. This stored command pulse 23 is stored in register 5.
The signal is outputted to the delay circuit 6 as an output signal @32, delayed by the delay circuit 6, and outputted as a delayed signal 33 to the AND circuit 7. This delay is for timing the input of the comparison signal 31 of the comparator 3 to the AND circuit 7.

AND circuit 7 receives comparison signal 31 from comparator 3,
The pulse signal 28 having a period of 2T from the frequency dividing circuit 4 and the delay signal 33 from the delay circuit 6 are ANDed, and the result (deceleration detection result) 34 is outputted to the register 8. When the calculation result 34 from the AND circuit 7 becomes valid, the register 8 notifies the outside via the deceleration detection signal 35 that the calculation result 34 has become valid. That is, the register 8 notifies the outside that deceleration has been detected.

The OR circuit 9 is the comparison signal 29.30 from the comparator 3.
The logical sum operation is performed and the output signal @36 is outputted to the AND circuit 10. In the AND circuit 10, this output signal 36
A logical AND operation is performed between and the pulse signal 28 having a period of 2T from the frequency dividing circuit 4, and the result of the operation is outputted to the OR circuit 11 as an output signal @37.

OR circuit 11 includes command pulse 23 and system reset 2
5 is input, a logical sum operation is performed between these signals and the output signal 37 from the AND circuit 10, and the result of the operation is outputted to the counter 1 and the frequency dividing circuit 4 as a clear signal 38. That is, when operating this speed detection circuit,
The counter 1 and the frequency dividing circuit 4 are cleared and initialized when the operation is stopped by the system reset 25 and when no deceleration is detected as a result of the operation of the speed detection circuit.

When operating this speed detection circuit, first register 2 is set to data bus 2 by software using command pulse 23.
Set the data from 2, that is, the minimum value of the rotation speed that is the deceleration limit. At this time, at the same time, the counter 1 and the frequency divider circuit 4 are put into an initial state by the clear signal 38 from the OR circuit 11 to which the command pulse 23 is input, and the register 5 is enabled by the input of the command pulse 23.

There is one hour until the pulse signal 28 with a period of 2T from the frequency dividing circuit 4 becomes high level, so during that time the count value 26 from the counter 1 changes to the set value 27 from the register.
is not equal to and does not become larger (that is, when the count (direction 26 is smaller than the set value 27), the comparison signal 31 output from the comparator 3 is "
1”.

When this comparison signal @31 becomes "1", the pulse signal 28 from the frequency divider circuit 4 which is input to the AND circuit 7 and the i! ! Extension angle signal 33
Since both are valid, the calculation result 34 from the AND circuit 7 becomes valid, the calculation result 34 is input to the register 8, and the deceleration detection signal 35 from the register 8 is made valid.

In other words, the register 8 notifies the outside that the fan has been decelerated to a minimum value or less.

In addition, if the count from the counter 1 (direct 26 becomes greater than or equal to the set value 27 from the register 2) until the pulse signal 28 from the frequency divider circuit 4 becomes high level, the OR circuit 9 outputs the AND circuit. When the output signal 36 to the AND circuit 10 becomes valid and the pulse signal 28 from the frequency divider circuit 4 becomes high level in the AND circuit 10, the output signal 37 from the AND circuit 10 to the OR circuit 11 becomes valid. The OR circuit 11 validates the clear signal 38 and returns the counter 1 and the frequency divider circuit 4 to their initial values.

In this way, the minimum set value 27 of the rotation speed that is the limit of deceleration stored in the register 2 can be arbitrarily set using the data bus 22 and the command pulse 23, and the rotation speed of the fan 12 can be controlled within a predetermined time T. By notifying the outside via the register 8 of deceleration detection when the count value 26 of the counting counter 1 is smaller than the set minimum rotation speed, it is possible to notify the microprocessor by an interrupt or the like. , it is also possible to output it as an alarm to the outside of the device. Furthermore, the minimum rotation speed to be detected can be arbitrarily set by the microprocessor.
It can provide versatility.

By being controllable by a microprocessor, detection of deceleration is stopped when detection of deceleration is unnecessary,
If necessary, deceleration can be detected, and the minimum rotational speed value, which is the deceleration limit, can be freely changed.

In the above, the detection of deceleration of the fan 12 has been described, but it is clear that the present invention can be widely applied to detecting the deceleration of rotating bodies in general, and also can detect overspeed. Furthermore, in the case of over speed, the permissible limit value may be set to the maximum rotation speed, and an abnormality notification may be issued accordingly when the comparison result of the comparator 3 is A>8.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described above, within a predetermined period of time, the detected rotational speed of the rotating body and the allowable rotational speed of the rotating body arbitrarily set according to an external instruction are determined. It is possible to synchronize with the microprocessor by comparing the limit value and detecting an abnormality in the rotating body according to the comparison result, and setting the allowable limit value of the rotation speed of the rotating body in advance. It has the advantage that it can be easily changed and has versatility.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. Explanation of symbols of main parts 1...Counter 2.5.8・・・Register 3...Comparator 4... Frequency divider circuit

Claims (1)

[Claims] a detection means for detecting the rotation speed of a rotating body; a setting means capable of arbitrarily setting a permissible limit value of the rotation speed of the rotary body according to an external instruction; and detection by the detection means within a predetermined time period. and an abnormality detection means for comparing the rotation speed determined by the rotation speed with the permissible limit value set by the setting means and detecting an abnormality in the rotation speed of the rotating body according to the comparison result. speed detection circuit.