JPS63129874U - - Google Patents

Info

Publication number
JPS63129874U
JPS63129874U JP2313587U JP2313587U JPS63129874U JP S63129874 U JPS63129874 U JP S63129874U JP 2313587 U JP2313587 U JP 2313587U JP 2313587 U JP2313587 U JP 2313587U JP S63129874 U JPS63129874 U JP S63129874U
Authority
JP
Japan
Prior art keywords
connector
hybrid
terminals
terminal connected
contact pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2313587U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2313587U priority Critical patent/JPS63129874U/ja
Publication of JPS63129874U publication Critical patent/JPS63129874U/ja
Pending legal-status Critical Current

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Landscapes

  • Measuring Leads Or Probes (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の第１の実施例を示す平面図、
第２図ａ，ｂはそれぞれ本考案の第２の実施例を
示す平面図及び側面図である。 １……プリント基板、２……ＩＣコネクタ、３
……接続コネクタ、４，４ａ……変換ブロツク、
５……プリント配線、２１……ピン、４１ａ，４
１ｂ……端子、４２，４２ａ……接続線、４３…
…コネクタ部、４４……接続変換部、４５ａ，４
５ｂ……ピン。 FIG. 1 is a plan view showing a first embodiment of the present invention;
FIGS. 2a and 2b are a plan view and a side view, respectively, showing a second embodiment of the present invention. 1...Printed circuit board, 2...IC connector, 3
... Connection connector, 4, 4a ... Conversion block,
5...Printed wiring, 21...Pin, 41a, 4
1b...terminal, 42, 42a...connection line, 43...
...Connector part, 44...Connection conversion part, 45a, 4
5b...Pin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プリント基板上に、複数のピンを備え混成ＩＣ
を装着するためのＩＣコネクタと、複数のコンタ
クトピンを備え試験回路と接続するための接続コ
ネクタと、前記ＩＣコネクタの各ピンにそれぞれ
接続する第１の端子と前記各コンタクトピンにそ
れぞれ接続する第２の端子とこれら第１及び第２
の端子間を予め設定された接続にする接続換え可
能な接続線とを備えた変換ブロツクとを有するこ
とを特徴とする混成ＩＣ選別治具。 Hybrid IC with multiple pins on a printed circuit board
an IC connector for mounting an IC connector, a connecting connector having a plurality of contact pins for connecting to a test circuit, a first terminal connected to each pin of the IC connector, and a first terminal connected to each of the contact pins, respectively. 2 terminals and these first and second terminals
1. A hybrid IC sorting jig, comprising: a conversion block having a connection line that can be reconnected to make a preset connection between the terminals of the hybrid IC sorting jig.
JP2313587U 1987-02-18 1987-02-18 Pending JPS63129874U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2313587U JPS63129874U (en) 1987-02-18 1987-02-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2313587U JPS63129874U (en) 1987-02-18 1987-02-18

Publications (1)

Publication Number Publication Date
JPS63129874U true JPS63129874U (en) 1988-08-24

Family

ID=30821176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2313587U Pending JPS63129874U (en) 1987-02-18 1987-02-18

Country Status (1)

Country Link
JP (1) JPS63129874U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5834375A (en) * 1981-08-13 1983-02-28 エンバイロシメンタル・プロセツシング・インコ−ポレイテツド Burn-in testing method for integrated circuit device and its device
JPS6134482A (en) * 1984-07-26 1986-02-18 Toshiba Corp Burn-in board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5834375A (en) * 1981-08-13 1983-02-28 エンバイロシメンタル・プロセツシング・インコ−ポレイテツド Burn-in testing method for integrated circuit device and its device
JPS6134482A (en) * 1984-07-26 1986-02-18 Toshiba Corp Burn-in board

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