JPS6312979A - Function test device - Google Patents

Abstract

PURPOSE:To improve generating efficiency of a test data by providing a data output means, series transfer means, identification signal generation means, test data output means, check means and answer data input means. CONSTITUTION:The data output means 1 which outputs the test data in series corresponding to each test terminal 71-7N, the series transfer means 2 connected to the output of the means 1 and the identification signal generation means 3 which outputs the identification signal for the purpose of each test data outputted from the means 1, are provided in the device. Further, the test data output means 41-4N are provided for each test terminal which outputs the test data to the corresponding test terminal- the test data which corresponds to the identification signal on the means 2 answering the identification signal; and answering data input means 61-6N are provided for each test terminal which inputs the answering data of a subject to be tested to the check means 5 - the answering data of the subject to be tested which appears in the test terminal corresponding to the identification signal answering the identification signal. Thus the test of the combination circuit of the subject to be tested is executed. The means 1 requires no need of outputting the unnecessary data, the generation efficiency is thereby improved.

Description

[Detailed Description of the Invention] [Summary] A test in which test data to be applied to each test terminal of a test object provided in a functional test device is generated in series, and the serial data is output to each test terminal. Data is outputted to a corresponding test terminal using the test data identification signal, and response data returned from the corresponding combinational circuit of the test object is inputted from the test terminal to the check circuit using the corresponding identification signal. This makes it possible to unify the circuit system from the serial test data generation means to the means for separating each test data, and to improve the efficiency of test data generation.

[Industrial application field]

The present invention relates to a functional testing device, and more particularly, to a functional testing device that pursues the benefits of serializing test data.

Information processing devices, etc. are constructed using multiple LSI mounting boards, but these boards are
It is necessary to test whether the semiconductor logic circuit system formed in I operates as designed. A functional test system has conventionally been used as one of the means for this purpose. Although this test system and awl can perform their intended functions from a structural standpoint,
From other viewpoints, it is not necessarily satisfactory, and there is still room for improvement.

[Conventional technology]

A combinational circuit test system for a test object in a conventional functional test system is configured as follows.

Primary input/input used for testing the logic circuit of the device under test
In order to provide the required test data pattern to the primary out (Pi/p□) bin, a switch on/off control memory 50, a test data input/output memory 52 and a comparison inhibit memory 54 are provided as shown in FIG.
In addition, a driver 56 is connected to the output of the memory 50, and a switch on/off memory 5 is connected between the output of the driver 56 and the P L / P O bin 60.
A switch 58 controlled on/off by an output of 0, an EOR 62 connected to the output of the memory 52 and the P i / P o pin 60, and a comparison inhibit memory 54 and an EOR 62
An AND gate 64 connected to the output of each Pi/P
It is provided for each o pin. During testing, P i / p is determined depending on the combinational circuit to be tested.
A predetermined test data pattern for the O-bin is applied from memory 50 via the driver 56° switch 58, and the response data from the combinational circuit is applied to the corresponding P i / P o pin and the EOR 62, AND gate. 64 to the check circuit for testing.

[Problem that the invention seeks to solve]

As is clear from the above, depending on the combinational circuit to be tested, it is necessary to store even unnecessary data in the test data input/output memory 50, so that it is possible to avoid poor memory usage efficiency. do not have. At the same time, the comparison prohibition memory 54 is essential. Moreover, the wiring from the test data input/output memo 1J50 to the driver and the wiring from the comparison prohibition memory 54 to the AND gate 64 are connected to each Pi/P.
Since it is necessary for each o pin, the above-mentioned amount of wiring was not a problem when the number of pins on the device under test was relatively small, but as has recently been the case, when the number of pins on the device under test is several thousand pins. As the number of pins increases, the above-mentioned wiring problems become more prevalent.

The present invention was created in view of the above problems, and an object of the present invention is to provide a function test system that improves the efficiency of generating test data and significantly reduces the amount of wiring.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. As is clear from this figure, the present invention includes a data output means 1 for serially outputting test data corresponding to each test terminal;
a serial transfer means 2 connected to the output of the data output means 1; an identification signal generation means 3 for outputting an identification signal for each test data output from the data output means 1; Test data output means 41 for each test terminal that outputs test data corresponding to the identification signal to the corresponding test terminal; and test object response data appearing at the test terminal corresponding to the identification signal in response to the identification signal. Response data input means 6 for each test terminal inputs the response data into the checking means 5
1...6N are provided to perform tests on the combinational circuit of the test object.

[For production]

Only the test data to be output to each of the necessary test terminals used for testing the test object is serially output from the data output means 1, and among the serial test data, the test data corresponding to the test terminal is output by the identification signal. It will be extracted and output to the relevant test terminal. Therefore, since the data output means 1 does not need to output unnecessary data, its generation efficiency is improved. Further, since a single wiring can be used from the data output means 1 to each test data output means, no problem occurs even if the number of terminals increases.

The response data that appears at the test terminal as the test object response to the test data given to the test object as described above is input to the checking means 5 by the input means corresponding to the test terminal, so that it is not considered as output data. A similar method can be used to prevent comparison using the conventional memory 54 (Fig. 3).
does not require.

〔Example〕

FIG. 2 shows an embodiment of the invention. This embodiment is an example in which a test object can be tested when the test object is made of ECL.

In the figure, lO indicates a functional test system. Reference numeral 12 denotes a serial data pattern generator, which is composed of, for example, a memory, and outputs test data of the combinational circuit of the test object bit serially (this part corresponds to data output means 1 in Fig. 1). ) along with the address for each bit. A decoder 14 decodes the address output from the serial data pattern generator 12. The system from the address generation section of the serial data pattern generator 12 to the decoder 14 corresponds to the identification signal generation means 3 in FIG. 161...
・16+...is a serial data pattern generator
Decoder 14 for serial test data from I2
This is a flip-flop that latches in response to bit &h separate signals from the . The output of the serial test data bit generator of the scan data pattern generator 12 and each flip-flop are connected by one transfer path 2.

The output of each flip-flop is connected to a corresponding primary in/primary out pin via a corresponding driver. The system from this flip-flop to the primary in/primary out pin corresponds to the test data output means in FIG. These primary in/primary out pins 20. . . 201 . . . are provided as many as the number of pins provided for testing the combinational circuit provided on the test object 21.

The output of each primary in/primary out pin is configured to be applied to the check circuit 5 via a corresponding AND gate. These AND gates are referenced by reference numbers 221 . . . 221 . Also, and gate 22. . . . 221 . . . each include a decoder used to cause the test data to be sent to the corresponding flip-flop in order to output the test data to the corresponding decode output of the decoder 14, that is, the primary in/primary out pin. Output is connected. The system from this primary in/primary out pin to the check circuit corresponds to the response data input means in FIG.

24 is a high-speed pattern generation/check circuit similar to the conventional one;
This is the primary in/primary out pin 201
. . . Provided for high-speed testing of a partial combination circuit of the test object via a desired pin of the 2ONs.

Further, 26 is a sequential circuit test circuit system, the configuration of which is the same as the conventional one. This test circuit system consists of scan address pin 28.
Scan in pin 30. It has scan-out pins 32, which are connected to the corresponding female connectors 34, 36 of the test object.
．． 38 and used for the test. The female connector 34 is connected to a decoder (not shown) provided on the device under test 21, and the female connector 36 is connected to inputs of each component constituting a sequential circuit (not shown) of the device under test 21. The connector 38 is connected to each component output of a sequential circuit (not shown). Each of the above-mentioned components is configured to be addressed by a corresponding decode output of a decoder (not shown).

According to the functional test system configured in this way, test data is output from the data pattern generator 12 when testing a combinational circuit in the object under test, but the test data is not necessary for the combinational circuit. Only those that are considered as such are sufficient. Furthermore, the data to the test terminals is given only to the part to be tested at that time, and there is no need to have unnecessary data as in the conventional case, which improves memory usage efficiency. Since the test data is supplied to each flip-flop via a single transfer path 2, which is shared by each pin, an increase in the number of pins does not cause any increase in the bulk of the transfer path. .

Each test data of the serial test data transferred via the transfer path is set in a flip-flop specified by the decoding output of the decoder 14 and input to the device under test 21 via the driver, and each of the response data is is sent to the check circuit 5 via the corresponding primary in/primary out pin and AND gate. The check circuit 5 determines whether the combinational circuit is good or bad based on the relationship with previously prepared data. In this way, there is no need for conventional input permission/inhibition means for inputting the response data.

In addition to this, the high-speed pattern generation/check circuit 24 can be used to perform tests similar to conventional ones. Further, the sequential circuit test circuit system 26 can be used to input and output test data for sequential circuits.

Note that the present invention can be applied even if the primary in pin and primary out pin are separate. In addition, if the test object is composed of TTL, in addition to the main configuration described above, it is necessary to provide a switch at the output of each driver and a control means for turning on/off this switch. .

〔Effect of the invention〕

As described above, according to the present invention, effects such as improvement in test data generation efficiency and avoidance of an increase in hardware due to an increase in the number of pins of a test object can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing related parts of a conventional system to the present invention. 1 and 2, 1 is a data generation means, 2 is a serial transfer means, 3 is an identification signal generation means, 41.42 is a test data output means, 61.
62... is a response data input means. Edge 4-Principle of invention diagram Figure 1

Claims (1)

[Claims] A plurality of test terminals (7_1...7
Data output means (1) for serially outputting test data corresponding to each test terminal in a functional test device having a
, serial transfer means (2) connected to the output of the data output means (1), and identification signal generation means (3) for outputting an identification signal for each test data output from the data output means (1). and test data output means (4_) for each combinational circuit test terminal that outputs test data corresponding to the identification signal on the serial transfer means (2) to the corresponding test terminal in response to the identification signal.
1...4_N) and input means for each combinational circuit test terminal for inputting into the checking means (5) the test object response data appearing at the combinational circuit test terminal corresponding to the identification signal in response to the identification signal. (6_1...6_N) is provided,
A functional test device characterized in that its test function can be connected to some test terminals that require high-speed testing.