JPS63129684A - Manufacture of semiconductor light emitting device - Google Patents

Manufacture of semiconductor light emitting device

Info

Publication number
JPS63129684A
JPS63129684A JP27531486A JP27531486A JPS63129684A JP S63129684 A JPS63129684 A JP S63129684A JP 27531486 A JP27531486 A JP 27531486A JP 27531486 A JP27531486 A JP 27531486A JP S63129684 A JPS63129684 A JP S63129684A
Authority
JP
Japan
Prior art keywords
compound semiconductor
layer
resistance layer
high resistance
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27531486A
Other languages
Japanese (ja)
Inventor
Hiroshi Ishikawa
浩 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP27531486A priority Critical patent/JPS63129684A/en
Publication of JPS63129684A publication Critical patent/JPS63129684A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make a high resistance layer good quality and to form a good current blocking structure by growing a compound semiconductor high resistance layer on the flat ground of a one conductivity type compound semiconductor substrate. CONSTITUTION:Semiconductor layers which include a compound semiconductor high resistance layer 2 and a one conductivity type compound semiconductor impurity supply layer 3 are formed on a one conductivity type compound semiconductor substrate 1. Stripes are formed by mesa etching from the surface of the semiconductor layers reaching to the high resistance layer 2. Then, compound semiconductor buried layers 8, 9 are formed on both sides of the stripes, an impurity is diffused from the impurity supply layer 3 to the high resistance layer 2 and selectively made conductive and electrodes 11, 12 are provided by forming a one conductivity type made conductive region 10. By this process, the good quality high resistance layer 2 is obtained since the ground is flat and a good current blocking structure wherein almost no leakage current is generated can be formed.

Description

【発明の詳細な説明】 〔概要〕 本発明は、半導体発光装置の製造方法に於いて、一導電
型化合物半導体基板上に化合物半導体高抵抗層及び一導
電型化合物半導体不純物供給層など所要半導体層を形成
し、ストライプ状になされた前記一導電型化合物半導体
不純物供給層から前記化合物半導体高抵抗層に不純物を
拡散して選択的に導電化することに依り、良質の化合物
半導体高抵抗層からなる埋め込み型電流阻止構造を形成
できるようにし、高速且つ高出力の半導体発光装置を得
られるようにしている。
[Detailed Description of the Invention] [Summary] The present invention provides a method for manufacturing a semiconductor light emitting device, in which required semiconductor layers such as a compound semiconductor high resistance layer and a one conductivity type compound semiconductor impurity supply layer are formed on a one conductivity type compound semiconductor substrate. A high-quality compound semiconductor high-resistance layer is formed by forming a stripe-shaped compound semiconductor impurity supply layer of one conductivity type and diffusing impurities into the compound semiconductor high-resistance layer to selectively make the layer conductive. A buried current blocking structure can be formed, and a high speed and high output semiconductor light emitting device can be obtained.

〔産業上の利用分野〕[Industrial application field]

本発明は、高抵抗層からなる埋め込み型電流阻止構造を
有する半導体発光装置を製造する方法の改良に関する。
The present invention relates to an improvement in a method for manufacturing a semiconductor light emitting device having a buried current blocking structure made of a high resistance layer.

〔従来の技術〕[Conventional technology]

通常、半導体レーザに於いては、光の閉じ込めと共に電
流の閉じ込めを行う必要があり、その電流の閉じ込めに
は、逆バイアス電圧を印加したpnp構造を利用するこ
とが行われている。
Normally, in a semiconductor laser, it is necessary to confine light as well as current, and a pnp structure to which a reverse bias voltage is applied is used to confine the current.

然しなから、これに依る電流の閉じ込めには限界があり
、リーク電流が流れることは避けられない、また、pn
接合に容量は付き物であるから、高速変調する為に高周
波を印加すると、その容量を介してリークが発生する。
However, there is a limit to the confinement of current due to this, and the flow of leakage current is unavoidable.
Since capacitance is inherent in a junction, when a high frequency is applied for high-speed modulation, leakage occurs through the capacitance.

更にまた、高温になったり、大きな電流を流すとリーク
電流が増大するので、高出力を取り出すことができない
等の欠点がある。
Furthermore, when the temperature rises or a large current flows, the leakage current increases, so there is a drawback that high output cannot be obtained.

このような欠点を解消する為、所望の電流路以外の部分
に高抵抗層を埋め込む構成の半導体レーザが実現されて
いる。
In order to eliminate such drawbacks, semiconductor lasers have been realized in which a high resistance layer is embedded in a portion other than the desired current path.

第5図は高抵抗層からなる埋め込み型電流阻止構造を有
する従来の半導体レーザを説明する為の要部切断正面図
を表している。
FIG. 5 shows a cutaway front view of essential parts for explaining a conventional semiconductor laser having a buried current blocking structure made of a high resistance layer.

図に於いて、21はn型1nP基板、22はn型InP
クラッド層、23はInGaAsP活性層、24はp型
1nPクラッド層、25はInP高抵抗層、26は5t
o2膜、27はp側電極、28はn側電極をそれぞれ示
している。
In the figure, 21 is an n-type 1nP substrate, and 22 is an n-type InP substrate.
Cladding layer, 23 is InGaAsP active layer, 24 is p-type 1nP cladding layer, 25 is InP high resistance layer, 26 is 5T
o2 film, 27 indicates a p-side electrode, and 28 indicates an n-side electrode.

この従来例に於けるInP高抵抗層25はクロライド気
相エピタキシャル成長(chloride  vapo
r  phase  epitaxy:chlorid
e  VPE)法を適用して形成しである。
The InP high resistance layer 25 in this conventional example is grown by chloride vapor phase epitaxial growth (chloride vapor phase epitaxial growth).
r phase epitaxy: chlorid
It is formed by applying the VPE method.

第6図は半導体レーザの他の従来例を説明する為の要部
切断正面図であり、第5図に於いて用いた記号と同記号
は同部分を示すか或い、は同じ意味を持つものとする。
Figure 6 is a cutaway front view of essential parts for explaining another conventional example of a semiconductor laser, and symbols used in Figure 5 indicate the same parts or have the same meanings. shall be taken as a thing.

図に於いて、29はInP高抵抗層を示している。In the figure, 29 indicates an InP high resistance layer.

この従来例に於けるInP高抵抗層29は有機金属化学
気相堆積(metalorganicschemica
l  vapor  deposit i o n :
 MOCVD)法を適用して形成しである。
The InP high resistance layer 29 in this conventional example is formed by metalorganic chemical vapor deposition (metalorganic chemical vapor deposition).
l vapor deposit ion:
It is formed by applying the MOCVD method.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第5図について説明した半導体レーザでは、表面から基
板に達する溝を形成し、その溝の中に高抵抗層を形成し
なければならないが、現在、その技術が確立されていな
いので、満足な特性をもつものを再現性良く得ることが
できない。
In the semiconductor laser explained with reference to FIG. 5, it is necessary to form a groove reaching from the surface to the substrate and form a high-resistance layer in the groove, but the technology for this has not been established at present, so it is difficult to obtain satisfactory characteristics. cannot be obtained with good reproducibility.

第6図に見られる半導体レーザに於いては、第5図につ
いて説明したものと比較して高抵抗層の質は良好である
が、表面が平坦にならない旨の欠点がある。
In the semiconductor laser shown in FIG. 6, the quality of the high resistance layer is better than that described with reference to FIG. 5, but there is a drawback that the surface is not flat.

本発明は、良質の高抵抗層からなる埋め込み型電流阻止
構造を持つ半導体発光装置を提供しよう・とする。
The present invention aims to provide a semiconductor light emitting device having a buried current blocking structure made of a high-quality high-resistance layer.

〔問題点を解決するための手段〕[Means for solving problems]

従来、下地が平坦でありさえすれば、極めて良質の高抵
抗層を成長させる技術が確立されているので、この技術
を旨く利用すればリーク電流が少ない埋め込み型電流阻
止構造を得ることができる筈である。
Conventionally, a technology has been established to grow an extremely high-quality, high-resistance layer as long as the underlying layer is flat, so if this technology is effectively utilized, it should be possible to obtain a buried current blocking structure with low leakage current. It is.

そこで、本発明に依る半導体発光装置に於いては、一導
電型化合物半導体基板(例えばp型InP基板l)の上
に化合物半導体高抵抗層(例えばInP高抵抗層2)及
び一導電型化合物半導体不純物供給層(例えばp+型I
nP不純物供給層3)を含む諸半導体層を成長させる工
程と、次いで、該諸半導体層の表面から前記化合物半導
体高抵抗層に達するメサ・エッチングを施してストライ
プ部分を形成する工程と、次いで、該ストライプ部分の
両側に化合物半導体埋め込み層(例えばn型[nP埋め
込み層8及びp型InP埋め込み層9)を形成すると共
に前記一導電型化合物半導体不純物供給層から前記化合
物半導体高抵抗層に不純物を拡散して一導電型導電化領
域(例えばp型厚電化領域10)を形成する工程とが含
まれてなる構成になっている。
Therefore, in the semiconductor light emitting device according to the present invention, a compound semiconductor high resistance layer (for example, InP high resistance layer 2) and a one conductivity type compound semiconductor Impurity supply layer (e.g. p+ type I
a step of growing various semiconductor layers including the nP impurity supply layer 3), then a step of performing mesa etching from the surface of the various semiconductor layers to the compound semiconductor high resistance layer to form a stripe portion; Compound semiconductor buried layers (for example, n-type [nP buried layer 8 and p-type InP buried layer 9) are formed on both sides of the striped portion, and impurities are introduced into the compound semiconductor high resistance layer from the one conductivity type compound semiconductor impurity supply layer. The structure includes a step of diffusing to form a conductive region of one conductivity type (for example, a p-type thick conductive region 10).

〔作用〕[Effect]

前記手段を採ることに依り、前記高抵抗層は下地が平坦
であることから極めて良質なものが得られ、如何なる条
件の下に置かれてもリーク電流が殆ど発生しない良好な
電流阻止構造を形成することができ、且つ、前記高抵抗
層には、その上のストライプ状不純物供給層から不純物
が自動的に拡散されて選択的に導電化領域が形成されて
充分な電流を流すことができる。
By adopting the above-mentioned method, the high-resistance layer can be of extremely high quality because the underlying layer is flat, and a good current blocking structure is formed in which almost no leakage current occurs under any conditions. In addition, impurities are automatically diffused into the high resistance layer from the striped impurity supply layer thereon to selectively form conductive regions, thereby allowing a sufficient current to flow.

従って、作成された半導体発光装置に大電流を流して常
に高い出力を取り出すことが可能であり、また、pn接
合と違って容量は存在しないから、高周波を流してもリ
ークせず、従って、高速変調が可能である。
Therefore, it is possible to constantly output high output by passing a large current through the fabricated semiconductor light emitting device. Also, unlike a pn junction, there is no capacitance, so there is no leakage even when high frequencies are passed, and therefore high speed is possible. Modulation is possible.

〔実施例〕〔Example〕

第1図乃至第4図は本発明一実施例を解説する為の工程
要所に於ける半導体レーザの要部切断正面図を表してい
る。以下、これ等の図を参照しつつ説明する。
FIGS. 1 to 4 are cutaway front views of essential parts of a semiconductor laser at key points in the process for explaining one embodiment of the present invention. The explanation will be given below with reference to these figures.

第1図参照 (1)  例えば、MOCVD法を適用することに依り
、p型InP基板1の上に、 InP高抵抗層2、 p1型1nP不純物供給層3、 p−型1nPバフファ兼クラッド層4、InGaAsP
活性層5、 n型InPクラッド層6、 を成長させる。尚、この場合、MOCVD法の外、VP
E法或0は分子線エピタキシャル成長(molecul
ar  beam  epi taxy:MBE)法な
どの技術を適宜に選択して用いることができる。
Refer to FIG. 1 (1) For example, by applying the MOCVD method, an InP high resistance layer 2, a p1 type 1nP impurity supply layer 3, and a p-type 1nP buffer/cladding layer 4 are formed on the p-type InP substrate 1. , InGaAsP
An active layer 5 and an n-type InP cladding layer 6 are grown. In this case, in addition to the MOCVD method, VP
E method or 0 is molecular beam epitaxial growth (molecular beam epitaxial growth).
A technique such as the ar beam epi taxy (MBE) method can be appropriately selected and used.

この場合に於ける各半導体層の主要データを例示すると
次の通りである。
An example of the main data of each semiconductor layer in this case is as follows.

(a)  基板1について 不純物濃度: 5 X 10’?  (cm−”)(b
)  高抵抗層2について 厚さ:O,S  〔μm〕〜工 〔μm〕Ic)  不
純物供給層3について 厚さ:0.5Cμm〕 不純物濃度:2X1018(鐘−3〕 (d)  バッファ兼クラッド層4について厚さ:0.
5Cμm〕 不純物濃度: 5 X 10”  (cab−’)(e
)  活性層5について 厚さ:0.15(μm〕 (f)  クラッド層6について 厚さ=2 〔μm〕 不純物濃度: 5 X 10I7(cm−”E第2図参
照 (2)通常のフォト・リソグラフィ技術に於けるレジス
ト・プロセス及び適宜のエツチング法を適用することに
依り、表面から高抵抗層2に達するメサ・エッチングを
行ってストライプ部分を形成する。
(a) Impurity concentration for substrate 1: 5 x 10'? (cm-”)(b
) Thickness for high resistance layer 2: O, S [μm] ~ Technique [μm] Ic) Thickness for impurity supply layer 3: 0.5Cμm] Impurity concentration: 2×1018 (bell-3) (d) Buffer and cladding layer About 4 Thickness: 0.
5Cμm] Impurity concentration: 5 X 10” (cab-’) (e
) Thickness of active layer 5: 0.15 (μm) (f) Thickness of cladding layer 6 = 2 [μm] Impurity concentration: 5 × 10I7 (cm-”Esee Figure 2) (2) Normal photo By applying a resist process in lithography technology and an appropriate etching method, mesa etching is performed from the surface to reach the high resistance layer 2 to form a stripe portion.

第3図参照 (3)VPE法を適用することに依り、メサ状のストラ
イプ部分両側にn型1nP埋め込み層8及びp型1nP
埋め込み層9を形成する。
(3) By applying the VPE method, an n-type 1nP buried layer 8 and a p-type 1nP buried layer 8 are formed on both sides of the mesa-shaped stripe part.
A buried layer 9 is formed.

この時、例えば温度650(’C)の熱が加わる為、ス
トライプ状の不純物供給層3から高抵抗層2にp型不純
物が拡散され、p型温電化領域10が形成されるので、
ストライプ部分と基板1とは電気的に導通状態となる。
At this time, for example, heat at a temperature of 650 ('C) is applied, so p-type impurities are diffused from the striped impurity supply layer 3 to the high-resistance layer 2, and a p-type warm electrification region 10 is formed.
The stripe portion and the substrate 1 are electrically connected.

尚、p型温電化領域10に於ける不純物濃度は5X10
17(am −’ )程度である。
Incidentally, the impurity concentration in the p-type warm electrification region 10 is 5×10
It is about 17 (am-').

第4図参照 (4)  真空蒸着法を適用することに依り、p側電極
11及びn側電極12を形成する。
Refer to FIG. 4 (4) By applying a vacuum evaporation method, the p-side electrode 11 and the n-side electrode 12 are formed.

これ等電極11及び12の主要データを例示すると次の
通りである。
Examples of the main data of these electrodes 11 and 12 are as follows.

(al  電極11について 材料: A u G e / A u 厚さ:1000  (人)/3(μm)(b)  電極
12について 材料: T i / P t / A u厚さ:100
0(人)/1000(人〕/3〔μm〕 〔発明の効果〕 本発明に依る半導体発光装置の製造方法に於いては、一
導電型化合物半導体基板上に化合物半導体高抵抗層及び
一導電型化合物半導体不純物供給層など所要半導体層を
形成し、ストライプ状になされた前記一導電型化合物半
導体不純物供給層から前記化合物半導体高抵抗層に不純
物を拡散して選択的に導電化するようにしている。
(al Material for electrode 11: A u G e / A u thickness: 1000 (people) / 3 (μm) (b) Material for electrode 12: T i / P t / A u thickness: 100
0 (people)/1000 (people)/3 [μm] [Effects of the Invention] In the method for manufacturing a semiconductor light emitting device according to the present invention, a compound semiconductor high resistance layer and a one conductivity type compound semiconductor substrate are formed on a one conductivity type compound semiconductor substrate. A required semiconductor layer such as a type compound semiconductor impurity supply layer is formed, and impurities are diffused from the striped one conductivity type compound semiconductor impurity supply layer into the compound semiconductor high resistance layer to selectively make it conductive. There is.

前記構成を採ることに依り、前記高抵抗層は下地が平坦
であることから極めて良質なものが得られ、如何なる条
件の下に置かれてもリーク電流が殆ど発生しない良好な
電流阻止構造を形成することができ、且つ、前記高抵抗
層には、その上のストライプ状不純物供給層から不純物
が自動的に拡散されて選択的に導電化領域が形成されて
充分な電流を流すことができる。
By adopting the above structure, the high resistance layer has a flat base, so it can be of extremely high quality, and forms a good current blocking structure in which almost no leakage current occurs under any conditions. In addition, impurities are automatically diffused into the high resistance layer from the striped impurity supply layer thereon to selectively form conductive regions, thereby allowing a sufficient current to flow.

従って、作成された半導体発光装置に大電流を流して常
に高い出力を取り出すことが可能であり、また、pn接
合と違って容量は存在しないから、高周波を流してもリ
ークせず、従って、高速変調が可能である。
Therefore, it is possible to constantly output high output by passing a large current through the fabricated semiconductor light emitting device. Also, unlike a pn junction, there is no capacitance, so there is no leakage even when high frequencies are passed, and therefore high speed is possible. Modulation is possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第4図は本発明一実施例を説明する為の工程
要所に於ける半導体レーザの要部切断正面図、第5図及
び第6図は従来例の要部切断正面図をそれぞれ表してい
る。 図に於いて、1は基板、2は高抵抗層、3は不純物供給
層、4はバッファ兼クラッド層、5は活性層、6はクラ
ッド層、8及び9は埋め込み層、10は導電化領域、1
1及び12は電極をそれぞれ示している。 特許出願人   富士通株式会社 代理人弁理士  相 谷 昭 司 代理人弁理士  渡 邊 弘 − 第1図 第2図 第3図 第4図 従来例の要部切断正面図 第5図
1 to 4 are cut-away front views of essential parts of a semiconductor laser at important process points for explaining one embodiment of the present invention, and FIGS. 5 and 6 are cut-away front views of essential parts of a conventional example. each represents. In the figure, 1 is a substrate, 2 is a high resistance layer, 3 is an impurity supply layer, 4 is a buffer/cladding layer, 5 is an active layer, 6 is a cladding layer, 8 and 9 are buried layers, 10 is a conductive region ,1
1 and 12 indicate electrodes, respectively. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Akira Aitani Representative Patent Attorney Hiroshi Watanabe - Fig. 1 Fig. 2 Fig. 3 Fig. 4 Cutaway front view of main parts of conventional example Fig. 5

Claims (1)

【特許請求の範囲】 一導電型化合物半導体基板の上に化合物半導体高抵抗層
及び一導電型化合物半導体不純物供給層を含む諸半導体
層を成長させる工程と、 次いで、該諸半導体層の表面から前記化合物半導体高抵
抗層に達するメサ・エッチングを施してストライプ部分
を形成する工程と、 次いで、該ストライプ部分両側に化合物半導体埋め込み
層を形成すると共に前記一導電型化合物半導体不純物供
給層から前記化合物半導体高抵抗層に不純物を拡散して
一導電型導電化領域を形成する工程と を備えてなることを特徴とする半導体発光装置の製造方
法。
[Claims] A step of growing semiconductor layers including a compound semiconductor high resistance layer and a one conductivity type compound semiconductor impurity supply layer on a compound semiconductor substrate of one conductivity type; forming a stripe portion by performing mesa etching that reaches the compound semiconductor high resistance layer, and then forming a compound semiconductor buried layer on both sides of the stripe portion and removing the compound semiconductor layer from the one conductivity type compound semiconductor impurity supply layer. 1. A method of manufacturing a semiconductor light emitting device, comprising the step of diffusing impurities into a resistance layer to form a conductive region of one conductivity type.
JP27531486A 1986-11-20 1986-11-20 Manufacture of semiconductor light emitting device Pending JPS63129684A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27531486A JPS63129684A (en) 1986-11-20 1986-11-20 Manufacture of semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27531486A JPS63129684A (en) 1986-11-20 1986-11-20 Manufacture of semiconductor light emitting device

Publications (1)

Publication Number Publication Date
JPS63129684A true JPS63129684A (en) 1988-06-02

Family

ID=17553717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27531486A Pending JPS63129684A (en) 1986-11-20 1986-11-20 Manufacture of semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JPS63129684A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103545407A (en) * 2012-07-10 2014-01-29 华夏光股份有限公司 Leakage current prevention structure and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103545407A (en) * 2012-07-10 2014-01-29 华夏光股份有限公司 Leakage current prevention structure and manufacturing method thereof

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