JPS63126260A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase the integration density of element, by forming elements on specified regions of an upper semiconductor after bonding a base semiconductor on a specified region of which passive elements are formed and the upper semiconductor, and separating and insulating each element region. CONSTITUTION:A p-type silicon wafer 1 and an n-type silicon wafer 2 are respectively formed by stacking an insulating layer 5, a Ti metal layer 3, and a Pt metal layer 4. A resistance layer 6 is formed under the layer 5 of the wafer 1, and taken out by a resistance electrode film 8 connected to contact holes on both ends. After the wafers 1 and 2 are bonded in the manner in which the respective layers 4 are stacked, transistors and the like are formed on specified positions of the wafer 2. Then the wafer 2 between transistor regions is eliminated, and the respective island-shaped transistor regions 11 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit in which semiconductor substrates forming elements are structured in two stages.

[Conventional technology]

Since a monolithic semiconductor integrated circuit has a plurality of elements formed on a single semiconductor substrate, it is necessary to electrically isolate and insulate each element.

In order to achieve this separation and insulation, there has conventionally been a method of separating each element region by a pn junction and applying a reverse bias to the substrate to float and insulate each element region.

Also, a method has been developed for isolating and insulating each element by embedding an element region in polycrystal with an insulator such as an oxide film interposed therebetween using means such as etching or polycrystalline growth.

[Problem that the invention seeks to solve]

However, in the case of the method of applying a reverse bias to the pn junction, the element formation layer becomes thicker in order to provide the pn junction.
When a separation layer is formed between each element region by selective diffusion, etc.
This separation layer becomes too wide. For this reason, the gap between each element region becomes wide, resulting in a disadvantage that higher density of elements cannot be achieved. In addition, in semiconductor integrated circuits manufactured by this method, each element region is separated by a pn junction, so the barrier capacitance and leakage current of this pn junction have an adverse effect on electrical characteristics such as frequency characteristics and withstand voltage. It also had the disadvantage of having a negative impact.

In addition, in the method of embedding the element region in polycrystal, since there is no pn junction, it is possible to prevent an adverse effect on the electrical characteristics, and the gap between each element region can be narrowed. This has the disadvantage of wasting space, and in particular, passive elements (resistors, etc.) require a large area, which is an obstacle to increasing the density of elements. It was also the cause.

[Means for solving problems]

In order to solve the above problems, the method for manufacturing a semiconductor integrated circuit according to the present invention includes a step of forming passive elements in each predetermined region of a base semiconductor, and forming an upper semiconductor on the passive element forming surface of the base semiconductor. A step of bonding, a step of forming an active element and, if necessary, a passive device in each predetermined region of the bonded upper semiconductor, and a step of removing gaps between each element region of the upper semiconductor to separate and insulate each element region from each other. It is characterized by having a step of.

[For production]

The passive element formed in the base semiconductor is a resistor or the like. Passive elements such as resistors occupy a large area on the semiconductor, but since only passive elements are provided on the base semiconductor, they can be easily connected to active elements formed on the upper stage in later steps. Each element can be arranged relatively freely. These passive elements are formed using conventional semiconductor integrated circuit manufacturing processes such as selective diffusion of impurities on a base semiconductor, and wiring is performed by forming an insulating film and electrodes using a high-melting point material as necessary. .

Adhesion is performed by pressurizing metal layers or insulating layers formed on the bonding surfaces of the base semiconductor and the upper semiconductor at high temperature, or by other reliable bonding means. If necessary, an insulating layer is previously formed on the bonding surface of either or both of the base semiconductor and the upper semiconductor.

Active elements formed in the upper semiconductor are transistors, diodes, etc., and passive elements formed as needed are resistors, etc. These elements are formed by conventional semiconductor integrated circuit manufacturing processes such as impurity diffusion or ion implantation on the upper semiconductor, formation of an epitaxial layer, photoetching technology, selective etching technology, formation of an insulating film, and formation of electrodes. Ru. At this time, since each element region does not need to be separated by a pn junction, the thickness of the semiconductor may be the minimum required to form each element.

Removal between each element region of the upper semiconductor is performed by selective etching using photolithography technology. This removal of the semiconductor is performed until reaching the insulating layer of the upper semiconductor, the adhesive layer between the base semiconductor and the upper semiconductor, or the insulating layer of the base semiconductor, thereby reliably electrically separating and insulating each element region of the upper semiconductor. This semiconductor removal process is generally performed during the element formation process, followed by the formation of an insulating film, electrode formation, etc.

[Embodiment 1] An embodiment of the present invention will be described below based on FIGS. 1 to 5.

In this example, the crystal plane is (100) n as the base semiconductor.
Furthermore, a p-type silicon wafer 2 with a (100) crystal plane is used as the upper semiconductor, and a Ti metal is used as an adhesive layer to bond the n-type silicon wafer 1 and the p-type silicon wafer 2 together. A case is shown in which layer 3 and pt metal layer 4 are used.

First, as shown in FIG. 2, an n-type silicon wafer 1 is
After forming a resistor as a passive element at a predetermined location on the upper surface, an insulating layer 5 is formed on the entire upper surface, and a Ti metal layer 3 and a PT metal N4 are further formed in layers. p-type silicon wafer 2
After forming an insulating layer 5 on the entire bottom surface, a Ti metal layer 3 is formed.
and a Pt metal layer 4 are formed in an overlapping manner. To form a resistor on an n-type silicon wafer 1, first, a p-type impurity is selectively diffused to form a resistive layer 6, the entire upper surface of the resistive layer 6 is covered with a resistive insulating film 7 leaving an electrode window, and a predetermined pattern is formed on the upper surface. The resistive electrode film 8 is constructed by forming the resistive electrode film 8 . Selective diffusion of p-type impurities is achieved by covering the entire upper surface of the n-type silicon wafer 1 with a film of Sing or SiN by thermal oxidation or low-temperature vapor phase growth, and opening windows at predetermined locations using photoetching technology, etching technology, etc. After forming a diffusion mask, p-type impurities are diffused into the surface layer of n-type silicon wafer 1 by thermal diffusion or the like. At this time, the diffusion conditions are determined in consideration of the heat treatment temperature, etc. to be applied in a later step, so that the desired resistance value can be finally obtained.

For the resistive insulating film 7, after removing the oxide film etc. during selective diffusion, an oxide film is formed again by low-temperature vapor phase growth, etc., and electrode windows are opened at predetermined locations by photo-notching technology, etching technology, etc. It is formed by The resistive electrode film 8 is formed by low pressure CVD (Chemical Vapor
Mos W % W S iz- by deposition method, sputtering method, electron beam evaporation method, etc.
,M.

It is formed by forming a metal film with a high melting point such as Si, . .

The reason why such a high melting point material is used to form the resistive electrode film 8 is to prevent melting during subsequent heat treatment. The resistance of this resistance layer 6 is drawn out by resistance electrode films 8 connected to the contact holes at both ends. The insulating layer 5 is 5
It is made of iOz, SxN, Al2O3, or a multilayer film thereof, and is formed by a thermal oxidation method, a low-temperature vapor phase growth method, a sputtering method, or the like. The Ti metal layer 3 and the Pt metal layer 4 are formed by continuous sputtering or continuous electron beam evaporation. The Ti metal layer 3 is compatible with the oxide film of the insulating layer 5, etc., and since the Ti metal N3 and Pt metal layer 4 are also formed continuously in the vacuum chamber, these metal layers 3 and 4 are made of n-type silicon. It is firmly bonded to the wafer 1 and the n-type silicon wafer 2. The above steps correspond to the "step of forming passive elements in each predetermined region of the base semiconductor" which is a component of the present invention.

Next, as shown in FIG. 3, the n-type silicon wafer 1 and the n-type silicon wafer 2
are placed on top of each other and bonded by applying a predetermined temperature and pressure. Normally, a metal layer to which pressure is applied starts to firmly adhere in a temperature range of 40% to 50% of the melting point of the metal. In the case of Pt, this adhesion starting temperature is 88
Since 0 is a degree, here, the temperature is heated to 890° C. and pressure is applied. In this case, since Ti and pt hardly cause a metal reaction, the Ti metal layers 3, 3 and the Pt metal layer 4, which are bonded and integrated, maintain a stable state. The above steps correspond to the "step of bonding the upper semiconductor onto the passive element forming surface of the base semiconductor" which is a component of the present invention.

When the n-type silicon wafer 1 and the n-type silicon wafer 2 are bonded together as described above, the entire upper surface of the n-type silicon wafer 2 is smoothed and etched as shown in FIG. A transistor or the like as an active element is formed at a predetermined position of 2. When smoothing etching is performed, a protective layer is formed on the entire lower surface of the n-type silicon wafer 1. The protective layer is for protecting the n-type silicon wafer 1 from an etching solution during smoothing etching, and is made of a double metal film of TiAu, CrAu, or the like. Smooth etching is an operation in which the n-type silicon wafer 2, which has been sliced thickly in order to provide rigidity for convenience of handling, is ground down to the minimum thickness necessary for forming elements. As the etching solution, a KOH or NaOH aqueous solution that can preferentially etch the (100) plane of the n-type silicon wafer 2 is used. Note that at this time, polishing or the like may be performed as necessary. The protective layer on the lower surface of the n-type silicon wafer 1 is removed after smoothing etching is completed.

In order to form a transistor on the n-type silicon wafer 2 whose upper surface has been smoothed, base layers 9 and 9 are first formed at predetermined positions by selectively diffusing n-type impurities.
The emitter layer 10 is further formed by selectively diffusing p-type impurities into the
・Perform by forming 10, respectively. Note that the highest processing temperature for forming this transistor is about 1000°C when forming the base layer 9, but since the temperature at which the TiPt alloy system may melt is about 1300°C, the adhesive The coated Pt metal layer 4 does not peel off and is stable. In addition, since the resistance layer 6 is subjected to processing in anticipation of being subjected to these processing temperatures as described above when it is first formed, a desired resistance value can be obtained at this time.

The above steps correspond to a part of the "step of forming an active element and, if necessary, a passive element in each predetermined region of the bonded upper semiconductor" which is a component of the present invention.

Once the transistors are formed on the p-type silicon wafer 2 in this way, as shown in FIG. Form. The p-type silicon wafer 2 was removed using hydrofluoric acid as an etching solution, the insulating layer 5 was removed using hydrofluoric acid as an etching solution, and the Ti metal layer 3 was removed using sulfuric acid as an etching solution.
The removal is carried out by selective etching using photo-etching technology using aqua regia as an etching solution. The above steps correspond to the "step of removing the gaps between the respective element regions of the upper semiconductor and isolating and insulating the respective element regions of the upper semiconductor from each other" which is a component of the present invention.

Finally, as shown in FIG. A semiconductor integrated circuit is completed by opening electrode windows at required locations in the insulating layer 5 formed on the mold silicon wafer 1 and forming the electrode film 13 in a predetermined pattern. The insulating film 12 is made of SiO□, SiN, or the like, and is formed by a thermal oxidation method or a low-temperature vapor phase growth method. The electrode window is opened by removing a portion of the insulating film 12 and the insulating layer 5 using a photoetching technique, a selective etching technique, or the like. The electrode film 13 is /l, MOLW, MoSi2, W
A film of this conductor is formed on the insulating film 12 and the electrode window by electron beam evaporation, sputtering, or low-pressure plasma CVD, and then selectively etched using photoetching technology. It is formed by etching this conductor film into a predetermined pattern. The above steps correspond to a part of the "step of forming an active element and, if necessary, a passive element in each predetermined region of the bonded upper semiconductor" which is a component of the present invention.

In this example, a multilayer film of Ti metal layer 3 and PL metal layer 4 was used for bonding n-type silicon wafer 1 and p-type silicon wafer 2, but Cr and Cu, Cr and Pt
Or a multilayer film of Ti and Ni, etc., TiS 1% M
A single alloy film such as o SI SW SI SCr Co or the like may also be used.

[Embodiment 2] Another embodiment of the present invention will be described below with reference to FIGS. 6 to 8.

In this example, the crystal plane is (111) n as the base semiconductor.
A p-type silicon wafer 1' is used, and a p-type silicon wafer 2 with a (100) crystal plane is used as the upper semiconductor, and an adhesive layer for bonding these n-type silicon wafer 1' and p-type silicon wafer 2 is used. A case where an insulating layer 5' is used is shown.

First, as shown in FIG. 6, an n-type silicon wafer 1' has resistors as passive elements formed at predetermined locations on the upper surface, and an insulating layer 5' formed over the entire upper surface.

The p-type silicon wafer 2 has an n''tl layer 1 on the entire bottom surface.
4 is formed, and an insulating layer 5' is further formed.

To form a resistor on the upper surface of the n-type silicon wafer 1', first, p-type impurities are selectively diffused to form a resistive layer 6, and the entire upper surface is covered with a resistive insulating film 7 leaving an electrode window. It is constructed by forming a resistive electrode film 8 in a pattern. At this time, the diffusion conditions are determined in consideration of the heat treatment temperature, etc. to be applied in a later step, so that the desired resistance value can be finally obtained. Resistance electrode Jl! 8 is low pressure CV
MOLW by D method, sputtering method, electron beam evaporation method, etc.
After forming a metal film of a high melting point material such as , WSi2, Mo5iz, Ti5iz, etc. on the entire upper surface of the n-type silicon wafer 1',
It is formed by etching into a predetermined pattern using photo-etching technology or selective etching technology.

The resistance of this resistance layer 6 is drawn out by resistance electrode films 8 connected to the contact holes at both ends. The n+ buried layer 14 is formed by diffusing n-type impurities over the entire lower surface of the p-type silicon wafer 2. The insulating layer 5' is St
It is made of O□ and is formed by thermal oxidation method, low temperature vapor phase growth method, etc. This insulating layer 5' is made of P20S at the same time as it is formed.
and doping with B2O3. Non-doped Sin.

The melting point of the film is about 1700°C, but when PzOs is 10
% doping, the melting point will be about 1000° C., and if B201 or the like is additionally doped, the melting point will further decrease. Therefore, the insulating layer 5' has at least a surface layer of 11
P2O and Bz 03 are doped so as to melt at about 00°C. The above steps correspond to the "step of forming passive elements in each predetermined region of the base semiconductor" which is a component of the present invention.

Next, as shown in FIG.
5' are overlapped and bonded by applying a predetermined temperature and pressure. At this time, since pressure is applied to the insulating layers 5' and 5', the temperature is lower than 1100°C at which 5i02 melts.
Adhesion is carried out at a temperature of 000°C or less. The above steps correspond to the "step of bonding the upper semiconductor onto the passive element forming surface of the base semiconductor" which is a component of the present invention.

After the n-type silicon wafer 1' and the p-type silicon wafer 2 are bonded together as described above, the entire top surface of the p-type silicon wafer 2 is etched to smooth it in the same manner as in Example 1, as shown in FIG. , transistors and the like as active elements are formed on the smoothed p-type silicon wafer 2 at a predetermined value 't. To form a transistor on a p-type silicon wafer 2 whose top surface has been smoothed, a base N9.9 is first formed at a predetermined position by selective diffusion of n-type impurities, and then a p-type impurity is further added to the base layer 9.9. This is done by forming the emitter layers 10, 10, respectively, by selective diffusion.

Note that the highest processing temperature during the formation of this transistor is about 1000°C when forming the base layer 9, but the melting temperature of the insulating layer 5' consisting of 5in2 is 1100°C.
Since the bonded and integrated insulating layer 5' is not peeled off, it is stable. In addition, the resistance layer 6
However, since the diffusion conditions are set taking into consideration that these temperature treatments will be carried out, a predetermined resistance value is exhibited after these steps are completed. The above steps correspond to the component of the present invention, which is the step of forming an active element and, if necessary, a passive element in each predetermined region of the bonded upper semiconductor.

When transistors are formed on the p-type silicon wafer 2 in this way, as shown in FIG. At the same time as forming the regions 11, 11, an insulating film 12 is formed on the exposed portion of the insulating layer 5' and the entire upper surface of each transistor region 11, 11, and electrode windows are formed at necessary locations on the insulating film 12 and the insulating layer 5'. A semiconductor integrated circuit is completed by opening the electrode film 13 in a predetermined pattern. The above steps correspond to the "step of removing the gaps between the element regions of the upper semiconductor and isolating the element regions of the upper semiconductor from each other" which is a component of the present invention.

In addition, in Examples 1 and 2, a case was shown in which a resistive electrode film 8 was formed on the resistor formed on the n-type silicon urchin 1', but it may not be necessary due to the design and may not necessarily be formed. isn't it. Further, in Example 2, a case is shown in which an n+ buried layer 14 is provided on the lower surface of the p-type silicon wafer 2 in order to improve the characteristics of the transistor, but the p-type silicon wafer 2 of Example 1 also has a similar n+ buried layer 14. A buried layer can be provided. Furthermore, in Example 1 and Example 2,
Although the case where a silicon wafer is used as the base semiconductor and the upper semiconductor is shown, the present invention is not limited to this, and for example, GaAs or r
Group III-V semiconductors such as nP and other semiconductors can also be used. Further, in the first and second embodiments, a bipolar IC has been described, but it is also possible to implement the present invention in a unipolar IC such as a C-MOS-IC or other devices.

〔Effect of the invention〕

As described above, the method for manufacturing a semiconductor integrated circuit according to the present invention includes the steps of forming passive elements in each predetermined region of the base semiconductor, and bonding the upper semiconductor onto the passive element forming surface of the base semiconductor. , forming an active element and, if necessary, a passive element in each predetermined region of the bonded upper semiconductor; and a step of removing gaps between each element region of the upper semiconductor and isolating and insulating each element region from each other. This is a configuration that has

As a result, each element region of the upper semiconductor is separated and insulated by removing the semiconductor in the gap, so there is no need to provide a pn junction, which reduces the distance between each element region and reduces the negative effect C on electrical characteristics. I won't even receive it (naru).

In addition, passive elements that require a particularly large area are formed in the base semiconductor as much as possible, and active elements are mainly formed in the upper semiconductor, making it possible to significantly increase the density of elements. This not only improves the yield of integrated circuits, but also eases restrictions on the position and shape of passive elements, making design easier.

[Brief explanation of the drawing]

1 to 5 show one embodiment of the present invention, in which FIG. 1 is a vertical cross-sectional partial front view of a semiconductor integrated circuit, and FIG.
5 to 5 are vertical cross-sectional partial front views showing the manufacturing process of a semiconductor integrated circuit, FIGS. 6 to 8 show other embodiments of the present invention, and FIG. 6 is a longitudinal cross-sectional view of the semiconductor integrated circuit. 7 and 8 are vertical cross-sectional partial front views showing the manufacturing process of a semiconductor integrated circuit. l・1' is n-type silicon wafer (base semiconductor), 2 is n
type silicon wafer (upper semiconductor), 3 is Ti metal layer, 4
is a PT metal layer, 5' is an insulating layer, 6 is a resistance layer, and 11 is a transistor region. Patent applicant Sharp Co., Ltd. Figure 1'$2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A process of forming passive elements in each predetermined region of the base semiconductor, a process of bonding an upper semiconductor on the passive element forming surface of the base semiconductor, and a step of forming an active element and as necessary in each predetermined region of the bonded upper semiconductor. 1. A method of manufacturing a semiconductor integrated circuit, comprising the steps of forming passive elements accordingly, and removing gaps between each element region of an upper semiconductor to isolate and insulate each element region from each other.