JPS63124472A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a FET operating at high speed by implanting N-type impurity ions, collectively forming a sufficiently activated low-resistance contact region and an N-type conductive layer as an operating layer and implanting P-type impurity ions only into the operating layer and lowering the effective concentration of electrons. CONSTITUTION:Si ions are implanted into a semi-insulating GaAs substrate 11 and a plasma Si3N4 film is applied, and an operating layer 12 in an N-type low-resistance contact region is formed through heat treatment in an H2 atmosphere. The Si3N4 film is removed, an SiO2 film 19 is applied again, a slitty opening is bored made to correspond to a gate-electrode forming section, and Mg ions are implanted and a source contact region 14 and a drain region 15 are shaped through heat treatment in the H2 atmosphere containing AsH3. Al is used as a Schottky barrier gate electrode material, a gate electrode 13 is formed on the boundary of the regions 14 and 15 exposed into the opening, and films 19 on the regions 14 and 15 are removed and a source electrode 16 and a drain electrode 17 are attached to the films 19.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor, and more particularly to a method for manufacturing a Schott 1 barrier gate type gallium arsenide field effect transistor.

[Conventional technology]

In order to improve the performance of a Schottky barrier gate field effect transistor (MESFET) using gallium arsenide (GaAs), reducing the source parasitic resistance is most important.

For this purpose, it is effective to form a low resistance contact region with a high impurity concentration in self-alignment with the gate electrode.

Conventionally, GaAs MESFs using this type of self-alignment technology have not been used.
The manufacturing method of ET is described in the Proceedings of the International Solid Stay 1~Circuit Conference (19811EE).
E 5olid-3tateC4rcuits C
218-219. For this purpose, those manufactured according to the manufacturing process shown in FIGS. 2(a) to 2(d) have been widely used.

That is, as shown in FIG. 2(a), first, ion implantation and activation are performed to form an active layer 12 on a semi-insulating GaAs substrate 11, and on this active layer 12, for example, Ti is deposited.
The gate electrode 23 is formed using a heat-resistant metal such as -W alloy, and then the gate electrode 23 is used as a mask to form the gate electrode 23 as shown in FIG.
), ion implantation is performed to form a low resistance contact region to form a source contact region 14 and a drain contact region 15, and as shown in FIG. 2(C), for example, after depositing a SiO□ film 29, Activation is performed by heat treatment at a temperature below the activation temperature of the active layer, as shown in Figure 2(d).
A source electrode 16 and a drain electrode 17 are formed to obtain Ga As M E S F E T as shown in FIG.

[Problem that the invention seeks to solve]

The above-mentioned conventional G a As M E S F E
In the manufacturing method of T, low resistance contact regions (14, 15
) It is difficult to make the activation temperature higher than the activation temperature of the active layer 12, and it is also difficult to make the activation time sufficiently long. This is a heat treatment process for activating the low resistance contact area, and the active layer is also heat treated at the same time.
The higher the activation temperature and the longer the activation time, the wider the implanted impurity profile becomes
This is because it degrades the mutual conductance (g,) of the S FET. However, when comparing the active layer 12 and the low-resistance contact regions (14, 15>), the latter has higher acceleration energy and larger implantation dose, so the activation temperature is higher and it takes longer than 2 hours. Conventional GaAs
The MESFET manufacturing method has the drawback that activation of the low-resistance contact region is insufficient, and the source parasitic resistance cannot be sufficiently reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a field effect transistor that eliminates these drawbacks, sufficiently reduces source parasitic resistance, and improves high-speed operation and high-frequency operation.

[Means for solving problems]

The method for manufacturing a field effect transistor of the present invention includes a step of forming a source contact region and a drain contact region by ion-implanting and activating an n-type impurity into a gallium arsenide substrate, and a step of forming a source contact region and a drain contact region. A step of opening an intermediate region between the two regions and covering the other region with a mask material, and setting an acceleration energy for applying an n-type impurity using the mask material as a mask so that the average projected range is deeper than that of the n-type impurity. a step of ion-implanting the contact region; a step of activating the contact region by heat treatment at a temperature lower than the activation temperature of the contact region; and a step of providing a gate electrode in the n-type impurity implantation region and the source contact region and the drain contact region. The structure includes a step of providing a source electrode and a drain electrode, respectively.

[Effect]

Generally, n-type impurities in GaAs can be activated by heat treatment at a lower temperature and for a shorter time than that for n-type impurities. Therefore, in the manufacturing process of GaAs MESFET, an n-type impurity is first ion-implanted and sufficiently activated to form a low-resistance contact region and an active layer.
The type conductive layer is formed all at once, and then n-type impurities are ion-implanted only in the region that is to become the active layer, and activated at a lower temperature and in a shorter time than the n-type region, effectively improving the effectiveness of the region that is to become the active layer. By reducing the electron concentration, the source resistance can be significantly reduced.

〔Example〕

The present invention will be described in detail below using the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views illustrating an embodiment of the present invention in the order of steps. First, as shown in FIG. 1 (a), Si ions are deposited on the main surface of a semi-insulating GaAs substrate 11 at an acceleration energy of 70 KeV and a dose of 3×1013C11-2.
Ion implantation was performed under the following conditions, a plasma silicon nitride film with a thickness of 0.1 μm was deposited, and heat treatment was performed for 20 minutes in a hydrogen atmosphere at 850° C. to form the active layer 12 of the n-type low resistance contact region.
is formed, and then the silicon nitride film is removed. Next, thickness 0
．． A 5 μm thick Si 02 film 19 is deposited, and the Si 02 film in the gate electrode formation area is removed by cutting into a 1.5 μm long slit shape, and the Mg ions are accelerated with an energy of 120 μm.
After ion implantation under the conditions of K e V , dose IX], 013 cm -2 , it was activated by heat treatment for 5 minutes in a hydrogen atmosphere at 750° C. containing As H3, and as shown in Fig. 1 (1).
), a source contact region 14° and a drain contact region 15 are formed.

Next, a 0.3 μm thick A/ as an electrode material is deposited on the shop 1 as a key barrier gate 1 by vacuum evaporation, and unnecessary portions of A are removed using H3PO4 using a photoresist as a mask to form a gate electrode 13. (Fig. 1 (C))
. Further, the 5i02 film 19 of the source contact region 14 and drain contact region 15'' is removed, and the 5i02 film 19 of
~AuGe alloy with a thickness of 0.1 μm by the off method, thickness 0
．． A laminated metal film made by successively depositing 0.3 μm of Ni was selectively installed, and the temperature was raised to 420° C. to form a source electrode 16 and a drain electrode 17 (Fig. 1(d)), GaAsME.
Completed SFET.

Ga with a gate length of 1.5 μm obtained in this way
The source parasitic resistance of AsMESFET is 0.4Ω1m, an improvement of more than 40% compared to the conventional one, and the maximum value of g is 33
It became 0m5/dragon.

〔Effect of the invention〕

As explained above, according to the present invention, the low resistance contact I-
It has become possible to reduce the source resistance of a region self-aligned GaAs MESFET, increase g7, and easily realize high-speed operation and high-frequency operation. In this example, p
We have explained the case where the p-type ion implantation region and the gate electrode are formed in a self-aligned manner by using the type ion implantation mask as it is as the Goo 1~Open Lo mask, but there is a case where the gate electrode is formed without using the self-alignment method. It goes without saying that the effects of the present invention can also be obtained.

[Brief explanation of the drawing]

1(a) to 1(d) are cross-sectional views of a GaAs MESFET explaining one embodiment of the present invention in the order of manufacturing steps, and FIG. 2(a)
) to (d) are sectional views sequentially showing the manufacturing process of a conventional GaAsM ESFET. 1]... Semi-insulating GaAs substrate, ]2... Operating layer, 1.3.23... Gate electrode, ]4... Source contact region, 15... Drain contact region,
16...source electrode, 17...drain electrode, ]9
...Mask = 9- Ward 4, Figure 2

Claims (1)

[Claims] A step of forming a source contact region and a drain contact region by ion-implanting and activating an n-type impurity into a gallium arsenide substrate, and opening an intermediate region between the source contact region and the drain contact region and forming other regions. a step of covering with a mask material, a step of ion-implanting a p-type impurity using the mask material as a mask while setting acceleration energy so that the average projected range is deeper than that of the n-type impurity, and activating the contact region. a step of activating the p-type impurity by heat treatment at a temperature below the oxidation temperature; and a step of providing a gate electrode in the p-type impurity implantation region and providing a source electrode and a drain electrode in the source contact region and drain contact region, respectively. A method of manufacturing a field effect transistor, characterized in that: