JPS63124446A - 接続孔形成方法 - Google Patents

接続孔形成方法

Info

Publication number
JPS63124446A
JPS63124446A JP62205346A JP20534687A JPS63124446A JP S63124446 A JPS63124446 A JP S63124446A JP 62205346 A JP62205346 A JP 62205346A JP 20534687 A JP20534687 A JP 20534687A JP S63124446 A JPS63124446 A JP S63124446A
Authority
JP
Japan
Prior art keywords
layer
stud
forming
connection hole
studs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62205346A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0583177B2 (en:Method
Inventor
ポール・ノーマン・シャロックス、ジュニア
トーマス・フレデリツク・ホートン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS63124446A publication Critical patent/JPS63124446A/ja
Publication of JPH0583177B2 publication Critical patent/JPH0583177B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P14/69215—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H10D64/0111—

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP62205346A 1986-11-06 1987-08-20 接続孔形成方法 Granted JPS63124446A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US92762386A 1986-11-06 1986-11-06
US927623 1986-11-06

Publications (2)

Publication Number Publication Date
JPS63124446A true JPS63124446A (ja) 1988-05-27
JPH0583177B2 JPH0583177B2 (en:Method) 1993-11-25

Family

ID=25455013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62205346A Granted JPS63124446A (ja) 1986-11-06 1987-08-20 接続孔形成方法

Country Status (3)

Country Link
EP (1) EP0266522B1 (en:Method)
JP (1) JPS63124446A (en:Method)
DE (1) DE3780407T2 (en:Method)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7314077B2 (en) 2003-10-16 2008-01-01 Fanuc Ltd Telescopic cover

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0748502B2 (ja) * 1988-05-13 1995-05-24 三菱電機株式会社 半導体装置の製造方法
JP2000294545A (ja) * 1999-04-09 2000-10-20 Nec Corp 半導体装置及びその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2419586A1 (fr) * 1978-03-08 1979-10-05 Thomson Csf Circuit integre et son procede de fabrication
US4353159A (en) * 1981-05-11 1982-10-12 Rca Corporation Method of forming self-aligned contact in semiconductor devices
US4640738A (en) * 1984-06-22 1987-02-03 International Business Machines Corporation Semiconductor contact protection
US4541168A (en) * 1984-10-29 1985-09-17 International Business Machines Corporation Method for making metal contact studs between first level metal and regions of a semiconductor device compatible with polyimide-filled deep trench isolation schemes
JPS61242044A (ja) * 1985-04-19 1986-10-28 Matsushita Electronics Corp 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7314077B2 (en) 2003-10-16 2008-01-01 Fanuc Ltd Telescopic cover

Also Published As

Publication number Publication date
JPH0583177B2 (en:Method) 1993-11-25
EP0266522A3 (en) 1988-10-05
DE3780407T2 (de) 1993-03-04
DE3780407D1 (de) 1992-08-20
EP0266522A2 (en) 1988-05-11
EP0266522B1 (en) 1992-07-15

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