JPS63123152A - Memory access system - Google Patents

Abstract

PURPOSE:To reduce memory competition and to improve system performance by grouping plural processors, associating plural memories with the groups one by one, giving the same memory capacity to each group and allocating the same address to the groups. CONSTITUTION:When a processor 1 reads data out of the memory, a memory access control part 7 turns on a signal line 15, and gives a read command R to the memory 5 and simultaneously gives a read address A to the memory 5 through a signal line 11. When the processor 1 writes data in the memory, the memory access control part 7 turns on a signal line 16, and gives a write command R to the memories 5 and 6 and simultaneously gives write address A and write data D1 to the memories 5 and 6 through a signal line 14. A processor 2 accesses the memory in the same manner as the processor 1, and processors 3 and 4 do the same action except for reading data in the memory 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access method in a multiprocessor system.

[Conventional technology]

In a conventional multiprocessor system, multiple processors use one memory (here, one memory means one memory with the same address assigned to every processor). The disadvantage was that as the number of processors increased, memory contention increased and system performance did not improve as the number of processors increased.

[Problem that the invention seeks to solve]

Therefore, the present invention provides a multiprocessor system that
The problem to be solved is to reduce memory contention and improve system performance regardless of the increase in the number of processors.

[Means for Solving the Problem] In order to solve the above problem, the present invention provides a multiprocessor system consisting of a plurality of processors and a plurality of memories, in which the plurality of processors are grouped into a plurality of groups, and , the plurality of memories are associated one with each of the plurality of groups, and the plurality of memories all have the same storage capacity and are assigned the same address.

[Effect]

When accessing an arbitrary address consisting of an arbitrary processor in an arbitrary group among the plurality of groups, if the access is for reading, access the address in the memory corresponding to the group to which the processor belongs, and If the access is for writing, the relevant address of all the memories of the plurality of devices is accessed.

〔Example〕

FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, 1. 2. 3. 4 are processors, processors 1 and 2 belong to the first group, and processors 3 and 4 belong to the second group. 5 and 6 are memories, respectively, and are assigned addresses from address 0 to address (A-1), respectively.

7 is a memory access control unit in the processor 1,
In the case of reading, the signal line 15 is turned on, and in the case of writing, the signal line 16 is turned on. 8 is a memory address register (MAR), 9 is a read data register (RD
R), 10 is write data register (WDR),
11 is a signal line that supplies the contents of the memory address register 8 in the processor 1 to the memory 5; 12 is a signal line that supplies the contents of the memory address register 8 to the memories 5 and 6; and 13 is a data register that reads data read from the memory 5. Signal line given to 9, 14 is write data register 1
A signal line 15 gives the contents of 0 to the memory 5.6, a signal line 15 gives a read instruction from the processor 1 to the memory 5,
16 receives the write instruction from the processor 1 into the memories 5 and 6.
This is the signal line that feeds the

Internal configuration of processors 2 and 3.4 and processors 2 and 3
．． 4 and the memory 5.6 is not shown in FIG. 1 because it is not necessary for explaining the present invention.

Hereinafter, a memory access method as a first embodiment of the present invention will be explained with reference to FIG.

First, when reading a memory from the processor 1, the memory access control unit 7 turns on the signal line 15, gives a read instruction R to the memory 5, and also gives a read address A to the memory 5 via the signal line 11. memory 5
performs a read operation (the read operation in the memory 5 is a well-known technical matter, so its explanation will be omitted) and provides read data DO to the read data register 9 in the processor via the signal line 13. In this way, memory reads from the processor are performed only to memory 5.

Next, when writing to the memory from the processor, the memory access control unit 7 turns on the signal line 16, gives a write instruction W to the memories 5 and 6, and the signal line 12
The write address A is applied to the memories 5 and 6 via the signal line 14, and the write data D1 is applied to the memories 5 and 6 via the signal line 14. Memories 5 and 6 perform write operations (write operations within memories 5 and 6 are well-known technical matters, so their explanation will be omitted).
.

Therefore, the contents held in all memories are always kept the same.

Here, memory access from processor 1 has been explained, but as can be easily inferred, memory access from processor 2 is the same as that from processor 1, and memory access from processors 3 and 4 is such that reading is performed on each memory. This is the same as the memory access from processor 1, except that it is done for processor 6.

FIG. 2 is a block diagram showing a second embodiment of the invention. In the same figure, parts 1 to 15 are exactly the same as those in FIG.

100 is a memory access control register (MACR), and the same value is set for all processors.

Addresses 0 to j (0<j< (A-1)) of the memory are the specific area of each group of processors, and the (j+1) of the memory
If the address (A-1) from the address is a shared area for all processors, set the value j in the memory access control register 100 (because setting the value in the memory access control register 100 is a well-known technical matter) , the explanation is omitted). A comparison circuit 101 compares the value of the memory access control register 100 supplied via the signal line 105 with the value of the memory address register 8 supplied via the signal line 106. If the value of is smaller than or equal to the value of the memory access control register 100, the signal line 107 is turned on.

102 is a NOT circuit, and 103 and 104 are AND circuits. 16 is a signal line that sends a write instruction from the processor 1 to the AND circuits 103 and 104; 105 is a signal line that sends the contents of the memory access control register 100 to the comparison circuit 101; and 106 is a signal line that sends the contents of the memory address register 8 to the comparison circuit 101. The signal line 107 is the comparison circuit 101.
The output of the inverting circuit 102. A signal line 108 supplies the output of the NOT circuit 102 to the AND circuit 103.
109 is a signal line that provides the output of the AND circuit 103 to the memory 5, and 110 is a signal line that provides the output of the AND circuit 104 to the memories 5 and 6.

Hereinafter, a memory access method as a second embodiment of the present invention will be explained with reference to FIG. However, since reading from the memory from the processor 1 is the same as that explained in FIG. 1, the explanation will be omitted, and the writing from the processor 1 to the memory will be explained.

First, if the address to be written into the memory by the processor 1 is smaller than or equal to the address j set in the memory access control register 100, the output of the comparison circuit 101 is turned on, the AND circuit 103 is turned on, and the AND circuit 104 is turned off. Become. Therefore, the write instruction from the memory access control unit 7 is sent to the signal line 16. AND circuit 103.
It is applied only to the memory 5 via the signal line 109, and writing is performed only to the memory 5.

Next, if the address to be written into the memory by the processor 1 is larger than the address j set in the memory access control register 100, the output of the comparison circuit 101 is turned off, the AND circuit 103 is turned off, and the AND circuit 104 is turned on. .

Therefore, the write instruction from the memory access control unit 7 is sent to the signal line 16. AND circuit 104. Memory 5. via signal line 110. memory 6, and writing is performed in memory 5. This is done for memory 6. Therefore, the contents of all memories are kept the same in areas where the memory address is greater than address j, that is, areas shared by all processors.

FIG. 3 is a block diagram showing a third embodiment of the present invention. In the same figure, I,2,3.4 is a processor,
Processors 1 and 2 belong to the first group, and processors 3 and 4 belong to the second group. 5 and 6 are memories, 70 is a write tag memory, and information on whether or not writing has been performed for each address of the memory (for example, if address a of the memory is rewritten, the tag at the same address in the tag memory is turned on) , if the tag has not been rewritten, the same tag is off) and the group number of the processor that has performed the rewriting (1 or 2 in the case of FIG. 3).

80.90 is a memory switch, which is a switch for selecting memory to be accessed from the processor. 10 is a signal line connecting the processor 1 and the memory switch 8; 11
is a signal line connecting the processor 2 and the memory switch 8,
12 is a signal line connecting the processor 3 and memory switch 9; 13 is a signal line connecting processor 4 and memory switch 9; 14 is a signal line connecting write tag memory 70 and memory switch 80; 15 is a write tag memo U
16 is a signal line that connects the memory 5 and the memory switch 80; 17 is a signal line that connects the memory 6 and the memory switch 90; 18 is a signal line that connects the memory 6 and the memory switch 90;
is a signal line connecting memory switch 80 and memory switch 90.

Hereinafter, a memory access method as a third embodiment of the present invention will be explained with reference to FIG.

First, when reading memory from the processor 1, the processor 1 sends a memory address (for example, address a) to the memory switch 80 via the signal line 10. The memory switch 80 reads the contents of address a (tag and processor group number) of the write tag memory 70 via the signal line 14, and if the tag is off, that is, the memory has not been rewritten, and which memory should have the same content, so
The contents of address a are read from the memory 5 corresponding to its own group (first group) via the signal line 16 and sent to the processor 1 via the signal line 10.

If the tag is on and the processor group number is 1, the content read by the memory switch 80 from address a of the write tag memory 70 via the signal line 14 is read from address a of the memory 5 corresponding to group number 1. Since this indicates that the content has been rewritten, the switch 80 also reads the content of address a (the latest content that has been rewritten) from the memory 5 via the signal line 16, and transfers the read content via the signal line 10. Send to processor 1.

On the other hand, if the tag is on and the group number of the processor is 2, this means that the contents of the memory 6 corresponding to group number 2 have been rewritten, so the read address a is sent to the memory switch 90 via the signal line 18. send. The memory switch 90 reads the content of address a (the latest rewritten content) from the memory 6 via the signal line 17 and sends the read content to the memory switch 80 via the signal line 18.

The memory switch 80 transfers the contents of the sent address a to the signal line 1.
0 to processor 1.

Next, when writing to the memory from the processor 1, the processor 1 sends the memory address (a) via the signal line 10.
address) and write data to the memory switch 80. The memory switch 80 writes write data to address a of the memory 5 via the signal line 16. Furthermore, signal line 1
4, the tag at address a of the write tag memory 70 is turned on, and the processor group number written there is set to 1.

The memory reading and writing from the processor 1 has been described above. Memory reading and writing from the processors 2, 3 and 4 will be similarly easily understood and will not be repeated.

In Figure 3, there is only one write tag memory, but
In order to reduce contention for access to the write tag memory, it is also possible to install multiple write tag memories.

FIG. 4 is a block diagram showing fourth and fifth embodiments of the present invention. In the figure, 1, 2, 3.4 are processors, processors 1 and 2 are in the first group, processors 3.
4 belongs to the second group.

5A and 6A are read memories, 5B and 6B are write memories, and 70 is a write tag memory. Information on whether or not writing has been performed for each address of the memory (if address a is rewritten, the tag is on, If the data has not been rewritten, the tag is turned off) and the group number of the processor that performed the rewriting (1 or 2 in the case of FIG. 4) is retained. 80
．． Reference numeral 90 denotes a memory switch, which is a switch for selecting a memory to be accessed by the processor. 12 is a signal line connecting the processor 1 and the memory switch 80; 13 is a signal line connecting the processor 2 and the memory switch 80;
14 is a signal line connecting the processor 3 and memory switch 90; 15 is a signal line connecting processor 4 and memory switch 90; 16 is a signal line connecting write tag memory 70 and memory switch 80; 17 is write tag memory 70. 18 is a signal line that connects the readout memory 5A and the memory switch 80, 19 is a signal line that connects the readout memory 6A and the memory switch 90.
20 is a signal line that connects the write memory 5B and the memory switch 80, 21 is a signal line that connects the write memory 6B and the memory switch 90, and 22 is a signal line that connects the memory switch 80 and the memory switch 90. It is.

A memory access method according to a fourth embodiment of the present invention will be described below with reference to FIG.

First, when reading memory from the processor 1, the processor 1 sends a memory address (address a) to the memory switch 80 via the signal line 12.

The memory switch 80 reads the contents of address a (tag and processor group number) of the write tag memory 70 via the signal line 16, and when the tag is off, reads the contents of address a from the read memory 5A via the signal line 18. and sends the read contents to the processor 1 via the signal line 12. On the other hand, if the tag is on, this indicates that all write memories are being rewritten, so the contents of address a (the latest rewritten contents) are read from the write memory 5B via the signal line 20. The read contents are sent to the processor 1 via the signal line 12.

Next, when writing to the memory from the processor 1, the processor 1 sends the memory address (a) via the signal line 12.
address) and write data to the memory switch 80. The memory switch 80 writes write data to address a of the write memory 5B via the signal line 20. Furthermore, the tag at address a in the write tag memory 70 is turned on via the signal line 16. Also, the write address a and write data are sent to the memory switch 90 via the signal line 22.
send to The memory switch 90 writes write data to address a of the write memory 6B via the signal line 21.

The memory reading and writing from the processor 1 has been described above. The same goes for memory reads and writes from processor 2.3.4.

Hereinafter, a memory access method as a fifth embodiment of the present invention will be explained with reference to FIG.

First, when reading memory from the processor 1, the processor 1 sends a memory address (address a) to the memory switch 80 via the signal line 12.

The memory switch 80 reads the contents of address a (tag and processor group number) of the write tag memory 70 via the signal line 16, and when the tag is off, reads the contents of address a from the read memory 5A via the signal line 18. and sends the read contents to the processor 1 via the signal line 12.

If the tag is on and the group number of the processor is 1, this means that the contents of the write memory 5B corresponding to group number 1 have been rewritten, so the contents of address a are transferred from the write memory 5B via the signal line 20 ( The latest rewritten content) is read out, and the read content is sent to the processor 1 via the signal line 12. If the tag is on and the processor group number is 2, this indicates that the contents of the write memory 6B corresponding to group number 2 have been rewritten.
A read address a is sent to the memory switch 90 via the signal line 22. The memory switch 90 reads the content of address a (the latest rewritten content) from the write memory 6B via the signal line 21, and transfers the read content to the signal line 2.
2 to the memory switch 80. The memory switch 80 sends the contents of address a to the processor 1 via the signal line 12.

Next, when writing to the memory from the processor 1, the processor 1 sends the memory address (a) via the signal line 12.
address) and write data to the memory switch 80. The memory switch 80 writes write data to address a of the write memory 5B via the signal line 20. Further, the tag at address a of the write tag memory 70 is turned on via the signal line 16, and the group number of the processor is set to 1.

The memory reading and writing from the processor 1 has been described above. The same goes for memory reading and writing from the processors 2, 3 and 4.

In Figure 4, there is one write tag memory, but
In order to reduce contention for access to the write tag memory, it is also possible to provide a plurality of write tag memories.

〔Effect of the invention〕

As explained above, the number of memory reads per processor is R (times/second), the number of memory writes per processor is W (times/second), and the probability that the tag in the write tag memory is off is α In this case, the number of memory accesses when the number of memories is one is (NR+NW) (times/second).

On the other hand, in the first and second embodiments of the present invention, the number of memory accesses to one memory is (nR+NW)(times/
In the third embodiment of the present invention, the number of memory accesses to one memory is (nR+nW) (times/second), and in the fourth embodiment of the present invention, the number of memory accesses to one read memory is [ nαR) (times/sec), and the number of memory accesses to the write memory is [n(1-α)R+NW) (times/sec)
, in the fifth embodiment of the present invention, the number of memory accesses to one read memory is [nαR) (times/sec), and the number of memory accesses to the write memory is (n (1-α)R+n
W) (times/second), which has the advantage that the number of memory accesses is distributed compared to the case of one memory, memory access contention is reduced, and system performance is improved.

[Brief explanation of the drawing]

1 to 4 are block diagrams each showing an embodiment of the present invention. Description of symbols 1.2, 3.4... Processor, 5, 6... Memory, 7... Memory access control unit, 8... Memory address register, 9... Read data register, 10
...Write data register, 100...Memory access control register, 101...Comparison circuit, 102.
...Negation circuit, 103.104...AND circuit, 70
...Writing tag memory, 80.90...Memory switch, 5A, 6A...Reading memory, 5B, 6B
...Writing memory. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki 143 Figure 4 Figure 6A 6t:1

Claims (1)

[Scope of Claims] 1) In a multiprocessor system consisting of N processors and K memories, the N processors are grouped into K groups each having n processors, and the K One memory is associated with each of the K groups, and each of the K memories has the same storage capacity and is assigned the same address. When any processor in a group accesses an arbitrary address, if the access is for reading, then
A memory access method characterized in that the relevant address of the memory corresponding to the group to which the processor belongs is accessed, and if the access is for writing, the relevant address of all K memories is accessed ( However, N, K
, n are all integers, and there is a relationship of N=n×K). 2) In the memory access method according to claim 1, each of the processors is provided with a memory access control register, and any processor in any one of the K groups accesses a certain arbitrary address A. In this case, if the access is for reading, the relevant address A of the memory corresponding to the group to which the processor belongs is accessed, and if the access is for writing, the relevant address A is held in the memory access control register. is compared with a certain value B, and if A is smaller than B (or larger), the address A of the memory corresponding to the group to which the processor belongs is accessed, and if A is larger than B (or
A memory access method characterized in that when the memory is small), the corresponding address A of all K memories is accessed. 3) In a multiprocessor system consisting of N processors and K memories, the K memories have a common write tag memory,
The N processors are grouped into K groups each having n processors, one memory is associated with each of the K groups, and the K memories are divided into K groups each having n processors. and the tag memory are assigned the same address, and when any processor in any one of the K groups accesses a certain arbitrary address, if the access is for writing, that processor's Accesses the address in the memory corresponding to the group to which it belongs, and writes that fact (accessed) and the number of the group to which the accessed processor belongs to the address in the tag memory, even if the access is for reading. For example, the processor first refers to the address in the tag memory to find out whether there is an access written there, and if there is no access, it accesses the address in the memory corresponding to the group to which the processor belongs, and determines whether there is an access written there. In this case, the number of the group to which the processor that made the access corresponding to the presence belongs is also known from the corresponding address in the tag memory, and the access is made to the corresponding address in the memory corresponding to the group with that number. Characteristic memory access method (N, K, and n are all integers, and there is a relationship of N=n×K). 4) In the memory access method according to claim 3, each of the K memories is composed of a write memory and a read memory, and write access is to the write memory, and read access is to the write memory. A memory access method characterized in that reading is performed on memory. 5) In a multiprocessor system consisting of N processors and K memories each consisting of a read memory and a write memory, the K memories have a common write tag memory, and the N processors , each group is divided into K groups each having n processors, and the K memories are associated with each of the K groups, and each readout memory and each The write memory and the tag memory are assigned the same address, and when any processor in any one of the K groups accesses a certain arbitrary address, if the access is for writing, the above All K write memories are accessed and written, and a message to that effect (accessed) is written to the corresponding address in the tag memory. If the access is for reading, the processor first writes data to the corresponding address in the tag memory. Check to see if there is an access written there, and if there is no access, access the read memory corresponding to the group to which the processor belongs, and if there is, access to the read memory corresponding to the group to which the processor belongs. 1. A memory access method characterized in that a written memory is accessed and read from the written memory (N, K, and n are all integers, and there is a relationship of N=n×K).