JPS63120536A - Bit collation supervisory equipment for stuff synchronizing multiplex converter - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution of the titled equipment and to attain correct bit collation by making a delay of a buffer memory constant, counting the bit difference between a high data string and a low speed data string so as to reset the readout of the buffer memory and to take the phase synchronization of the bit unit. CONSTITUTION:The initial setting of write to a buffer memory to a buffer memory 2 at a high speed signal is applied in synchronism with a stuff signal informing the rejection of a stuff pulse of a demultiplex section 1. Throuth the initial setting, the delay of the buffer memory 2 to a data string of a low speed signal obtained by decomposing a high speed signal is decided depending on the read position and the delay of the delay part 4 provided with the low speed signal is fixed. Then the data string of the low speed signal and the data string of high speed signal are compared by a comparator section 3 and its bit difference is counted by a counter 6. Thus, the circuit constitution is simplified. mis-synchronization is eliminated to ensure the bit collation.

Description

[Detailed Description of the Invention] [Summary] Phases of low-speed side signals and high-speed side signals in a bit matching monitoring device that synchronizes the phases of high-speed side signals and low-speed side signals of a stuff synchronous multiplex converter and collates them bit by bit. Synchronous method. First, the delay amount of the buffer memory is made constant by performing the initial setting of the buffer memory in which the high-speed side signal is decomposed and written in synchronization with the sending of the stuff signal in which both signals have the same phase, and then the high-speed side data is The circuit configuration of the device is simplified by counting the number of bit differences between the column and the low-speed data column and resetting the readout of the buffer memory to achieve bit-by-bit phase synchronization.

[Industrial application field]

The present invention relates to a stuffed synchronous multiplex converter, and more particularly to a monitoring device for monitoring bit errors in a stuffed synchronous multiplex converter.

A stuff synchronous multiplex converter bundles 0 low-speed digital signals whose frequency is not synchronized in a communication channel, adds and inserts stuff pulses, converts them into high-speed digital signals, and sends them out. This inverse conversion is performed.

Communication channels were originally designed to have code errors,
It is designed and monitored so that the code error does not exceed a certain value.

As a monitoring device for a stuff synchronous multiplex converter, stuff synchronization is achieved by checking and comparing the low speed digital signal bit by bit with the low speed digital signal of the same series created by decomposing the high speed digital signal. A bit matching monitoring device is generally used to detect code errors that occur during multiplexing processing by a multiplex conversion device.

During this code error detection, the two low-speed signals of the same series created by decomposing the low-speed side signal and the high-speed side signal have a phase shift because their respective transmission paths are different. Bit matching generally requires a circuit to compensate for this phase shift, but as a PIP/verification monitoring device, it is possible to simplify the circuit to compensate for this phase shift and facilitate control for phase synchronization. desired.

[Conventional technology]

As shown in FIG. 3, the conventional bit matching monitoring device of a stuff synchronous multiplex converter decomposes a high-speed side digital signal into signals at a speed of 1/n in a separating unit 1 and writes them into a buffer memory 2. The stuff pulse inserted on the low speed side is extracted and frequency synchronization is achieved with the low speed digital signal.

Further, after passing through the delay section 4, the low-speed side digital signal is data-compared with the above-mentioned frequency-synchronized low-speed signal coming from the high-speed side in the comparison section 3, and a comparison signal ε is output.

At this time, the amount of time delay until the low-speed signal obtained by decomposing the high-speed side signal reaches the comparator 3 is determined by the detection time of the stuff signal that informs the removal of the stuff pulse in the separation unit 1 and the writing/reading of the buffer memory 2. Since the time varies depending on the time relationship, the delay control section 5 uses the comparison signal ε output from the comparison section 3 to synchronize the phase of the data strings from both low and high speeds each time.

Specifically, the delay control unit 5 receives the comparison signal ε, and outputs control signals cl and c2 to the buffer memory 2 for the high-speed side signal and the delay unit 4 for the low-speed side signal, respectively. Controls the amount of delay to be added to the signal, controls the reading start position of the digital signal written in the memory 2 in the buffer memory 2, and controls the amount of delay in the buffer memory 2 for the high-speed side signal. are doing. However, since the delay amount of the latter buffer memory 2 changes due to the stuff pulse extraction in the separating section 1, the phase relationship between writing and reading of the backup memory 2 changes, so the delay amount of the former delay section 4 is controlled by the control signal c2 each time. to achieve phase synchronization.

That is, by removing the stuff pulse (destuffing), the data written to the buffer memory 2 is advanced by one bit, so that the writing phase is one bit earlier than the reading phase.

[Problem that the invention seeks to solve]

In the conventional bit monitoring device, as described above, the delay amount of the delay unit 4 is variably controlled by the control signal c2 from the delay control unit 5 in order to synchronize the phase of the data string. Since the phase of the low-speed signal obtained by the low-speed signal constantly fluctuates due to the extraction of stuff pulses, the circuit of the delay control section 5 that compensates for this fluctuating phase each time is large in scale (and is not easy to configure).

Further, the variable width of the delay amount of the delay unit 4 for phase synchronization is n
If the number of bits exceeds n bits, add n bits to the communication path for monitoring.
/ When a fixed pattern of N bits (n = N) is streamed, the number of points at which phase synchronization can be obtained is not one, but multiple points, resulting in false synchronization, and accurate phase synchronization points cannot be obtained. When the fixed pattern shifts to a random pattern (data), a problem arises in that synchronization is lost and the pull-in operation starts again.

[Means for solving problems]

As a means of solving the above problem, the phase relationship between the low-speed data string and the high-speed data string is made constant during bit matching.As is clear from the time chart in Figure 2, the high-speed side signal Focusing on the fact that it is time to detect a stuff signal in the data string and remove the inserted stuff pulse, as shown in the block diagram of FIG. The setting is performed in synchronization with a stuffing signal that notifies removal of the stuffing pulse of the separation unit 1.

With this initial setting, the delay amount of the buffer memory 2 for the data string of the low speed signal obtained by decomposing the high speed side signal is determined by the read position, and also the delay section 4 column to be added to the low speed side signal is determined by the read position. and the data string of the signal from the high-speed side, and a counter 6 is provided to count the number of bit differences.

[Effect]

Since the initial settings for writing and reading high-speed side signals to and from the buffer memory 2 are performed in synchronization with the stuffing signal that informs the separating section 1 of the removal of stuff pulses, the low-speed signals obtained by decomposing the high-speed side signals are The amount of delay of the buffer memory 2 with respect to the data string is made constant. Furthermore, since the amount of delay of the delay group 4 that affects the low-speed side signal is fixed, the phases of the data string of the low-speed side signal and the data string of the signal from the high-speed side in comparison Z3 are synchronized. However, the bit positions are generally shifted from their correct positions.

The counter 6 counts the amount of shift of this bit position and sends the counted value to the buffer memory 2 as a read setting signal a for the buffer memory 2.

The buffer memory 2 resets the read start address using the setting signal a, corrects the mutual relationship between the bit positions of both data strings, and enables correct bit collation.

〔Example〕

FIG. 1 is a block diagram of a bit monitoring device of a stuff synchronous multiplex converter according to an embodiment of the present invention.

To describe the overall operation, the Skusoff synchronous multiplex converter W10
The 0 low-speed digital signals that are not frequency-synchronized and input to 0 are bundled by inserting stuff pulses in the stuff-synchronized multiplex converter 100, and are frequency-synchronized and converted into high-speed digital signals. Output.

A portion of each low-speed digital signal input to the stuff synchronous multiplex converter 100 is branched and guided to the bit monitoring device 10, where a certain delay is given by the delay section 4, and the signal is input to the comparison section 3. Ru.

Further, a part of the high-speed digital signal output from the stuff synchronous multiplex converter 100 is also branched and input to the separating unit 1 of the bit monitoring device 10.

The separation unit 1 of the bit monitoring device 10 decomposes the input high speed signal into a low speed signal of 1/n speed, and generates a stuff signal that indicates the position of the stuff pulse inserted on the low speed side of the stuff synchronous multiplexing device 100. The signal is detected from the data string, the stuff pulse is extracted, and a low-speed signal of the same series is output.

FIG. 2 shows a data string (a) of the low-speed digital signal input to the bit monitoring device 10 and a data string of the low-speed signal of the same series obtained from the high-speed digital signal output from the separation unit 1 of the bit monitoring device 10. The phase relationship between (b) and the stuffing signal (c) that indicates the point in time when stuffing synchronization has been performed is shown. As shown in this figure, the data string (a) of the low-speed digital signal and the data string (b) of the low-speed digital signal of the same series obtained by separating it from the high-speed signal have the same phase relationship at the time the stuff signal is detected. become.

The output data of the separation unit 1 of the bit monitoring device 10 is used to initialize the bathophore memory 2 (buffer memory write counter preset)
and then written.

The data on the high speed side written in the buffer memory 2 is read out appropriately and inputted to the comparison section 3, and the comparison section 3
It is compared with the data string of the low-speed side signal input from the delay section 4. The two data strings input to the comparator 3 are written in the buffer memory 2 on the high-speed side in synchronization with the stuff signal, so the phases of the data strings are synchronized with each other, but both data strings are in phase with each other. Corresponding bit positions in columns do not necessarily match. In general, it is normal for the deviation to occur in units of bits.

The counter 6 counts this bit-by-bit deviation, and resets the starting position of the read address in the buffer memory 2 based on the count output. This resetting can be performed by presetting the read counter of the buffer memory 2.

In the buffer memory 2, the number of time slots between memory writing and reading is set in synchronization with the stuff signal that indicates that the phase relationship between the data strings of the low-speed side signal and the high-speed side signal is constant, so the amount of delay is reduced. By setting the delay section 4 on the low speed side to a constant value in advance, the phase synchronization of the data strings on the high speed side and the low speed side can be achieved.

As a circuit, a counter 6 is driven by the comparison signal ε output from the comparator 3, and the number of bit differences between the data string from the low speed side and the data string from the high speed side is counted, and the sofa memory is determined by the counted value. 2 reading? a constant (g number a is sent to the buffer memory 2 and the buffer memory 2 is reset. Correct bit-by-bit matching is possible with phase synchronization.

As the bit comparison monitoring device, it is only necessary to provide the counter 6 at the output stage of the comparing section 3, so that the circuit configuration of the bit comparison monitoring device is simplified. [Effects of the Invention] As described above, according to the present invention, the circuit configuration of the bit matching monitoring device of the stuff synchronous multiplexing device is simplified, false synchronization is eliminated, and bit matching is reliably performed. can get.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a bit matching monitoring device of a stuffed synchronous multiplexing device according to an embodiment of the present invention, and FIG. 2 is a block diagram for explaining the operation of the bit matching monitoring device of a stuffed synchronous multiplexing device of the present invention. FIG. 3 is a block diagram of a bit collation monitoring device of a conventional stuff synchronous multiplex converter. 1 and 3, 1 is a separation unit, 2 is a buffer memory, 3 is a comparison unit, 4 is a delay unit, 5 is a delay control unit, 6 is a counter, 10 is a bit matching monitoring device, and 100 is a stuffer. This is a synchronous multiplex converter.

Claims (1)

[Claims] A stuff pulse is inserted into n asynchronous low-speed digital signals to synchronize them, convert them to high-speed digital signals, and send them out. Both signals before and after conversion by the stuff synchronous multiplex converter (100) are compared and verified bit by bit. In the bit matching monitoring device (10), a separating unit (1) separates the high-speed digital signal into 1/n and extracts stuff pulses.
, a buffer memory (2) that performs initial settings for writing and reading in synchronization with the stuffing signal that indicates the inserting position of the stuffing pulse output from the separating section (1), and a buffer memory (2) that performs initial settings for writing and reading, and a certain delay time with respect to the low-speed digital signal. The delay part that gives (
4), a comparator (3) for comparing the data string output from the delay section (4) and the data string output from the buffer memory (2), and a bit of the data string output from the comparison section (3). a counter (6) for counting the number of differences, the counter (6)
A bit collation monitoring device for a stuff synchronous multiplex conversion device, characterized in that phase synchronization between bits is achieved by resetting readout of the buffer memory (2) according to a count value of .