JPH04192637A - Stuff multiplex converter - Google Patents

Abstract

PURPOSE:To improve the reliability of communication by using a dummy bit of the stuff multiplex system so as to send a code for error detection thereby monitoring a code error of a transmission line without deteriorating the transmis sion efficiency. CONSTITUTION:Error detection code addition means 6, 7 which make calculation to obtain an error detection code in the unit of blocks blocks by a stuff bit with respect to a synchronizing signal and insert the result to the stuff bit to form a transmission signal are provided to the sender side. Moreover, an extraction means 11 which extracts the stuff bit from the received transmission signal and an error detection means 13 which makes calculation in the unit of blocks blocked by the stuff bit with respect to the received transmission signal, extracts information of an error detection code from the stuff bit of the received transmission signal, compares it with the result of calculation so as to check the presence of the code error are provided to the receiver side. Thus, it is possible to monitor and detect the code error in the transmission line.

Description

[Detailed description of the invention]

[Purpose of the Invention (Industrial Field of Application) The present invention relates to a stuff multiplex converter that makes it possible to detect transmission line code errors. (Prior art) In the digital transmission system for wired transmission, multiple low-order group digital signals are time-division multiplexed to create a high-order group digital signal, which is transmitted, and the receiving side separates it and transmits it to the original signal. A multiplexing technique is used to obtain lower order group digital signals. This multiplexing of digital signals basically involves temporarily holding low-order group digital signals corresponding to the number of multiplexed signals in a buffer memory, and then changing each of the held low-order group digital signals to correspond to the speed of the high-order group side. This is done by sequentially reading out signals in accordance with a clock signal, and the multiplexed signal becomes a high-order group digital signal. At this time, a frame synchronization signal is inserted so that the position of the low-order group digital signal can be identified during separation on the receiving side. Such multiplex conversion includes stuff multiplexing in which the low-order group digital signals to be multiplexed and the clock frequencies of the low-order group digital signals are not synchronized, and synchronous multiplexing in which the low-order group digital signals are synchronized. Here, consider stuff multiplexing, which is a multiplex conversion method in which the low-order group digital signals to be multiplexed and the clock frequencies of the low-order group digital signals are not synchronized. Stuff multiplexing is also called asynchronous multiplexing, and its principle is that a signal with n times a frequency slightly higher than the frequency of each of the n unsynchronized low-order group input digital signals is selected as the high-order group clock frequency fO. An extra pulse (stuff pulse) corresponding to the frequency difference between fo and the own digital signal frequency is added to each of the next group input digital signals to match the output frequencies. If information indicating that a surplus pulse has been inserted is sent separately, the receiving side can restore the original data by removing the surplus pulse based on this information. Inserting this surplus bit is called stuffing, and removing it is called destuffing. Here, as mentioned above, the multiplexed signal is divided into sections called frames, and this is done in order to be able to recognize which channel of the lower-order group signal a certain bit in the multiplexed signal belongs to. This is because it is necessary to transfer various types of inter-office information. A frame synchronization pulse is placed in each frame, and by detecting this pulse, the frame separation is confirmed, that is, frame synchronization is established. An example of the process of obtaining multi-frames is shown in Figure 6 (a
) is the surplus bit V corresponding to the surplus pulse.
is inserted, and empty bits are further provided for service bits, and the signal is converted into a signal as shown in FIG. 6(b). Combining this with the service bit string of FIG. 6(C) results in FIG. 6(d). Here, F is a frame synchronization pulse train, usually “0”
However, during stuffing, it becomes "1", indicating that an extra bit is inserted at the V position. When multiple low-order group signals are subjected to similar processing and bit multiplexed, a multi-frame is obtained. FIG. 6(e) shows an example of a multiframe in the case of two-way multiplexing. Incidentally, Fl is a frame synchronization pulse, CI is a stuff control bit of the i-th channel, Ii is an information bit of the i-th channel, and Vl is a surplus bit of the i-th channel. By the way, the stuff multiplex conversion device, which is a device for multiplexing and outputting stuff in this manner, has not conventionally added check bits for error detection. Therefore, even if a code error occurs in the transmission path, there is a problem in that the receiving side cannot detect this error. In addition, the quality of the transmission path is checked, and if the quality deteriorates, an alarm is issued. One way to monitor this quality is to have the receiving device side check the bits expected from the received signal sequence (for example, There is a method that monitors the bits used for frame synchronization (bits for frame synchronization) and monitors the error rate of the transmission path based on errors in those bits, but according to this method, only certain bits in the transmitted data are monitored. Therefore, there was a problem in that the error rate of the transmission path could not be properly monitored. [Problems to be Solved by the Invention] In the asynchronous time division multiplexing system, synchronization is achieved using stuff pulses. It is said to synchronize the signal to a higher bit rate. Conventional stuff multiplexing converters that use these stuff bits do not monitor errors at all, or if they do, they only monitor certain specific bits. Therefore, even if the transmission path deteriorates and a code error occurs, the abnormality cannot be detected, resulting in a lack of reliability. Therefore, an object of the present invention is to eliminate this problem and provide an error detection method that can monitor and detect code errors on a transmission path. [Configuration of the Invention (Means for Solving the Problem) In order to achieve the above object, the present invention is configured as follows. In other words, the signal is synchronized to a predetermined transmission speed by inserting stuff bits into the multiplexed original signal,
In a stuffed multiplex communication system that transmits the synchronized signal as a transmission signal, and also separates the received transmission signal and removes stuff bits to restore it, the first invention provides a transmitting side with the synchronized signal. An error detection code adding means is provided which performs a calculation to obtain an error detection code for each section separated by the stuff bits, and inserts the result into the stuff bits as a transmission signal, and the receiving side is provided with an error detection code adding means that performs a calculation to obtain an error detection code for each section separated by the stuff bits. an extraction means for extracting stuff bits from a signal; and an arithmetic function for performing the calculation on the received transmission signal in units of sections delimited by stuff bits detected based on the output of the extraction means;
an error detection means having a check function for extracting information on the error detection code from the stump bits of the received transmission signal and comparing the information with the calculation result obtained by the calculation function to check for the presence or absence of a code error; and configure it. Further, a second invention provides a parity operation in which the transmitting side performs a parity operation on the synchronized signal in units of sections separated by the stuff bits, and inserts the result into the stuff bits to obtain a transmission signal. additional means are provided, on the receiving side, an extraction means for extracting stuff bits from the received transmission signal; and an interval unit delimited by the stuff bit detected based on the output of the extraction means for the received transmission signal. A check function that extracts information on the parity calculation result from the stuff bits of the received transmission signal and compares it with the parity calculation result obtained by the calculation function to check for code errors. and a parity error detection means. Further, the third invention provides a transmitting side with a CRC code every time the number of stuff bits added to the multiplexed original signal reaches a predetermined number.
CRC frame bit adding means for adding frame bits, and the C1? Cyclic redundancy check code inserting means for performing a cyclic redundancy check calculation in units of sections separated by C frame bits and inserting the calculation result into stuff bits in the next section of the section to generate a transmission signal, The side includes a CRC frame bit detection means for detecting CRC frame bits from the received transmission signal, and performs a periodic redundancy check operation on the transmission signal in units of sections separated by the detected CRC frame bits, and uses the results of this operation as a next step. A CRC error detection means is provided for detecting a transmission error by comparing with cyclic redundancy check operation result information obtained from stuff bits in data in the interval. (Function) In the case of the first and second configurations of the device with this configuration, the transmitting side multiplexes lower group data from multiple lower group lines including stuff bits (surplus and soto). ,
Stuff bits are used as dummy bits, error detection code calculations or parity calculations are performed for each section separated by the stuff bits, and this is inserted into the dummy bits and transmitted to the upper group as a transmission signal. In addition to extracting dummy bits and sotos from the received transmission signal from the upper group, parity calculation is performed on the received data in intervals separated by stuff bits, and information on the error detection code or the parity calculation result obtained from the dummy bits is obtained. Compare and check for code errors. In this way, in the present invention, on the transmitting side, an error detection code is calculated for all data at each interval when stuffing occurs, and information on the result of this calculation is transmitted using stuff bits. The error detection code is calculated and compared with the received error detection code information to detect transmission errors, and the error detection code information is added. Since we have made it possible to check based on this, it is now possible to check the occurrence of code errors in received data, which not only improves the reliability of transmission, but also enables accurate error rate monitoring. In addition, error checking now adds error detection code information to dummy bits using stuffed bits, so the code on the transmission path can be adjusted without affecting the transmission efficiency of the stuffing multiplexing device. Error rate can be monitored. Further, in the third invention, stuffing bits are inserted into the multiplexed original signal to generate a transmission signal synchronized to a predetermined transmission rate, and the transmitting side transmits a plurality of lower group data including the stuffing bits. At the same time as multiplexing, CRC frame bits are added every time the stuff bits reach a predetermined number, and a cyclic redundancy check (CRC) is performed on the multiplexed data in units of sections separated by the CRC frame bits.
The calculation result is inserted into the stuff bits in the next section of the section and transmitted together with the multiplexed data, and the receiving side detects the CRC frame bits from the transmitted data and checks the CRC frame bits. Transmission errors are detected by calculating the CRC of the transmitted data in units of sections separated by frame bits, and comparing the calculation results with the CRC obtained from the star/soft bits in the data in the next section. Since transmission errors are detected by CRC check,
It becomes possible to detect deterioration of the transmission path when it occurs, which not only improves reliability but also improves C
Since the RC operation result is inserted into the dummy stuff bits and sent, the bit error rate of the transmission path can be monitored without reducing the transmission efficiency of the stuff multiplex converter. As explained above, since the present invention transmits code information for error detection using dummy bits of the stuff multiplexing method, code errors on the transmission path can be monitored without reducing transmission efficiency, etc. It is possible to provide a staff multiplex conversion system that can dramatically improve communication reliability. (Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram of a transmission system showing an embodiment of the present invention, in which 1 is lower group data, 2 is a transmission memory, 3 is a stuff control circuit, and 4 is a transmission timing. A pulse generating circuit, 5 a stuff pulse, 6 a multiplexing circuit, 7 a parity calculation circuit, and 8 upper group data. Of these, the transmission memory 2 is a buffer memory provided for each transmission line, and is used to sequentially store and temporarily hold the lower group data 1 transmitted via each lower line. Further, the transmission timing pulse generation circuit 4 generates timing pulses for driving at a predetermined period, and the stuff control circuit 3 compares the writing speed and the reading speed to the transmission memory 2 and determines the writing speed. is slower than the readout speed, it operates to generate stuff pulses 5 at predetermined timings based on timing pulses of a predetermined frequency generated by the transmission timing pulse generation circuit 4. The multiplexing circuit 6 is operated by the timing pulse output from the transmission timing pulse generating circuit 4, and the multiplexing circuit 6 operates by controlling the lower group lines (transmission lines) for n lines.
is connected, receives data from each of these lower group lines via the transmission memory 2, multiplexes these lower group data 1, receives frame pulses to generate frame bits, and receives stuff pulses to generate dummy data. It has a function of multiplexing bits (stuff bits) and the like and then sending it to the parity calculation circuit 7. The parity arithmetic circuit 7 performs parity arithmetic on a section divided by the stuff pulses 5 from the stuff control circuit 3, multiplexes the parity arithmetic results on the dummy bits, and sends out the result as upper group data 8. The above is the configuration of the transmission system. Next, the configuration of the receiving system is shown. FIG. 2 is a block diagram showing an embodiment of the reception system in the apparatus of the present invention, in which 1 is lower group data, 9 is a frame synchronization generation circuit, 10 is a reception timing pulse generation circuit, 11 is a destuff control circuit, 1
2 is a destuff pulse, 3 is a parity error detection circuit, 14 is error information, 15 is a separation circuit, and 16 is a reception memory. Among these, the frame synchronization generation circuit 9 detects a frame pattern from the received upper group data 8 and generates a synchronization pulse, and the reception timing pulse generation circuit IO receives this synchronization pulse and generates a reception timing pulse. It happens. The destuffing control circuit 11
operates in response to a reception timing pulse from the reception timing pulse generation circuit IO, and when it detects a stuff control bit from the received upper group data 8, it generates a destuff pulse 1 to remove the stuff bit (dummy bit).
2. Further, the parity error detection circuit 13 performs a parity operation on the received upper group data 8, and compares it with the parity operation result inserted into the dummy bit to detect the presence or absence of an error. The parity error detection circuit 13 has a function of outputting error information 14 when a parity error is detected as a result of the parity check. The separation circuit 15 is a reception timing pulse generation circuit I.
It operates in synchronization with the timing pulse from O, separates the received upper group data 8, and outputs the separated data for each lower group data. The reception memory 16 is a buffer memory provided for each lower group data, and receives and temporarily holds the lower group data separated and outputted for each lower group data by the separation circuit 15, and also outputs a destuff pulse. When received, the output data from the separation circuit 15 is captured (written) into the reception memory 16 in order to drop starvation pits accordingly.
It has a function to suppress this and a function to perform reading in synchronization with the reception timing pulse. Receiving memory 1B
The data read from is the lower group data 1. The operation of this device having such a configuration will be explained. First, to explain the operation of the transmission system, the lower group data 1 sent via the transmission line is taken into the transmission memory 2 corresponding to the transmission line and held at - time, and the multiplexing circuit 6 Data is sequentially read from memory 2 and multiplexed. At this time, the stuff control circuit 3 compares the writing speed and the reading speed to the transmission memory 2, and if the writing speed is slower than the reading speed, the stuff control circuit 3 uses a timing pulse of a predetermined frequency generated by the transmission timing pulse generation circuit 4. Stuff pulse 5 is generated at each predetermined timing determined by . In other words, in stuff multiplexing, the speed of lower-order group data 1 sent via the transmission line is somewhat slower than the speed at which it is read from the transmission memory 2, so there is a shortage of data, so stuff bits are inserted to match the speed. In order to do this, stuff pulses 5 are generated at predetermined timings and applied to the multiplexing circuit 6. The multiplexing circuit 6 is connected to n lower group lines (transmission lines), and the transmission timing pulse generating circuit 4 is connected to the multiplexing circuit 6.
It operates in synchronization with timing pulses from the lower group lines, takes in data from these lower group lines through the transmission memory 2, multiplexes these lower group data 1, and further adds frame patterns, dummy bits (stuff bits), etc. After multiplexing, it is sent to the parity calculation circuit 7. Further, the parity calculation circuit 7 receives the multiplexed data output from the multiplexing circuit 6 and the stuff pulse 5 from the stuffing control circuit 3, and divides the multiplexed data by the star/software pulse 5. A parity calculation is performed for the section, and the parity calculation result is multiplexed onto the dummy bits of the multiplexed data and sent as upper group data 8. In this way, the transmitting side multiplexes the lower group data from multiple lower group lines including the stuff bits, performs parity calculation for each section separated by stuff pulses, and uses the dummy bits, that is, the stuff bits. The transmission frame is inserted into the frame and transmitted to the upper group. Therefore, after each lower group data is multiplexed including stuff bits, parity including the stuff bits is added and transmitted. On the other hand, on the receiving side, the upper group data 8 received via the transmission path is sent to a separation circuit 15 and a parity error detection circuit 13.
and is applied to the frame synchronization generation circuit 9. Then, the frame synchronization circuit 9 detects a frame pattern from the upper group data 8 and establishes synchronization. In this case, the frame synchronization circuit 9 generates a frame synchronization pulse in synchronization with the frame synchronization pattern and supplies it to the reception timing pulse generation circuit 10. Thereby, the reception timing pulse generation circuit 10 operates in synchronization with this frame synchronization pulse, and generates a timing pulse synchronized with the reception data. The generated timing pulse is then applied to the destuff control circuit 11 and the separation circuit 15. As a result, the separation circuit 15 operates in synchronization with the timing/curse from the reception timing pulse generation circuit 10, and separates the received upper group data 8 into data for each lower group data, The corresponding received memo will be output on January 6th. That is, by separating the upper group data 8, each lower group data is separated into data for each channel, so the separated data is output to the reception memory 16 corresponding to the channel corresponding to the data and held. That will happen. Further, the destuff control circuit 11 detects the star/rough control bi-soto in the received upper group data 8, and synchronizes with the timing pulse output from the reception timing pulse generation circuit 1O. The position of the dummy node in the upper group data 8 is detected, and the desta node node 12 is outputted accordingly. Further, the parity error detection circuit 13 receives the destuffing pulse 12 from the destuffing control circuit 11 and performs a parity operation on the received upper group data 8 using the period until the next receiving the destuffing pulse 12 as a break. That is, parity calculation is performed on the received upper group data 8 in order to perform a parity check similar to that in the transmission system in units of sections in which stuff bits are inserted. Then, the parity error detection circuit 18 compares the content of the parity bit carried on the dummy bit with the result of the above parity operation, and if the comparison result is different, it is assumed that a code error has occurred in the transmission path. The destuff pulse 12 is also given to the reception memory 16, and the reception memory 16 is given the destuff pulse 12. During this time, the acquisition of output data from the separation circuit 15 is interrupted.The generation timing of this destuff pulse 12 corresponds to the position of the stuff bit in the data output from the separation circuit 15. As a result, destuffing can be performed.In this way, the lower group data 1 of each channel is separated by the separation circuit 15, destuffed, and held in the reception memory 16.
is read from each reception memory 16 at the transmission rate of the lower group, and is sent to the lower group. In this way, in a communication system that performs stuff multiplexing for communication, the transmitting side multiplexes lower group data from multiple lower group lines including stuff bits (surplus bits), and uses the stuff bits as dummy bits. A parity calculation is performed for each section separated by stuff bits, and this is inserted into dummy bits and transmitted to the upper group in a transmission frame.On the receiving side, the dummy bits are extracted and the received data is separated by stuff bits. Since the parity calculation is performed in each interval and compared with the parity calculation result information obtained from the dummy bits to check for code errors, it is now possible to check the occurrence of code errors in the received data, and the transmission In addition to improving the reliability of data processing, it has also become possible to monitor error rates with high accuracy.Furthermore, error checking has been improved by adding parity information to dummy bits using stuff bits. Therefore, without affecting the transmission efficiency of the staff multiplex converter,
The bit error rate of the transmission path can be monitored. Also, since the interval at which stuff pulses occur is not constant, the interval at which code errors are monitored is not constant, but it will not be used on lines with extremely poor transmission path quality (about 10-3). It can be considered that the number of errors that occur in one section of the section where errors are monitored is one. In addition, since code information for error detection is transmitted using dummy bits in the stuff multiplexing system, code errors on the transmission path can be monitored without reducing transmission efficiency. Since it uses dummy bits, there is no change in the frame structure (it can also be used with conventional stuff multiplex conversion devices).

[Second Embodiment] The method described above involves inserting parity information into dummy bits and detecting code errors in transmission by parity checking. In addition to this method, a method for detecting code errors in transmission using a CRC check can also be considered, and this method will be explained below. Here, CRC (Cyclic Redundancy)
Check is one of the error detection methods called cyclic redundancy test or periodic test, and is a test method used in data transmission, magnetic disks, etc.
In this method, input data is divided by a certain formula, the remainder is added as a check code, and transmitted or written, and when receiving or reading, an inverse calculation is performed to determine whether the data is correct or incorrect. In the present invention, on the transmitting side, an interval in which stuff pulses occur n times, that is, an interval in which stuff bits are inserted 0 times, is defined as one interval, and (n-1) stages of CRC calculation are performed to remove stuffing dummy bits. CRC bits and a bit indicating a frame position for starting CRC calculation are inserted and transmitted. A similar CRC check is performed on the receiving side,
Errors are detected by comparing the CRC calculation result with the sent CRC bits. Generally, the intervals at which stuff pulses are generated are not constant, but since the positions where stuff pulses are generated can be determined on both the transmitting and receiving sides, CRC calculations can be performed correctly. FIG. 3 is a block configuration diagram of a transmission system showing an embodiment of the present invention employing a CRC check system.
Components that are the same as those in the figures are given the same reference numerals, and their descriptions will be omitted. 1 is lower group data, 2 is a transmission memory, 3 is a stuff control circuit, 4 is a transmission timing pulse generation circuit, 5 is a stuff pulse, 6 is a multiplexing circuit, 8 is upper group data,
These are basically the same as those explained in FIG. Further, 21 is a CRC frame pulse generation circuit, and 22 is a C
RC calculation circuit, 23 is CRC frame bit, 24 is C
RC frame pulse, 25 are CRC bits. The CRC frame pulse generation circuit 21 counts the stuff pulses output from the stuff control circuit 3, and generates a CRC frame bit 23 for delimiting the range of CRC calculation once every n times. The CRC frame bits 23 generate a simple frame pattern, such as a 0°1 alternating pattern. Further, the CRC calculation circuit 22 has a (n - 1) order generation polynomial, and calculates the generation polynomial from the position of the CRC frame pulse 24 output from the CRC frame pulse generation circuit 21 for the upper group data 8. starts, calculates up to the bit immediately before the next frame pulse 24, and uses the calculation result as (n-1) CRC bits 2.
5 and is output to the multiplexing circuit 6. The multiplexing circuit 6 inserts this CRC bit 25 into (n-1) dummy bits between the next CRC frame pulse 24 and the next CRC frame pulse 24 . In addition, in the multiplexing circuit 6, due to the frame structure of the stuff multiplexing method,
K pieces (for k channels) of lower group data 1 are multiplexed and sent as upper group data 8. FIG. 4 shows the receiving side of an embodiment of the present invention, where 1 is lower group data, 8 is upper group data, 9 is a frame synchronization circuit,
10 is a reception timing pulse generation circuit, 11 is a destuff control circuit, 12 is a destuff pulse, and 16 is a reception memory. These are basically the same as those explained in FIG. 31 is a CRC frame synchronization circuit, 32 is a C
RC error detection circuit, 33 is CRC frame pulse, 3
4 is error information. The CRC frame synchronization circuit 9 receives the received upper group data 8 and the destuff pulse 12 from the destuff control circuit 15, and extracts a bit string from the upper group data 8 in synchronization with the destuff pulse 12. Extract a dummy bit string from the data, and use C from that dummy bit string.
It has the function of detecting RC frame bits, establishing CRC frame synchronization, and outputting a CRC frame pulse 38. Further, the CRC error detection circuit 32 receives the destuff pulse 12 from the destuff control circuit 11, the received upper group data 8, and the CRC from the CRC frame synchronization circuit 9.
By using the frame pulse 33 as input and starting CRC calculation every time the CRC frame pulse 33 is received for the upper group data 8, the CRC calculation is performed for each section separated by the CRC frame pulse 33, and the CRC calculation result and the next CR that is placed on the dummy bit of the frame
It has a function of comparing the data with the C bit, and if the result is incorrect, it is assumed that a code error has occurred in the transmission path, and error information 19 is output. Here, the frame synchronization circuit 13 detects a frame slam from the received upper group data 8 to establish synchronization, and the reception timing pulse generation circuit 14 generates timing synchronized with the reception data. Further, a dummy bit in the data is detected by the timing output from the reception timing pulse generation circuit 14 and the destuff control circuit 15,
Outputs destuff pulse 1B. The CRC frame synchronization circuit 17 extracts a dummy bit string from the data using the destuff pulse 16, detects a CRC frame bit from the dummy bit string, and
Establish RC frame synchronization, CRC frame Hals 10
Output. Furthermore, the CRC error detection circuit 18
A CRC calculation is performed for each interval in which the CRC frame pulse 10 is generated, and the result and the CI? If the result is incorrect, it is assumed that a code error has occurred in the transmission path, and error information 34 is output. Next, the operation of this device having such a configuration will be explained. First, the transmission system will be described. Lower group data 1 sent via a transmission line is taken into a transmission memory 2 corresponding to the transmission line and temporarily held. The multiplexing circuit 6 converts the lower group data 1 taken into these transmission memories 2 into
Data is sequentially read from the transmission memory 2 and multiplexed. At this time, the stuff control circuit 3 compares the writing speed and the reading speed to the transmission memory 2, and if the writing speed is slower than the reading speed, the stuff control circuit 3 uses a timing pulse of a predetermined frequency generated by the transmission timing pulse generation circuit 4. Stuff pulse 5 is generated at each predetermined timing determined by . In other words, in stuff multiplexing, the speed of lower-order group data 1 sent via the transmission line is somewhat slower than the speed at which it is read from the transmission memory 2, so there is a shortage of data, so stuff bits are inserted to match the speed. In order to do this, stuff pulses 5 are generated at predetermined timings and applied to the multiplexing circuit 6. On the other hand, the stuff pulse 5 is input to the CRC frame pulse generation circuit 22.
counts the input stuff pulses, and n
Once a time, CI? Generates CRC frame bits 23 for delimiting the range of C operations. As the CRC frame bits 23, for example, a simple frame pattern such as a 0.1 alternation is generated. The generated CRC frame bits 23 are given to the CRC calculation circuit 22. CI? The C arithmetic circuit 22 has a generator polynomial of (n-1) order, and performs CRC on the upper group data 8 output from the multiplexing circuit 6.
CRC calculation is started from the position of frame pulse 24. Upon receiving the next CRC frame bit 23, the CRC calculation circuit 22 converts the calculation results up to this point into data (n
C1? CRC calculation is started from the position of C frame pulse 24. As a result, the CRC calculation circuit 22 determines whether the CI? When C frame pulse 24 is received, CRC calculation is performed up to the bit immediately before the next frame pulse and CI? The C operation result can be output as (n-1) CRC bits 25. Then, this CRC operation result is passed to the multiplexing circuit 12, and the multiplexing circuit 6 inserts this CRC operation result into the dummy bit (stuff bit) in the upper group data 8 that is currently being output. That is, CR in the previous frame
The C operation result is now inserted into (n-1) dummy bits in the interval between the given CRC frame pulse and the next given CRC frame pulse. The multiplexing circuit 6 multiplexes the lower group data for k channels using a stuff multiplexing frame structure, and sends out the upper group data in the form of multiplexed frame bits and dummy bits. Therefore, after each lower group data is multiplexed including stuff bits, parity including the stuff bits is added and transmitted. Next, the operation on the receiving side shown in FIG. 4 will be explained. On the receiving side, the upper group data 8 received via the transmission path is applied to a separation circuit 15, a CRC frame synchronization circuit 31, a frame synchronization circuit 9, and a CRC error detection circuit 32. Then, the frame synchronization circuit 9 detects a frame pattern from the upper group data 8 and establishes synchronization, and in response to this, the reception timing pulse generation circuit 10 generates a timing pulse synchronized with the reception data. The generated timing pulse is then applied to the destuff control circuit 11 and the separation circuit 15. As a result, the separation circuit 15 operates in synchronization with the timing pulse from the reception timing pulse generation circuit 10, separates the received upper group data 8, and separates each lower group data into separate data to correspond to the received upper group data 8. Output to reception memory 16. That is, by separating the upper group data 8, each lower group data is separated into data for each channel, so the separated data is output to the reception memory 1B corresponding to the channel corresponding to the data and held. That will happen. Further, the destuffing control circuit 11 detects the stuffing control bit in the received upper group data 8, and while synchronizing with the timing pulse output from the reception timing pulse generation circuit 10, the destuff control circuit 11 detects the stuffing control bit in the received upper group data 8. The CRC frame synchronization circuit 9 detects the position of the dummy bit in the received upper group data 8 and outputs the destuff control circuit 15 accordingly. A dummy bit string is extracted from the data by extracting a bit string from the upper group data 8 in synchronization with the destuff pulse 12, and detecting a CRC frame bit from the dummy bit string. It establishes frame synchronization and outputs a CRC frame pulse 33.The CRC error detection circuit 32 also outputs the CRC frame pulse 33, the destuff pulse 12 from the destuff control circuit 11, and the received upper group data 8. and received
By starting the CRC calculation every time the CRC frame pulse 33 is received for the upper group data 8, the CRC calculation is performed for each section separated by the CRC frame pulse 33, and the CRC calculation result is placed on the dummy bit of the next frame. If the result is incorrect, it is assumed that a code error has occurred on the transmission path, and error information 34 is output. In this way, in the CRC frame synchronization circuit 17,
A dummy bit string in the data is extracted using the destuff pulse IB, a CRC frame bit is detected from the dummy bit string, CRC frame synchronization is established, and a CRC frame pulse 10 is generated according to the establishment of this synchronization.
The RC error detection circuit 18 performs a CRC calculation for each interval in which the CRC frame pulse lO is generated, and compares the result with the CRC bits placed on the dummy bits of the next frame.If the result is incorrect, It is assumed that a code error has occurred on the transmission path, and error information 34 is output. This makes it possible to notify the occurrence of a code error. Here, the destuff pulse 12 is also given to the reception memory 16, and the reception memory 16 receives the destuff pulse 12.
When is given, the acquisition of output data from the separation circuit 15 is interrupted during that time. This destuff pulse 12
Since the timing of occurrence corresponds to the position of the stuff bit in the data output from the separation circuit 15, destuffing can be performed. In this way, the lower group data 1 of each channel separated by the separation circuit 15, destuffed, and held in the reception memory IB is read out from each reception memory 1B at the transmission speed of the lower group, thereby being transferred to the lower group. Sent. FIG. 5 is a timing chart for explaining the operation of an embodiment of the present invention, in which (a) shows the stuffable position;
(b) is stuff pulse 5, F is CRC frame bit, C11-C15, C21-C25. C3l-C35 are CRC bits, 41.42.43 are C
This is an interval in which RC calculation is performed. The operation of the second embodiment described above will be explained with reference to the timing chart of FIG. Note that an example in which the CRC is of 5th order will be explained here. If the CRC is of the 5th order, 5 CRC bits are required, and together with the frame bit for indicating the start position of the CRC calculation, 6 bits constitute one section. On the transmitting side, the generated stuff pulses 5 are counted and a CRC frame bit F is added every 6 bits. The CRC calculation circuit 22 performs a CRC on the upper group data 8 to be transmitted.
The calculation is started from the beginning of the frame bits, the CRC is calculated over the entire section 41, and the result is multiplexed on the CRC bits C21 to C25, which are the CRC bits of the next frame. Similarly, in section 42, CRC computation is started from the beginning of the frame bits of the section 42 for the upper group data 8 to be transmitted, and the result of the computation is multiplexed onto CRC bits C3l-C35, which are the CRC bits of the next frame. Repeat this operation sequentially. On the other hand, on the receiving side, after establishing main frame synchronization of the stuff multiplexing system, the position of the stuff pulse 5 shown in FIG. 5(b) is detected and CRC frame synchronization is established using the CRC frame bit F. The CRC error detection circuit 32 detects the CRC frame bit F.
The CRC calculation is started from the beginning of the received upper group data 8, and the result of the CRC calculation for section 41 is latched. Then, the CRC error detection circuit 32 detects the CRC bits C21 to C21 from the frame of section 42 which is the next frame.
25 is extracted and compared with the latched result, and if even 1 bit differs, error information 34 is output. Error checking is performed by repeating this operation frame by frame. In this way, in a stuffed multiplex communication system that synchronizes to a predetermined transmission rate by inserting stuffing bits into the multiplexed original signal, the transmitting side multiplexes a plurality of lower-order group data including the stuffing bits, and A CRC frame bit is added every time the number of bits reaches a predetermined number, and a cyclic redundancy check (CRC) is performed on the multiplexed data in units of sections separated by the CRC frame bits.
) and inserts the calculation result into the stuff bits in the next section of the section to transmit it together with the multiplexed data, and the receiving side detects the CRC frame bits from the transmitted data and reads this data. C)? C
Transmission errors are detected by calculating the CRC of the transmitted data in units of sections separated by frame bits, and comparing this calculation result with the CRC obtained from the stuff bits in the data in the next section. Since transmission errors are detected by CRC checking, it becomes possible to detect deterioration of the transmission path when it occurs, and improve reliability.
Since the CRC calculation result is inserted into the dummy stuff bits and sent, the bit error rate of the transmission path can be monitored without reducing the transmission efficiency of the stuff multiplexing converter. Note that the interval at which stuff pulses are generated, that is, the interval at which stuff bits are inserted, varies depending on the speed of the multiplexed lower group data and the asynchronous state, so it is not constant, so the interval at which code errors are monitored is not constant. However, since it is not used on a line where the quality of the transmission path is extremely poor, it is safe to assume that there is only one error occurring in one section of error monitoring, and the monitoring time to calculate the error rate is shorter than the CRC calculation. If it is sufficiently long compared to one section, it is possible to correctly calculate the bit error rate of the transmission path. It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, but can be implemented with appropriate modifications within the scope without changing the gist thereof. Furthermore, since the present invention uses dummy bits that were previously discarded to transmit error detection codes, there is no change in the frame structure, and therefore, it can be used with conventional stuff multiplex conversion devices. be. [Effects of the Invention] As explained above, the present invention uses dummy bits of the stuff multiplexing method to transmit error detection codes, so that code errors on the transmission path can be monitored without reducing transmission efficiency. It is possible to provide a staff multiplex conversion system that can dramatically improve communication reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a transmission system showing an embodiment of the present invention.
FIG. 2 is a block diagram of a receiving system showing an embodiment of the present invention.
FIG. 3 is a block diagram of a transmission system using a CRC check method which is another embodiment of the present invention, FIG. 4 is a block diagram of a reception system according to the present invention using the CRC check method, and FIG.
FIG. 6 is a timing chart for explaining the operation of an embodiment of the present invention using the RC check method, and FIG. 6 is a diagram for explaining an example of multiplexing. 1... Lower group data, 2... Transmission memory, 3...
stuff control circuit, 4... transmission timing pulse generation circuit, 5... stuff pulse, 6... multiplexing circuit,
7... Parity calculation circuit, 8... Upper group data, 9
... Frame synchronization circuit, 10 ... Reception timing pulse generation circuit, 11 ... Destuff control circuit, Engineering 2.
...Destack pulse, 13...Parity error detection circuit, 14, 34...Error information, 15...Separation circuit, 21...CRC frame pulse generation circuit, 23
...CRC frame bits, 22...CRC [IE
Circuit, 24...CRC frame pulse, 25...C
RC bit, 31...CRC frame synchronization circuit, 32
...CRC error detection circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 3 i', ti (c) Service bit string F'CFC Figure 6

Claims (3)

[Claims] (1) By inserting stuff bits into the multiplexed original signal, the signal is synchronized to a predetermined transmission rate, and this is transmitted as a transmission signal, and the received transmission signal is separated and the stuff bits are removed. In the stuffed multiplex communication system to be restored, the transmitting side performs an operation on the synchronized signal to obtain an error detection code for each section separated by the stuff bits, and inserts the result into the stuff bits. an error detection code adding means for adding a stuff bit to the received transmission signal, and the receiving side includes an extraction means for extracting stuff bits from the received transmission signal; an arithmetic function that performs the arithmetic operation in intervals divided by the detected stuff bits; extracts information on the error detection code from the stuff bits of the received transmission signal; and compares the information with the arithmetic result obtained by the arithmetic function; What is claimed is: 1. A stuff multiplex conversion device comprising: an error detecting means having a checking function for checking the presence or absence of a code error; (2) By inserting stuff bits into the multiplexed original signal, the signal is synchronized to a predetermined transmission rate, and this is transmitted as a transmission signal, and the received transmission signal is separated and the stuff bits are removed. In the stuffed multiplex communication system to be restored, the transmitting side has a parity operation that performs a parity operation on the synchronized signal in units of sections separated by the stuff bits, and inserts the result into the stuff bits as a transmission signal. Arithmetic addition means is provided, and the receiving side includes: an extraction means for extracting stuff bits from the received transmission signal; and a method for dividing the received transmission signal by stuff bits detected based on the output of the extraction means. an arithmetic function that performs parity arithmetic on a section-by-section basis; extracts information on the parity arithmetic result from the stuff bits of the received transmission signal; and compares the information with the parity arithmetic result obtained by the arithmetic function;
1. A stuff multiplex conversion device comprising: parity error detection means having a check function for checking the presence or absence of a code error. (3) Stuff multiplexing, which inserts stuff bits into the multiplexed original signal to create a transmission signal synchronized to a predetermined transmission speed, and while transmitting, the received transmission signal is separated, and the stuff bits are removed to restore it. In the communication system, the transmission side includes a CR that adds CRC frame bits every time the stuff bits added to the multiplexed original signal reach a predetermined number.
C frame bit addition means, and performs a periodic redundancy check operation on the multiplexed data in units of sections separated by the CRC frame bits, inserts the operation result into stuff bits in the section next to the section, and transmits it. CRC frame bit detection means for detecting CRC frame bits from the received transmission signal;
A cyclic redundancy check calculation is performed on the transmission signal in units of sections separated by C frame bits, and transmission errors are detected by comparing the calculation results with the cyclic redundancy check calculation result information obtained from the stuff bits in the data in the next section. C to detect
A stuff multiplex conversion device comprising an RC error detection means.