JPS63120426A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63120426A JPS63120426A JP26693886A JP26693886A JPS63120426A JP S63120426 A JPS63120426 A JP S63120426A JP 26693886 A JP26693886 A JP 26693886A JP 26693886 A JP26693886 A JP 26693886A JP S63120426 A JPS63120426 A JP S63120426A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- side wall
- semiconductor
- inp
- forward direction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000001020 plasma etching Methods 0.000 claims abstract description 11
- 238000003486 chemical etching Methods 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims abstract 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 5
- 239000007791 liquid phase Substances 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 abstract 4
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 abstract 2
- 238000000059 patterning Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 229910021620 Indium(III) fluoride Inorganic materials 0.000 description 2
- 241000408551 Meza Species 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法に関し、特に半導体レ
ーザ装置の反射ミラーをエツチングによ2 ti−>
り製造する方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a reflecting mirror of a semiconductor laser device by etching.
従来の技術
リアクティブイオンエツチング(RIE)法(d、エツ
チング特性に結晶方位依存性がないことから半導体レー
ザのミラー形成に適し広く用いられている。しかしマス
ク材との選択比が小さい場合あるいはマスクエツジが十
分垂直でない場合マスク後退効果と呼ばれる現象が生じ
、ミラーの垂直性を悪くする。ミラーの垂直性の良否は
半導体レーザの重要なパラメータであるしきい値電流や
微分量子効率に直接影響するので十分垂直性のよいミラ
ーを形成することが重要である。Conventional technology Reactive ion etching (RIE) method (d) is suitable and widely used for forming mirrors in semiconductor lasers because its etching characteristics do not depend on crystal orientation.However, when the selectivity with the mask material is small or the mask edge If the mirror is not sufficiently perpendicular, a phenomenon called mask recession effect occurs, which deteriorates the perpendicularity of the mirror.The perpendicularity of the mirror directly affects the threshold current and differential quantum efficiency, which are important parameters of semiconductor lasers. It is important to form a mirror with sufficient verticality.
これまでミラーの垂直性を確保するため例えば電子通信
学会技術研究報告5SD85−47(Vol。Until now, in order to ensure the verticality of the mirror, for example, the Institute of Electronics and Communication Engineers Technical Research Report 5SD85-47 (Vol.
85 & 110 ) に示されているような斜めR
IE法が考案されている。第2図は斜めR2Hを説明す
るための断面図であって試料7はInP10上にTiO
29をマスクとしてパターニングしたものであり、8は
斜め治具である。試料7は斜め治具8によりサセプタ1
3から0だけ角度をつけた状態でRIM装置のチャンバ
内に配置6される。なお・用いられる装置は通常の平行
平板型RIE装めである0
との状態で例えばC12ガスを用いてRIEを行なうと
加速電界は垂直、即ち試料7に対(〜ては0だけ斜めに
生じるからCI の活性種cj試料了に対[2てOな
る入射角をもって入射1−1その結果第3図に示すよう
なエツチング形状が得られる。85 & 110) as shown in
The IE method has been devised. FIG. 2 is a cross-sectional view for explaining the oblique R2H, and sample 7 is made of TiO on InP10.
It is patterned using 29 as a mask, and 8 is a diagonal jig. Sample 7 is attached to susceptor 1 using diagonal jig 8.
It is placed 6 in the chamber of the RIM device at an angle of 3 to 0. The equipment used is a normal parallel plate type RIE setup, and when performing RIE using, for example, C12 gas, the accelerating electric field is perpendicular to the sample 7 (since it is generated obliquely by 0). The active species of CI are incident 1-1 on the sample at an angle of incidence of 20. As a result, an etched shape as shown in FIG. 3 is obtained.
発明が解決しよう表する問題点
!−かじ上記の」、うな製造5が、では、第2図におい
てエツチングレートが場所によって異なり、例えばA部
、B部、0部の順にエソチレ−1・が速くなるという欠
点を有しており、このため大面積ウェハを用いた半導体
レー(ドのプロセスには不適旨な方法であった。さらに
第3図に示すように、ミラー面11け垂直性がよくなる
が、対向するミラー面12は逆に垂直性が悪くなること
から、との方法で半導体レーザ゛を製作するさい、片側
のニラ−は別途へき開等の方法で製造する必要かぁ−)
だ。The problem that the invention is trying to solve! - The above-mentioned Eel Manufacturing 5 has the disadvantage that the etching rate differs depending on the location in FIG. For this reason, this method was unsuitable for the process of semiconductor rays using large-area wafers.Furthermore, as shown in Fig. 3, the perpendicularity of the mirror surface 11 is improved, but the opposing mirror surface 12 is inverted. Since the perpendicularity deteriorates, when manufacturing a semiconductor laser using the method described above, is it necessary to separately manufacture the lance on one side by a method such as cleaving?
is.
問題点を解決するだめの手段
本発明は化学的−エツチングによりストライブ状のメ(
Jを形成1−、1′″、のメザの側壁面iRI E法に
よって11?的性のよいミラーに加二にする方法を提供
するものである。Means for Solving the Problems The present invention provides stripe-like mesh (
The present invention provides a method of forming a mirror with good 11- and 1'-inch characteristics using the iRIE method on the side wall surface of a meza of 1-, 1'''.
イ′1 月1
化学エツチングによるメザ形成のさい側壁面に順力向の
傾斜を牛[二せ[7,めでおくにとにより、斜めRIE
法と同様の効果を期待でき、またウェハを水−\17.
f(配置できることからエツチングのばらつきをなく
すことができ、さらに溝部の対向する側壁の両方のを重
重にすることができる。January 1: When forming a meza by chemical etching, the slope in the forward direction was created on the side wall surface by diagonal RIE.
The same effect as the method can be expected, and the wafer can also be soaked in water.
f (can be arranged, it is possible to eliminate variations in etching, and furthermore, it is possible to make both of the opposing side walls of the groove part heavier.
実施例
第1図は本所、明の一実施例の断面を示すものであって
、試t1と(〜て、n−I n P基板6上に、n −
InF3.InGaAsP5.P−InF3.PInG
aAsp2を順次液相成長しfCダブル・\ゾロ構コ1
5のJビタキゾヤルウェハが用いられている。第1図a
は前記エビタギンヤルウ。−ハにスパッタ法によりTi
O21を形成し、通常のホトリソグラフィ・−によって
、バターニングし7た状態を示i〜でいる。第1図すは
、図1aで示し5、/r、エビタギシャルウェハをTi
O21をマスクとしてBr2−CH30H(2重量%)
液でn−InP基板61で化学エツチングを行なった状
態を示す。ことでエツチング面は(111)而であり順
テーバがついている。この状態でc c7?4ガスによ
るRIE法でエツチングを行なうと第1図Cに示すごと
く垂直性は著しく改善された0
発明の効果
本発明によればウェハを水平においた状態でエツチング
を行なうため、ウェハ内のエツチングばらつきが小さく
大面積ウェハの使用が可能でありかつすべての側壁面の
垂直性かよくなることから半導体レーザの両端面にエツ
チドミラーを使用することが可能である。即ち、半導体
レーザの量産性が飛躍的に向上することになり、本発明
の工業的価値は非常に大きい。Embodiment FIG. 1 shows a cross section of an embodiment of the present invention, in which samples t1 and (n-I nP substrate 6, n-
InF3. InGaAsP5. P-InF3. PInG
Sequential liquid phase growth of aAsp2 to create fC double/Zoro structure 1
A No. 5 J Vitaki Zoyal wafer is used. Figure 1a
The above-mentioned Evitaginyaruru. - Ti by sputtering method
The state in which O21 was formed and patterned by ordinary photolithography is shown in i~. Figure 1 shows a Ti
Br2-CH30H (2% by weight) using O21 as a mask
This figure shows a state where an n-InP substrate 61 is chemically etched using a liquid. Therefore, the etched surface is (111) and has a forward taper. When etching was performed in this state by RIE using c7?4 gas, the verticality was significantly improved as shown in Figure 1C.0 Effects of the Invention According to the present invention, etching is performed with the wafer placed horizontally. Etched mirrors can be used on both end faces of the semiconductor laser because the etching variation within the wafer is small, allowing the use of large-area wafers, and the perpendicularity of all sidewall surfaces is improved. That is, the mass productivity of semiconductor lasers is dramatically improved, and the industrial value of the present invention is extremely large.
第1図は本発明の一実施例方法を説明するだめの工程断
面図、第2図は従来用いられていた斜め6 ・ −7
RIE法を説明するだめの断面図、第3図は斜めRIE
法によるJ−ノチング形状を示す断面図である。
1−−−− T i O2,2=・・・P、−1:nG
aAsP、 3.−−−−−P−InF14−−−−
−−1nCzhAsP、ts−−−−n−1:nP。
6・・・・・・n−InP基板。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名/
−−−Ti0z
2−−− F −In Cr0LAs /)第1図
3−F−1nF
4−−−1 ?1.6cLA S P
5−77−1矢P
(0−) /)−n −17LP基板(b)
7−試折
ε −m−針Jう ラ白具
Q −−−Ti0z
第3図 //、/計−ミラー面(C)Fig. 1 is a cross-sectional view of a process to explain a method according to an embodiment of the present invention, Fig. 2 is a cross-sectional view of a process to explain a conventionally used diagonal 6/-7 RIE method, and Fig. 3 is a process cross-sectional view of a diagonal RIE method.
FIG. 3 is a sectional view showing a J-notching shape according to the method. 1---- T i O2,2=...P, -1:nG
aAsP, 3. ------P-InF14----
--1nCzhAsP, ts---n-1:nP. 6...n-InP substrate. Name of agent: Patent attorney Toshio Nakao and 1 other person/
---Ti0z 2--- F -In Cr0LAs /) Figure 1
3-F-1nF 4---1? 1.6cLA S P 5-77-1 Arrow P (0-) /)-n -17LP board (b) 7-Trial folding ε -m-Needle J La white tool Q ---Ti0z Fig. 3 // ,/total - mirror surface (C)
Claims (4)
の側壁を有する断差を形成する工程とドライエッチング
により前記側壁の傾斜を急峻にする工程を含んでなる半
導体装置の製造方法。(1) A method for manufacturing a semiconductor device, comprising the steps of: forming a gap having forward-sloping sidewalls on a semiconductor surface by chemical etching; and making the slope of the sidewall steeper by dry etching.
第1項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor includes at least InP.
囲第1項記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor includes at least GaAs.
Brを含むガスを用いた反応性イオンエッチングである
特許請求の範囲第1項記載の半導体装置の製造方法。(4) The method for manufacturing a semiconductor device according to claim 1, wherein the dry etching is reactive ion etching using a gas containing Cl or Br as a component element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26693886A JPS63120426A (en) | 1986-11-10 | 1986-11-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26693886A JPS63120426A (en) | 1986-11-10 | 1986-11-10 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63120426A true JPS63120426A (en) | 1988-05-24 |
Family
ID=17437771
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26693886A Pending JPS63120426A (en) | 1986-11-10 | 1986-11-10 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63120426A (en) |
-
1986
- 1986-11-10 JP JP26693886A patent/JPS63120426A/en active Pending
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