JPS63119571A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to reduce the area of a base, by forming an outer base region by impurity diffusion through a silicon film, forming an active base layer in a self-aligning mode, and opening a diffusing window for forming an emitter layer in alignment with a silicon film pattern by a self-aligning mode. CONSTITUTION:A silicon film and a nitride film are sequentially formed on a substrate 1. The nitride film is selectively removed. With the remaining nitride film as a mask, the removed part is selectively oxidized. With the selected oxide film as a mask, outer base impurities are introduced in the silicon film and further diffused into the substrate. Thus an outer base region 53 is formed. Thereafter, the selected oxide film is removed, and an active base layer 62 is formed in a self-aligning mode. After an oxide film is deposited on the entire surface, anisotropic etching of the oxide film is performed with the nitride film as a mask. The oxide film is made to remain on the side wall of the silicon film at least on the side of the active base layer. The oxide film on a part of the surface of the active base layer is removed in a self-alining mode with respect to the silicon film. An emitter layer 71 is formed in the active base layer in a self-aligning mode. Thus the area of the base can be reduced.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and particularly to a bipolar semiconductor integrated circuit device (hereinafter referred to as B
This invention relates to an improvement in a method for forming an electrode lead-out portion of a transistor in an IP-IC (IP-IC).

[Conventional technology]

Generally, the transistor in BIP-IC is pnn
Junction separation 1 Oxide film separation using selective oxidation technology.

Alternatively, the transistors are formed in electrically independent islands by a method using triple diffusion, etc., and are isolated from adjacent transistors. Here, a method of forming an npn transistor using an oxide film separation method will be described. Of course, the present invention can also be applied when using the above-mentioned various separation methods other than this, or even when producing a pnp transistor.

FIGS. 4(A) to 4(I) are cross-sectional views showing main manufacturing process steps in a conventional method for manufacturing a semiconductor integrated circuit device. The conventional manufacturing method will be briefly explained below with reference to FIG.

After selectively forming an n-type (n+ type) layer 2 with a high impurity concentration to serve as a collector buried layer on a p-type (p-type) silicon substrate 1 with a low impurity concentration, an n-type layer 2 with a low impurity concentration is formed on the p-type (p-type) silicon substrate 1 with a low impurity concentration. Type (
Grow an n-type epitaxial layer 3 (see FIG. 4(A)
)).

An underlying oxide film 101 is formed on the epitaxial layer 3, and a nitride film 20 having a predetermined shape is further formed on the underlying oxide film 101.
form 1. By performing selective oxidation using the nitride film 201 as a mask, a thick isolation oxide film 102 is formed.

At this time, a p-type layer 4 for channel cut is also formed under the isolated oxidized FJ 102 (FIG. 4(B)).

After removing the nitride film 201 used as a mask for selective oxidation together with the underlying oxide film 101, an oxide film 103 for protecting ion implantation is formed again. After forming a p-type layer 6, which will become an active base layer, by performing ion implantation on the oxide film 103 using a photoresist film (the photoresist film at this stage is not shown) as a mask, a p-type layer 6, which will become an active base layer, is formed. The oxide film 103 near the region is removed. Next, a silicon film 601 is deposited on the entire exposed surface. Here, as the silicon film, one of a single crystal silicon film, a polycrystalline silicon film, and an amorphous silicon film is used (FIG. 4(C)).

By introducing n-type impurities into the entire surface of the silicon film 601 and performing sintering, the p-type layer 6 becomes an intermediate active base region 61, and the impurities are diffused from the p-type impurity-containing silicon film 601. An external base region 51 is formed. Thereafter, silicon film 601 is selectively etched away, leaving silicon film 601 on external base region 51 and isolation oxide film 102. Oxidation is performed again to form an oxide film 105 at the position where the oxide film 103 had been formed, an oxide film 106 on the remaining silicon film 601, and further a PSG (phosphorus glass) film 401 is formed on the entire surface. (Figure 4(D)).

By selective etching using a photoresist film (not shown) as a mask, the oxide film 105 and the PSG film 4 on the regions to become the emitter layer and the collector electrode extraction layer are removed.
Next, the silicon film 60 is removed to form an opening.
2 is deposited on the entire surface, n-type impurities are ion-implanted into the silicon film 602 at a high concentration. Next, by driving the implanted impurity and diffusing the impurity from the silicon film 602 to the substrate surface, the n+ type layer 71 that will become the emitter layer and the n-shaped layer 81 that will become the collector electrode extraction layer.
form. At this time, impurities are similarly driven in the external base region 51, and it becomes the external base region 52 (FIG. 4(E)).

Silicon film portion 602a that served as an impurity diffusion source.

Selective etching is performed on the silicon film 602 so that only the portion 603 remains. Next, using the resist film 302 patterned into a predetermined shape as a mask, a window for a base contact is opened. At this time, the resist film 302 is formed so as to expose a part of the silicon 1111602a for forming the emitter layer, and thereby the exposed silicon film 6
02a as a mask, the base contact is formed, and the subsequent oxide film 106.02a is formed on the silicon film 601. PSG film 401
is removed by etching (Fig. 4 (F)).

By performing oxidation at low temperature (approximately 800 to 900°C), n
A thick oxide film 108 is formed on the polysilicon films 602a and 603 on the ten layers 71 and 81, and a thin oxide film 107 is formed on the p-type head region 62 and the p-type silicon film 601. This is based on the well-known fact that enhanced oxidation occurs at low temperatures in silicon substrates and silicon films that contain high concentrations of n-type impurities such as phosphorus and arsenic (see Figure 4). (G)).

Only the thin oxide film 107 is washed out. Next, P t , P d + T i +W forming metal silicide between silicon and polysilicon film
, after forming a metal layer (not shown) on the entire upper surface using a vapor deposition method or a sputtering method using a metal such as Mo,
By performing sintering, the metal silicide film 5
01.502 is formed on the exposed surface of the silicon substrate and the surface of the silicon film 601. Next, the metal layer is removed by etching with aqua regia or the like so as to leave the metal silicide film (FIG. 4(H)).

After depositing the nitride film 202 (an oxide film may also be used) for the vanity basin, the nitride film 202 and the thick oxide film 1 are deposited.
By performing selective etching on the base electrode contact hole 50. Contact hole 7 for emitter electrode
0 and a collector electrode contact hole 80 are formed.

Next, base electrode wiring 9. is made of a low resistance metal such as aluminum (AI). Emitter electrode wiring 10 and collector electrode wiring 11 are formed respectively (Fig. 4 (
I) ”).

[Problem that the invention seeks to solve]

FIG. 5 is a diagram showing a planar pattern of a transistor manufactured through the manufacturing process shown in FIGS. 4(A) to 4(I) described above. In FIG. 5, the distance C is the emitter layer 7
1 and the polysilicon film 601 connected to the base electrode 9, and the distance indicates the distance between the emitter layer 71 and the isolation oxide film 102. Photolithography for opening a window (forming an opening) for forming the emitter layer 71 is performed in accordance with either the pattern of the isolation oxide film 102 or the polysilicon film 601. The distance from layer 71 must be larger than the overlapping margin during photolithography (an overlapping margin equivalent to two photolithographic processes is required). Generally, since photolithography is performed to open a window for forming the emitter layer 71 in accordance with the pattern of the isolation oxide film 102, the distance C
It is necessary to make it large (approximately twice the overlapping margin or more). By increasing this distance C, the base area increases, resulting in an increase in base-collector capacitance.

Figure 6 shows the distance C between the emitter layer and the polysilicon film connected to the base electrode due to the overlay accuracy of photolithography.
FIG. Hereinafter, the dependence of the distance C on the photolithographic overlay accuracy will be explained with reference to FIG.

Normally, as shown in FIG. 6(a), a polysilicon film 601 serving as a base electrode has an isolation edge (an edge of an isolation oxide film).
(arrow A in the figure), the emitter contact is also photoengraved to match the separation edge (arrow B in the figure), and the silicon film 602a that will become the emitter electrode is photoengraved to match the contact pattern. In addition, the polysilicon film spacing C (corresponding to the distance C in FIG. 5) is determined by the overlay accuracy of photolithography, and in the worst case
As shown in Figures (b) and (C), there is a large change from less than half to three times the normal state.

FIG. 7 is a diagram showing a planar pattern of a transistor with a double base structure in which the averaged value does not vary by having the above-mentioned distance C on both sides of the emitter. In this double base structure, an active base region 62 is formed to surround the emitter layer 71,
The silicon film 601 on the external base region is the emitter layer 7
1 and is connected to the base electrode wiring 11 through contact holes 50 on both sides.

FIG. 8 is a diagram showing a cross-sectional structure of a transistor element having a double base structure in the worst case of photolithography when forming the emitter layer 71. That is, by adopting the double base structure shown in FIG. 7, the emitter layer 7 as shown in FIG.
Even if the photolithographic overlay during the formation of 1 is the worst, the distance E between the silicon [9!601-emitter diffusion layer 71 connected to the base electrode] needs to be as designed. With such a double base structure, the polysilicon film spacing (
In other words, the silicon 11N connected to the emitter layer 71 and the base electrode! 601) C includes the photolithography overlay margin, and the extra base area is doubled by adopting this double base structure, which improves the frequency characteristics of the transistor element. This is a major obstacle to

Therefore, this invention was made to eliminate the above-mentioned drawbacks, and the distance between the emitter layer and the silicon film connected to the base electrode is reduced, thereby reducing the base area and improving the frequency characteristics. An object of the present invention is to provide an improved semiconductor integrated circuit device and a method for manufacturing the same.

[Means for solving problems]

A semiconductor integrated circuit device and a method for manufacturing the same according to the present invention include sequentially forming a silicon film and a nitride film on a substrate, selectively removing the nitride film, and using the remaining nitride film as a mask to select the removed portion. External base impurities are introduced into the silicon film using the selective oxide film as a mask, and further diffused into the substrate to form an external base region.Then, the selective oxide film is removed to form an active base layer in a self-aligned manner. After depositing the oxide film on the entire surface, anisotropic oxide etching is performed using the nitride film as a mask to leave the oxide film at least on the sidewall of the silicon film on the side of the active base layer and to activate the silicon film in a self-aligned manner. The oxide film on a partial region of the surface of the base layer is removed, and an emitter layer is formed in the active base layer in a self-aligned manner.

[Effect]

In this invention, an external base region is formed by impurity diffusion from a silicon film, an active base layer is formed in a self-aligned manner with respect to this silicon film, and a diffusion window for forming an emitter layer is formed in a silicon film pattern. By performing this in a self-aligned manner according to the The distance between the silicon film connected to the emitter layer and the distance between the emitter layer and the separation edge can be significantly reduced, making it possible to reduce the base area.

〔Example〕

FIGS. 1A to 1) are cross-sectional views showing main process steps in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS. Parts that are equivalent or comparable to the examples are provided with the same reference numerals. Hereinafter, a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described with reference to FIGS. 1(A) to 1(I).

First, as in the conventional method, n is applied to the p-type silicon group Fi,1.
÷ type collector buried layer 2. n-type epitaxial layer 3. After forming the p-type layer 4 for channel cut and the isolation oxide film 102, the nitride film 11!201 and the underlying oxide film 101 shown in FIG. 4(B) are removed. Next, after depositing a polysilicon film 600 on the entire upper surface, an oxide film 110. Nitride film 2
03 and an oxide film 111 are deposited in this order. Here, the oxide film 110 may be formed by oxidizing the polysilicon film 600. In addition, the nitride film 203 and the polysilicon 1
When performing selective etching with IJ600, oxide film 1
10 and 111 are not required, but an example will be described here in which an oxide film using a general plasma etching method is required (FIG. 1(A)).

Using common photolithography and selective etching techniques,
Composite film 110 including a nitride film 203 on a region to be an external base region and a region to be a base electrode extraction region
, 203, 111 are left, the composite membranes 110, 203,
111 is selectively removed by etching. Next, etching is performed again using the resist film 301 as a mask to remove the polysilicon film 600 in the region that will become the collector electrode extraction layer and between the region that will become the collector electrode extraction layer and the region that will become the external base layer. Here, composite membrane 110.203
, 111, the polysilicon film 600 may be etched to a predetermined thickness to reduce the thickness of the oxide film formed in the next step. In addition, the resist film 30
When etching the polysilicon film 600 using No. 1 as a mask, the surface of the n- layer may be slightly etched. Here, the etching of the polysilicon film in the portion in contact with the region to become the external base layer is performed using the composite films 110, 203, and 111 as a mask.
The resist film 301 is a part where the composite film 110, 203, 111 is not formed and is not to be etched (that is, at least a region that should become an active base layer).
(Fig. 1)
B)).

After removing the oxidized PAl 11 on the upper layer of the composite film (although it is not necessarily necessary to remove it here, it is better to remove it here to prevent thinning of the oxide film that will be formed in a later step), and then nitride y! By performing selective oxidation using 203 as a mask, the polysilicon film 600 is changed into oxide films 113 and 114, and the exposed surface of the n-layer 3 is oxidized 11
Grow i1112. These selective oxide films 112.
Using 113 and 114 as masks, a p-type impurity is introduced into the polysilicon film under the nitride film 203, and then sintering is performed to form a p-type impurity-containing polysilicon film 6.
From step 01, p-type impurities are diffused to form an intermediate external base layer 51. Here, since the oxide film 112 is formed by selectively oxidizing the epitaxial layer 3, the step difference between it and the adjacent polysilicon film is extremely small, and it is formed deep to the junction surface of the external base layer 51, which improves the breakdown voltage of the transistor. (Figure 1 (
C)).

A diffusion window is selectively opened in the oxide film 112 and n-type impurities are diffused at a high concentration to form the collector electrode extraction layer 81.
(Fig. 1(D)).

After oxidizing the surface of the collector electrode extraction layer 81 to form an oxide film 115, the oxide film 111 on the region to become the active base layer
4 is removed by etching using the nitride film 203 as a mask. At this time, the oxide 1!1!112, 113.degree. 115 is covered with a resist film 302 so as not to be etched, and the oxide film is etched (FIG. 1(E)).

After removing the resist film 302, an oxide film 116 is formed as a protective mask during ion implantation, p-type impurities are implanted, an oxide film 117 is deposited over the entire surface, and annealing is performed to form an active base layer 61 at an intermediate stage. do. Here, ion implantation technology was used to introduce the p-type impurity, but of course thermal diffusion or diffusion using a doped film can also be used. The active base layer 61 includes a nitride film 203, an oxide film 110, and an oxide film 112.
115 serves as a mask, and is formed in self-alignment with the external base layer (FIG. 1(F)).

The oxide film 117 and the oxide film 116 are removed by anisotropic etching (RIE). At this time, the nitride film 203 serves as a mask to oxidize the oxide film 110 under the nitride film 203 and the sidewalls of the polysilicon film 601! 116 and 117 will definitely remain. Further, after the nitride film 203 is completely removed, a second polysilicon film 602 is formed, n0 impurities are introduced therein, and a nitride film 204 is further formed thereon. When ion implantation is used, annealing is performed to uniformly diffuse impurities into polysilicon film 602. At this time, impurities are slightly diffused into the n- epitaxial layer 3 from the polysilicon film 602 to form an intermediate layer of the emitter layer 71. Then, the nitride film 204 other than the emitter layer 71. The n+ polysilicon film 602 is sequentially removed using a resist film mask (not shown).

At this time, since the emitter layer 71 is formed in a self-aligned manner with respect to the polysilicon film 601 which is the diffusion source of the external base, the external base layer 53 is the thickness of the oxide films 116 and 117 on the sidewalls of the polysilicon film 601. They are formed at regular intervals. That is, the external base layer 53 is formed by photolithography by patterning the nitride film 203 as shown in FIGS. 1(A) to 1(B).
．． Active base layer 61. This means that the entire region of the emitter layer 71 has been determined (FIG. 1(G)).

Continuing to FIG. 1(G), the oxide film 110 is also polysilicon 1
After etching and removing the resist film (not shown) used for patterning 11602, the resist film was removed,
Using the nitride film 204 as a mask, low-temperature oxidation (800-850
℃) to form a thick oxide film 119 on the side wall of the n+ polysilicon film 602, and a thick oxide film 119 on the side wall of the n+ polysilicon film 602, and a thick oxide film 119 on the sidewall of the p+ polysilicon film Ilj! A thin oxide film 118 is formed on the surface of 601. This takes advantage of the fact that the accelerated oxidation effect is greater as the n-layer silicon/polysilicon film is oxidized at a lower temperature (FIG. 1 (H)).

After removing the thin oxide film 118 using the nitride film 204 as a mask, removing the entire surface of the nitride film 204 by wet (phosphoric acid) to form silicide films 502 and 503, depositing PSGli 1401, and annealing and baking, Contacts are formed and electrode wiring 9°11 is performed. Here, the silicide films 502 and 503 are not used to prevent conventional electrode punching, but to lower the resistance.
If titanium (titanium) silicide or W (tungsten) silicide is used and there is no resistance to impurity diffusion, the PSG film may have at least a two-layer structure with a non-doped CVD film, and low-temperature formation that does not require baking. When using a plasma oxide film/nitride film, pt silicide or Pd silicide may be used (FIG. 1(I)).

FIG. 2(A) is a diagram showing a plane pattern of a transistor of a semiconductor integrated circuit device manufactured through the above manufacturing process, and FIGS. 5 and 7 are diagrams showing a plane pattern of a transistor manufactured by a conventional method. This corresponds to Second
A cross-sectional structure taken along the line xx' shown in FIG. 1(A) is shown in FIG. 1(1). As shown in FIG. 2(A), the distance C' between the external base layer 53 and the emitter layer 71 is determined to be small in a self-aligned manner, and the base resistance can be efficiently lowered. The wiring resistance between the external base layer 53 and the base electrode 9 is also significantly reduced by the film 502, and as shown in FIG. 1(I), the base electrode contact is on the oxide film 102, and the base capacitance is also significantly reduced can be done.

FIG. 2(B) is a diagram showing a cross-sectional structure taken along the line YY' in FIG. 2(A). Here, the distance D' between the emitter layer 71 and the wall portion (thick oxide film 113) is different from that of the conventional thick oxide films 112 and 113, and
Since it is determined in a self-aligned manner during patterning of I600, as shown in FIG. 2(A), this distance D' can also obtain a constant value for the patterning width of the polysilicon film by photolithography.

The external base region 53 also includes an emitter layer 71 as seen in the conventional double base structure shown in FIG.
The emitter layer 71 is not formed in a very unbalanced state around the emitter layer 71 at regular intervals (
As can be clearly seen by comparing FIG. 2(A) and FIG. 8, in the transistor element of the present invention, the base area can be significantly reduced, and the base It can be seen that the uniformity of parameters such as collector capacitance and base resistance is improved.

Note that the etching of the polysilicon film by the resist film 301 in FIG. 1(B) in the above embodiment is deleted, and
The process can also be shortened by performing selective oxidation as shown in FIG. 3, which corresponds to FIG. 1(C). However, in this case, as shown in FIG. 3, oxide 1ijll13 in contact with the external base layer 51 is formed on the semiconductor surface, which increases lateral diffusion and sidewall capacitance, resulting in a slight decrease in transistor performance.

Further, in the above embodiment, the external base layer 53, the emitter layer 71 . Although the film connected to the collector electrode extraction layer 81 has been described as a polysilicon film, a single crystal silicon film or an amorphous silicon film may be used instead.

Further, in the above embodiments, a case has been described in which an element isolation region made of a thick oxide film is formed to isolate adjacent transistor layers, but the present invention is not limited to this case; for example, a trench Even when applied to a transistor having an isolation region using a (groove) structure, the same effects as in the above embodiment can be obtained.

[Effects of the Invention] As explained above, according to the semiconductor integrated circuit device and the manufacturing method thereof according to the present invention, the external base region is formed by impurity diffusion from the silicon film left after a selective oxidation process, and this silicon film is Since the active base region is formed in a self-aligned manner and the opening for forming the emitter layer is provided in a self-aligned manner in accordance with the silicon film pattern, the selective oxide film on the outer periphery of the silicon film forms a transistor. The distance between the emitter layer and the silicon film connected to the base electrode and the distance between the emitter layer and the edge of the field portion can be significantly reduced, resulting in a reduction in the base area and the distance between the emitter layer and the silicon film connected to the base electrode. This has the effect that the collector-collector capacitance can be reduced, the base resistance can also be reduced, and a semiconductor integrated circuit device including a transistor with good frequency characteristics can be realized.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2(A) is a diagram showing a plane pattern of a transistor manufactured according to an embodiment of the present invention, and FIG. 2(CB) is a diagram showing a line Y in FIG. 2(A).
It is a figure showing a cross-sectional structure along -Y'. FIG. 3 is a process sectional view showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 4 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor integrated circuit device, and FIG. 5 is a diagram showing a planar pattern of a transistor manufactured using the conventional manufacturing method. FIG. 6 is a diagram showing the variation in the distance between the emitter layer and the edge of the isolation region and the variation in the distance between the emitter layer and the polysilicon film connected to the base electrode due to the overlay accuracy of photolithography in the transistor shown in FIG. 5. It is. Fig. 7 is a diagram showing the planar pattern of a conventional double-base structure transistor, and Fig. 8 is a photolithographic overlay of the distance between the emitter layer and the silicon film connected to the base electrode of a conventional double-base structure transistor element. FIG. 3 is a diagram showing dependence on alignment accuracy. In the figure, 1 is a p-type silicon substrate, 3 is an n-type epitaxial layer, 6, 61.62 is an active base layer, 71 is an emitter layer, 81 is a collector electrode extraction layer, 9 is a base electrode, and 10 is an emitter electrode. , 11 is a collector electrode, 51.
52, 53 is an external base layer, 102 is an isolation oxide film, 10
1,105 to 108, 110 to 119 are silicon oxide films, 201 to 204 are nitride films, 301, 30
2 is a resist film, 401 is a psc film (insulating film), 600
．． 601, 602 are polysilicon films, 501.502.
503 is a metal silicide film. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (5)

[Claims] (1) In a semiconductor integrated circuit device having a bipolar transistor, a silicon film serving as a diffusion source connected to an external base layer surrounding the active base layer of the transistor, and a first oxide film in contact with the outer periphery of the silicon film; and a second oxide film formed on a sidewall of the silicon film on the active base layer side. (2) The semiconductor integrated circuit device according to claim 1, wherein the first oxide film is obtained by oxidizing a semiconductor substrate. (3) The semiconductor integrated circuit device according to claim 1, wherein the first oxide film is obtained by oxidizing a silicon film. (4) An element isolation region is formed around the transistor, and one of the silicon films is formed to extend onto the element isolation region. 3. The semiconductor integrated circuit device according to any one of items 3 to 3. (5) A method for manufacturing a semiconductor integrated circuit device having a bipolar transistor, including: a first step of sequentially forming a silicon film and a nitride film on a substrate; a second step of selectively removing the nitride film; A third step of selectively oxidizing the removed portion using the nitride film as a mask. Using the selective oxide film as a mask, external base impurities are introduced into the silicon film and further diffused into the substrate to form an external base region. a fourth step of removing the selective oxide film and forming an active base layer in a self-aligned manner; after depositing the oxide film on the entire surface, anisotropic oxide film etching is performed using the nitride film as a mask; a fifth step of leaving the oxide film on the side wall of the film on the side of the active base layer and removing the oxide film on a partial region of the surface of the active base layer in a self-aligned manner with respect to the silicon film; a sixth step of forming an emitter layer in the active base layer in a consistent manner.