JPS63118234U - - Google Patents
Info
- Publication number
- JPS63118234U JPS63118234U JP1987008401U JP840187U JPS63118234U JP S63118234 U JPS63118234 U JP S63118234U JP 1987008401 U JP1987008401 U JP 1987008401U JP 840187 U JP840187 U JP 840187U JP S63118234 U JPS63118234 U JP S63118234U
- Authority
- JP
- Japan
- Prior art keywords
- pad
- pellet
- semiconductor device
- lead terminal
- bonding wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims 2
- 239000008188 pellet Substances 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 11
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
第1図は本考案の一実施例を示す図であり、A
は構造図、B等価回路図、Cはゲインの周波数特
性を示す図である。第2図は本考案の他の実施例
を示す図であり、Aは構造図、Bは等価回路図で
ある。第3図は従来例を示す図であり、Aは構造
図、Bは等価回路図、Cはゲインの周波数特性を
示す図である。
は構造図、B等価回路図、Cはゲインの周波数特
性を示す図である。第2図は本考案の他の実施例
を示す図であり、Aは構造図、Bは等価回路図で
ある。第3図は従来例を示す図であり、Aは構造
図、Bは等価回路図、Cはゲインの周波数特性を
示す図である。
Claims (1)
- ペレツト上に外部引出し端子へ接続する為のボ
ンデイング・パツドを有する半導体装置において
、任意のパツドに接続するボンデイングワイヤの
インダクタンスと直列共振する容量値を形成する
容量部とこの外部接続用パツドをペレツト上に形
成し、この容量部パツドと先の任意のパツドとか
ら並例に外部引立し端子へボンデイングし、先に
示した直列共振によりボンデイング・ワイヤの影
響を低減する事を特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987008401U JPH0543478Y2 (ja) | 1987-01-22 | 1987-01-22 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987008401U JPH0543478Y2 (ja) | 1987-01-22 | 1987-01-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63118234U true JPS63118234U (ja) | 1988-07-30 |
JPH0543478Y2 JPH0543478Y2 (ja) | 1993-11-02 |
Family
ID=30792742
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987008401U Expired - Lifetime JPH0543478Y2 (ja) | 1987-01-22 | 1987-01-22 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0543478Y2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013541308A (ja) * | 2010-10-29 | 2013-11-07 | クゥアルコム・インコーポレイテッド | パッケージインダクタンス補償型調整可能キャパシタ回路 |
-
1987
- 1987-01-22 JP JP1987008401U patent/JPH0543478Y2/ja not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013541308A (ja) * | 2010-10-29 | 2013-11-07 | クゥアルコム・インコーポレイテッド | パッケージインダクタンス補償型調整可能キャパシタ回路 |
Also Published As
Publication number | Publication date |
---|---|
JPH0543478Y2 (ja) | 1993-11-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS63118234U (ja) | ||
JPS63187341U (ja) | ||
JPS615023U (ja) | 周波数可変式帯域通過濾波器 | |
JPH01117119U (ja) | ||
JPH0281057U (ja) | ||
JPH01117109U (ja) | ||
JPH0330442U (ja) | ||
JPS63195754U (ja) | ||
JPS633178U (ja) | ||
JPS63163025U (ja) | ||
JPH0245676U (ja) | ||
JPS63152314U (ja) | ||
JPS59119626U (ja) | 遅延素子 | |
JPS596843U (ja) | 半導体装置 | |
JPH0195757U (ja) | ||
JPH0423156U (ja) | ||
JPS601054U (ja) | Am用外部アンテナ装置 | |
JPS5959032U (ja) | 同調回路 | |
JPS60141125U (ja) | 電子部品装置 | |
JPS6170373U (ja) | ||
JPS6169846U (ja) | ||
JPS62203538U (ja) | ||
JPS6425173U (ja) | ||
JPS5843026U (ja) | トラツプ回路 | |
JPS59161651U (ja) | マイクロ波モノリシツク集積回路 |