JPS63117121U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a linearizer that is a specific embodiment of the present invention, FIG. 2 is a diagram of nonlinear voltage characteristics between input and output, and FIG. 3 is a block diagram of a conventional linearizer. 1, 10...Analog-to-digital converter (ADC)
), 3, 11...ROM, 4...rate multiplier, 12...multiplexer, 13...output section.

Claims (1)

[Claims for Utility Model Registration] A linearizer that digitally converts an analog value of a nonlinear characteristic and obtains a linearized output value via a ROM in which a broken line corresponding to the nonlinear characteristic is stored, comprising: Converts the address into a digital signal, outputs the upper bit as an upper address signal,
an analog-to-digital converter that outputs the lower bit as a lower address signal; a ROM to which the upper address signal is guided and outputs a function value signal and a differential value signal; and a ROM that outputs the function value signal, the differential value signal, and the lower address. a multiplexer to which a signal is guided and which switches and outputs each of these signals; the function value signal switched and output from the multiplexer is sampled and held in a first sample holder after digital-to-analog conversion with a reference voltage of a predetermined value; The differential value signal is sampled and held in a second sample holder after digital-analog conversion using the reference voltage, and the lower bit signal is digital-analog-converted using the value sampled and held in the second sample holder as a reference voltage, and then sampled and held in a third sample holder. A linearizer comprising: an output unit that outputs a sample and hold value of the first sample holder and a sample hold value of the third sample holder that are added together;