JPS63116451A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS63116451A JPS63116451A JP61262388A JP26238886A JPS63116451A JP S63116451 A JPS63116451 A JP S63116451A JP 61262388 A JP61262388 A JP 61262388A JP 26238886 A JP26238886 A JP 26238886A JP S63116451 A JPS63116451 A JP S63116451A
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- chip
- integrated circuit
- hybrid integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920005989 resin Polymers 0.000 claims abstract description 46
- 239000011347 resin Substances 0.000 claims abstract description 46
- 239000011248 coating agent Substances 0.000 claims abstract description 14
- 238000000576 coating method Methods 0.000 claims abstract description 14
- 239000003822 epoxy resin Substances 0.000 claims abstract description 8
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 8
- 229920002050 silicone resin Polymers 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 3
- 230000007613 environmental effect Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000001351 cycling effect Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、混成集積回路装置、特に混成集積回路（ハ
イブリッドＩＣ）のコーティングに関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to the coating of hybrid integrated circuit devices, particularly hybrid integrated circuits (hybrid ICs).
第２図は従来より用いられている、例えば、“５ｅｒｎ
ｉｃｏｎｄｕｃｔｏｒ Ｗｏｒｌｄ ”誌１９８３．１
に示されたＳＩＰ形の一部破断斜視図である。Figure 2 shows conventionally used, for example, "5ern"
iconductor World” magazine 1983.1
FIG. 2 is a partially cutaway perspective view of the SIP type shown in FIG.
図中、１は、セラミック基板、２は、抵抗素子、３は、
チップトランジスタ、４はチップコンデンサ、５は外部
リード、６は、裸のＩＣチップ８をコーティングしてい
るチップコート樹脂層、７は、混成集積回路装置をコー
ティングしている外装コート樹脂層、９は、７の外装コ
ート樹脂層の内側層であるインナコート樹脂層である。In the figure, 1 is a ceramic substrate, 2 is a resistance element, 3 is
A chip transistor, 4 a chip capacitor, 5 an external lead, 6 a chip coat resin layer coating the bare IC chip 8, 7 an exterior coat resin layer coating the hybrid integrated circuit device, 9 a chip transistor; , 7 is an inner coat resin layer which is an inner layer of the outer coat resin layer of No. 7.
上記の従来例においては、チップコート樹脂層６、イン
ナコート樹脂層９．外装コート樹脂層７は積層状であり
、共にエポキシ樹脂コーティングしたものである。なお
、７の外装コート樹脂層は粉体エポキシによる外装であ
り、生成される外装は緻密である。また、インナコート
樹脂層９をシリコン樹脂としている従来例もある。In the above conventional example, the chip coat resin layer 6, the inner coat resin layer 9. The exterior coat resin layer 7 is in the form of a laminate, and both are coated with epoxy resin. Note that the exterior coat resin layer 7 is an exterior made of powdered epoxy, and the resulting exterior is dense. There is also a conventional example in which the inner coat resin layer 9 is made of silicone resin.
以上の従来例においては、その構成、特にその材質から
、前記の積層状の各樹脂層間には間隙が存在しないか、
あるいは少い。In the above conventional example, due to its structure, especially its material, there is no gap between each of the laminated resin layers, or
Or less.
従来の混成集積回路装置は、前述のような構成のため、
温度サイクルによりＩＣチップへ応力が加わったり、外
装コート樹脂層にクラックが入る危険性があるため、温
度サイクル試験や耐湿試験環境に弱い問題点がある。Conventional hybrid integrated circuit devices have the above-mentioned configuration, so
There is a risk that stress will be applied to the IC chip due to temperature cycling and cracks will occur in the outer coating resin layer, so there is a problem that it is weak in temperature cycling test and humidity test environments.
この発明は、上記のような従来例の問題点を解決するた
めのなさねたもので、信頼性試験等において、従来のモ
ノクシツクＩＣと同等の性能を有する混成集積回路装置
を得ることを目的としている。This invention was made to solve the problems of the conventional example as described above, and the purpose is to obtain a hybrid integrated circuit device that has performance equivalent to that of the conventional monoxic IC in reliability tests, etc. There is.
このため、この発明に係る混成集積回路装置は、チップ
コート樹脂層にシリコン樹脂、外装コート樹脂層にフェ
ノール変性エポキシ樹脂を使用して、該チップコート樹
脂層と外装コート樹脂層間の全域に間隙を存在させるよ
う構成したものである。Therefore, the hybrid integrated circuit device according to the present invention uses a silicone resin for the chip coat resin layer and a phenol-modified epoxy resin for the exterior coat resin layer, thereby creating a gap in the entire area between the chip coat resin layer and the exterior coat resin layer. It is configured to exist.
この発明における混成集積回路装置は、以上のように構
成されているので両組脂層間の全域にわたって間隙が介
在するようになり、ＩＣチップへの環境温度サイクルに
より応力が加わったり、外装コート樹脂層にクラックが
入ることが防止され、さらに、水分の発散が容易となる
。Since the hybrid integrated circuit device of the present invention is constructed as described above, there is a gap between the two resin layers over the entire area, and stress is applied to the IC chip due to environmental temperature cycles, and the outer coating resin layer This prevents cracks from forming, and also facilitates moisture dissipation.
（実施例）
第１図は、本発明の一実施例である混成集積回路装置の
側面断面図である。(Embodiment) FIG. 1 is a side sectional view of a hybrid integrated circuit device that is an embodiment of the present invention.
図中、１は、セラミック基板、２は、抵抗素子、３は、
チップトランジスタ、４はチップコンデンサ、５は外部
リード、６は、裸のＩＣチップ８をシリコン樹脂でコー
ティングしたチップコート樹脂層、７はフェノール変性
エポキシ樹脂でコーティングした外部コート樹脂層、１
０は、チップコート樹脂層６と外部コート樹脂層間に介
在する間隙である。図中、従来例第２図と同一符号は同
一または相当部分を示す。In the figure, 1 is a ceramic substrate, 2 is a resistance element, 3 is
A chip transistor; 4 is a chip capacitor; 5 is an external lead; 6 is a chip coat resin layer in which a bare IC chip 8 is coated with silicone resin; 7 is an external coat resin layer in which a bare IC chip 8 is coated with a phenol-modified epoxy resin;
0 is a gap between the chip coat resin layer 6 and the external coat resin layer. In the figure, the same reference numerals as in FIG. 2 of the conventional example indicate the same or corresponding parts.
間隙１０は、チップコート樹脂Ｎ６をコーティング硬化
後、外装コート樹脂層７をコーティングして硬化させる
ので、チップコート樹脂層６が、２度の硬化処理を受け
て、−層縮小し、両相脂層６．７間に間隙１０を生ずる
。The gap 10 is formed by coating and curing the exterior coat resin layer 7 after coating and curing the chip coat resin N6, so that the chip coat resin layer 6 is subjected to the curing process twice, shrinking in size, and forming both phase resins. A gap 10 is created between the layers 6,7.
以上にような構成としたため、本実施例によれば、環境
温度サイクルによる裸のＩＣチップ８への応力を緩和し
たり、外装コート樹脂層７にクラックが入る危険を防ぐ
ことができる。With the above configuration, according to this embodiment, stress on the bare IC chip 8 due to environmental temperature cycles can be alleviated, and the risk of cracks occurring in the outer coating resin layer 7 can be prevented.
なお、本実施例ではフェノール変性エポキシ樹脂とシリ
コン樹脂を用いて、間隙１０を生成させたが、他の種類
の樹脂を用いても同様の効果が期待できる。In this example, the gap 10 was created using a phenol-modified epoxy resin and a silicone resin, but the same effect can be expected by using other types of resin.
（発明の効果）
以上のように、この発明によれば、チップコート樹脂層
をシリコン樹脂、外装コート樹脂層をフェノール変性エ
ポキシ樹脂として、両組脂層間の全域に間隙を介在させ
ることにより、環境温度サイクル試験や耐湿試験におい
て信頼性向上の顕著な効果が得られる。(Effects of the Invention) As described above, according to the present invention, the chip coat resin layer is made of silicone resin, the exterior coat resin layer is made of phenol-modified epoxy resin, and by providing a gap throughout the entire area between both resin layers, environmentally friendly Significant improvements in reliability can be obtained in temperature cycle tests and humidity tests.
第１図は、本発明の一実施例による混成集積回路装置の
側面断面図、第２図は従来の混成集積回路装置の１例の
一部破断斜視図である。
６−−−−−チップコート樹脂層
７−−−−−−外装コート樹脂層
８−−−−−裸のＩＣチップ
１０・−・・・間隙FIG. 1 is a side sectional view of a hybrid integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a partially cutaway perspective view of an example of a conventional hybrid integrated circuit device. 6------Chip coat resin layer 7------Exterior coat resin layer 8---Bare IC chip 10---Gap
Claims (1)
装置において、前記裸のＩＣチップをシリコン樹脂でコ
ーティングしてチップコート樹脂層を形成し、このチッ
プコート樹脂層の外周全域に間隙を介して、エポキシ樹
脂でコーティングした外装コート樹脂層を設けて成る混
成集積回路装置。In a hybrid integrated circuit device in which a bare IC chip is directly mounted on a substrate, the bare IC chip is coated with a silicone resin to form a chip coat resin layer, and a chip coat resin layer is coated with a gap throughout the outer periphery of the chip coat resin layer. , a hybrid integrated circuit device comprising an outer coating resin layer coated with epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61262388A JPS63116451A (en) | 1986-11-04 | 1986-11-04 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61262388A JPS63116451A (en) | 1986-11-04 | 1986-11-04 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63116451A true JPS63116451A (en) | 1988-05-20 |
Family
ID=17375067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61262388A Pending JPS63116451A (en) | 1986-11-04 | 1986-11-04 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63116451A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03113835U (en) * | 1990-03-08 | 1991-11-21 | ||
| JP2015106649A (en) * | 2013-11-29 | 2015-06-08 | 株式会社デンソー | Electronic device |
| JP2019503277A (en) * | 2016-01-13 | 2019-02-07 | 日本テキサス・インスツルメンツ株式会社 | Structure and method for packaging a MEMS susceptible to stress |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56161661A (en) * | 1980-05-16 | 1981-12-12 | Fujitsu Ltd | Manufacture of hybrid circuit |
-
1986
- 1986-11-04 JP JP61262388A patent/JPS63116451A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56161661A (en) * | 1980-05-16 | 1981-12-12 | Fujitsu Ltd | Manufacture of hybrid circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03113835U (en) * | 1990-03-08 | 1991-11-21 | ||
| JP2015106649A (en) * | 2013-11-29 | 2015-06-08 | 株式会社デンソー | Electronic device |
| JP2019503277A (en) * | 2016-01-13 | 2019-02-07 | 日本テキサス・インスツルメンツ株式会社 | Structure and method for packaging a MEMS susceptible to stress |
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