JPS63116422A - Ion implanting method - Google Patents
Ion implanting methodInfo
- Publication number
- JPS63116422A JPS63116422A JP26315586A JP26315586A JPS63116422A JP S63116422 A JPS63116422 A JP S63116422A JP 26315586 A JP26315586 A JP 26315586A JP 26315586 A JP26315586 A JP 26315586A JP S63116422 A JPS63116422 A JP S63116422A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- plasma
- mask
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 24
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000001020 plasma etching Methods 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims description 13
- 238000001637 plasma atomic emission spectroscopy Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000004458 analytical method Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 59
- 239000010409 thin film Substances 0.000 abstract description 2
- 238000010183 spectrum analysis Methods 0.000 abstract 2
- 230000001678 irradiating effect Effects 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000000442 pressure-pulsed chemical vapour infiltration Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、′ｆ．導体装置の製造上程で用いられるイ
オン注入法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention is based on 'f. This invention relates to an ion implantation method used in the manufacturing process of conductor devices.
第２図および第３図（ａ）、（ｂ）はそれぞれ従来の半
導体装置の製造工程で用いられるイオン注入法を説明す
るための断面図である。これらの図において、１はＧａ
Ａｓ基板、２はスルー注入を行うための膜厚の薄い第１
の絶縁膜、３はフォトレジスト
第２の絶縁膜である。FIG. 2 and FIGS. 3(a) and 3(b) are cross-sectional views for explaining the ion implantation method used in the conventional manufacturing process of semiconductor devices, respectively. In these figures, 1 is Ga
As substrate, 2 is the first thin film for through implantation.
The insulating film 3 is a photoresist second insulating film.
次に、製造工程について説明する。Next, the manufacturing process will be explained.
第２図に示される方法では、まず、Ｇ ａ Ａ ｓ基板
１に第１の絶縁膜２をプラズマＣＶＤ法（以下Ｐ−ＣＶ
Ｄ法という）等により形成ずろ。乙の欣はＧａＡｓ基板
１の表面を安定化，保護するとともに、この膜を通して
注入された不純物の深さ方向の分布のばらつきを少なく
する働きをする。次に、写真製版技術によりフォトレジ
スト
成し、このフォトレジスト長技術マスクにして所望の場
所にイオン注入を行う。In the method shown in FIG.
(referred to as D method) etc. The film serves to stabilize and protect the surface of the GaAs substrate 1, and also to reduce variations in the depth distribution of impurities implanted through this film. Next, a photoresist is formed by photolithography, and ions are implanted into desired locations using this photoresist length mask.
また、第ｊ（図（ａ）、（ｂ）に示される方法では、ま
ず、Ｇ ａ Ａ ｓ基板１に第２の絶縁膜４を）） −
ＣＶＤ法等により形成する。次に、写真製版技術によリ
フォＩ・レジスト３を形成した後、第３図（ａ）に示す
ように、反応性イオンエッヂング（ｒｔ Ｉ Ｅ）また
はプラズマエツチング（Ｐ Ｅ”、 ）により、第２の
絶縁膜４に開口部を形成する、次に、フォトレジスト３
の除去を行った後、第３図（ｂ）に示すように、ｒ＞−
ｃｖｏ法等により、ウェハ全ｍｌに第１の絶縁膜２を形
成ずろ。次に、この第１の絶縁膜２を通して第２の絶縁
ｖ４をマスクにして所望の場所にイオン注入を行う。In addition, the j-th (in the method shown in FIGS. (a) and (b), the second insulating film 4 is first formed on the GaAs substrate 1)) -
It is formed by CVD method or the like. Next, after forming the ref I/resist 3 by photolithography, as shown in FIG. 2, an opening is formed in the insulating film 4, and then a photoresist 3 is formed.
After removing r>− as shown in FIG. 3(b),
The first insulating film 2 is formed on the entire ml of the wafer by the CVO method or the like. Next, ions are implanted into desired locations through the first insulating film 2 using the second insulating layer v4 as a mask.
上記の１うな従来のイオン注入法のうち、第２図に示さ
れる方法では、フォトレンスト３にもイＩノン主人され
てしまうので、フォＩ・レジスト３自身が硬化変質し−
Ｃしまい、次工程でのフォ）・レジスト３の除去が不完
全になるという問題点があり、第３図（ａ）、（ｂ）に
示される方法では工程が複雑になるうえ、工程途中でＧ
ａＡｓ基板１の表面が露出されるため、その部分の表面
が不安定になる等の問題点があった。Among the conventional ion implantation methods mentioned above, in the method shown in FIG.
There is a problem that the removal of the photoresist 3 in the next process is incomplete, and the process shown in FIGS. 3(a) and 3(b) complicates the process. G
Since the surface of the aAs substrate 1 is exposed, there are problems such as the surface of that part becoming unstable.
この発明は、かかる問題点を解決するためになされたも
ので、フォトレンストを完全に除去でき、表面の安定性
を損なうことのないイオン注入法を得ることを目的とす
る。The present invention was made to solve these problems, and aims to provide an ion implantation method that can completely remove photoresist without impairing surface stability.
この発明に係るイオン注入法は、半導体基数の表面にプ
ラズマＣＶＤ法を用いて形成１７た膜厚の薄い第１の絶
縁膜上に同一条件のプラズマＣＶＤ法を用いて膜質がや
や異なり膜厚の厚い第２の絶縁膜を形成ずろ上程と、写
真製版に」：るフォトＬ・ジス）・をマスクに（７て反
応性イオンエツチングまたはプラズマエツチングをプラ
ズマ発光分光分析によっ゛Ｃ発光強度の変化が検出され
るまで行−）で第２の絶縁膜のみを部分的にエツチング
除去する」−程と、第２の絶縁膜をマスクとし第１の絶
縁膜を通して不純物をイオン注入する工程とを含むもの
である。In the ion implantation method according to the present invention, a thin first insulating film is formed on the surface of a semiconductor substrate using a plasma CVD method. During the process of forming a thick second insulating film, reactive ion etching or plasma etching was performed using a photolithography mask as a mask (7) and the change in the emission intensity was measured by plasma emission spectroscopy. The second insulating film is partially etched away until the first insulating film is detected, and the second insulating film is used as a mask to implant impurity ions through the first insulating film. It is something that
この発明においては、プラズマ発光分光分析によって発
光強度の変化が検出された時点で第２の絶縁膜が除去さ
れたことが検出され、この後、第２の絶縁膜をマスクと
し第１の絶縁膜を通して不純物がイオン注入されろ。In this invention, removal of the second insulating film is detected at the time when a change in emission intensity is detected by plasma emission spectroscopy, and then the first insulating film is removed using the second insulating film as a mask. Impurities are ion-implanted through the
第１図（ａ）〜（Ｃ）は乙の発明のイオン注入法の一実
施例を説明するための図である。FIGS. 1(a) to 1(C) are diagrams for explaining an embodiment of the ion implantation method of the invention of B.
これらの図において、第３図（ａ）、（ｂ）と同一符号
は同一部分を示し、５はＰ −ＣＶ Ｄ法により形成さ
れた膜厚の薄い第１の絶縁膜、６は前記第１の絶縁膜５
の上に同様の条件によって形成された膜厚の厚い第２の
絶縁膜である。In these figures, the same reference numerals as in FIGS. 3(a) and 3(b) indicate the same parts, 5 is a thin first insulating film formed by the P-CVD method, and 6 is the first insulating film. Insulating film 5
This is a thick second insulating film formed under similar conditions.
次に、この発明のイオン注入法について説明ずろ。Next, the ion implantation method of this invention will be explained.
まず、ＧａＡｓ基板１の表面にＰ−ＣＶＤ法により第１
の絶縁膜５を形成する。この第１の絶縁膜５（，１、Ｇ
ａ Ａ ｓ基板１の表面を保謁するとともに、注入原
子の深さ方向の濃度分量のばらつきを小さくするための
ものであり、例えば膜種としてシリコン酸化膜、膜厚ど
して３００〜１０００人が選ばれる。ｒＡＨ’Ａが完了
するとＧａＡｓ基板１の入っているプラズマ反応室をＮ
２パーンし、続いて再び真空引の後、同様にして第１図
（ａ）に示すように第２の絶縁膜６を形成する。この第
２の絶縁膜６はイオン注入の注入原子に対するマスク効
果と、注入後の熱処理時における基板表面の安定化を目
的としているので、例えば膜種として第１の絶縁膜５と
同じシリコン酸化膜、膜厚として／１．０ （１０〜８
０００人が選ばれる。First, a first layer is deposited on the surface of the GaAs substrate 1 by the P-CVD method.
An insulating film 5 is formed. This first insulating film 5 (,1,G
This is to protect the surface of the substrate 1 and to reduce variations in the concentration of implanted atoms in the depth direction. For example, the film type is a silicon oxide film, and the film thickness is 300 to 1000. is selected. When rAH'A is completed, the plasma reaction chamber containing the GaAs substrate 1 is turned to N.
After performing two rounds and then evacuation again, a second insulating film 6 is formed in the same manner as shown in FIG. 1(a). The purpose of this second insulating film 6 is to have a masking effect on implanted atoms during ion implantation and to stabilize the substrate surface during heat treatment after implantation. , film thickness /1.0 (10~8
000 people will be selected.
次に写真製版技術によってイオン注入すべき所を残して
フォトレジスト
ブイオンエツチング（Ｒ ｉ Ｅ）またはプラズマエツ
チング（ＰＥ）により、第１図（ｂ）に示すように第２
の絶縁膜６のみを部分的にエツチング除去する。Next, the photoresist is etched by ion etching (R i E) or plasma etching (PE), leaving the areas to be ion implanted using photolithography, as shown in FIG. 1(b).
Only the insulating film 6 is partially etched away.
ここで問題となるのは、エツチングの停止時期を検出す
る方法である。The problem here is how to detect when etching should stop.
Ｊ 、Ｅｌｅｅｔｒｏｒ．ｈｍ． Ｓｏｅ，Ｖｏｌ．、
１ ３ ３ Ｎｏ．５ Ｐ９７０にも記載されてい
るように、Ｐ−ＣＶＩ）７去により成膜過程のごく初期
においては膜質のやや異なった膜が生成されろことが知
られている。また、第［の絶縁膜５および第２の絶縁膜
６も同質の膜であるが、両名は先に述べたように連続１
７で成膜され′Ｃはいないので、その膜質は異なってい
る。J, Eleetror. hm. Soe, Vol. ,
1 3 3 No. As described in 5 P970, it is known that the removal of P-CVI) 7 may produce a film with slightly different film quality at the very early stage of the film forming process. Further, the first insulating film 5 and the second insulating film 6 are also films of the same quality, but as mentioned earlier, they are continuous.
Since the film was formed in No. 7 and no 'C is present, the film quality is different.
すなわら、この発明では、エツチング中にプラズマ発光
分光分析を行うことにより、発光強度が変化するこれら
の界面を検出できる。したがって、この時、エツチング
を停止すれば、第１図（ｈ）に示すように、第１の絶縁
膜５のみを残すことができるわけである。That is, in the present invention, by performing plasma emission spectrometry during etching, it is possible to detect these interfaces where the emission intensity changes. Therefore, if etching is stopped at this time, only the first insulating film 5 can be left as shown in FIG. 1(h).
そして、次にフォトレジスト
有機溶剤で醍解除去した後、イオン注入を行えば所望の
不純物注入領域を形成することができる。Then, after removing the photoresist by dissolving it with an organic solvent, a desired impurity implantation region can be formed by performing ion implantation.
なお、上記実施例では、ＧａＡｓ半導体について説明し
たが、Ｓｉ半導体についても応用が可能であることはい
うまでもない。In the above embodiment, a GaAs semiconductor was explained, but it goes without saying that the present invention can also be applied to a Si semiconductor.
この発明は以上説明したとおり、半導体基板の表面にプ
ラズマＣＶＤ法を用いて形成した膜厚の薄い第１の絶縁
膜上に同一条件のプラズマＣＶＤ法を用いてＶ質がやや
異なり膜厚の厚い第２の絶縁膜を形成する工程と、写真
製版によるフォト１／ジス）・ヲマスクに１７で反応性
イオンエツチンクまたはプラズマエツチングをプラズマ
発光分光分析によっ′Ｃ発光強度の変化が検出されるま
で行って第２の絶縁膜のみを部分的にエツチング除去す
る工程と、第２の絶縁膜をマスクとし第１の絶縁膜を通
して不純物をイオン注入する工程とを含むので、成膜工
程をそれはとヤＶ雑にすることなく第１および第２の絶
縁Ｈ％を連続形成して半導体基板の表面を安定化するこ
とができ、また、フォトレジスト
ォトレジスト
り等の工程不良の発生ずる頻度を激減できるという効果
がある。As explained above, the present invention uses a thin first insulating film formed by plasma CVD on the surface of a semiconductor substrate using plasma CVD under the same conditions to form a thick film with slightly different V quality. Step 17 of forming the second insulating film, and applying reactive ion etching or plasma etching to the photolithography mask until a change in C emission intensity is detected by plasma emission spectroscopy. The film forming process is different from that of the first insulating film because it includes the step of partially etching away only the second insulating film, and the step of implanting impurity ions through the first insulating film using the second insulating film as a mask. The surface of the semiconductor substrate can be stabilized by successively forming the first and second insulating layers without causing V noise, and the frequency of occurrence of process defects such as photoresist photoresist processing can be drastically reduced. There is an effect.
第１図はこの発明のイオン注入法の一実施例を説明する
ための図、第２図，第３図は従来のイオン注入法を説明
するための図である。
図において、１はＧａＡｓ基板、３はフ第１・レジスト
、５は第１の絶縁膜、６は第２の絶縁膜である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第１図
３、７才トレヅスト
第２図
第３図
手続補正書（自発）FIG. 1 is a diagram for explaining an embodiment of the ion implantation method of the present invention, and FIGS. 2 and 3 are diagrams for explaining a conventional ion implantation method. In the figure, 1 is a GaAs substrate, 3 is a first resist, 5 is a first insulating film, and 6 is a second insulating film. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 3, 7-year-old Trezist Figure 2 Figure 3 Procedural amendment (voluntary)
Claims (1)
であって、半導体基板の表面にプラズマＣＶＤ法を用い
て形成した膜厚の薄い第１の絶縁膜上に同一条件のプラ
ズマＣＶＤ法を用いて膜質がやや異なり膜厚の厚い第２
の絶縁膜を形成する工程と、写真製版によるフォトレジ
ストをマスクにして反応性イオンエッチングまたはプラ
ズマエッチングをプラズマ発光分光分析によって発光強
度の変化が検出されるまで行って前記第２の絶縁膜のみ
を部分的にエッチング除去する工程と、前記第２の絶縁
膜をマスクとし前記第１の絶縁膜を通して不純物をイオ
ン注入する工程とを含むことを特徴とするイオン注入法
。An ion implantation method used in the manufacturing process of semiconductor devices, in which the film quality is improved using the plasma CVD method under the same conditions on a thin first insulating film formed using the plasma CVD method on the surface of the semiconductor substrate. The second film is slightly different and thicker.
forming an insulating film, and performing reactive ion etching or plasma etching using a photolithographic photoresist as a mask until a change in emission intensity is detected by plasma emission spectrometry analysis to form only the second insulating film. An ion implantation method comprising the steps of partially etching away, and implanting impurity ions through the first insulating film using the second insulating film as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26315586A JPS63116422A (en) | 1986-11-05 | 1986-11-05 | Ion implanting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26315586A JPS63116422A (en) | 1986-11-05 | 1986-11-05 | Ion implanting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63116422A true JPS63116422A (en) | 1988-05-20 |
Family
ID=17385561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26315586A Pending JPS63116422A (en) | 1986-11-05 | 1986-11-05 | Ion implanting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63116422A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208173A (en) * | 1990-03-20 | 1993-05-04 | Kabushiki Kaisha Toshiba | Method of manufacturing non-volatile semiconductor memory device |
-
1986
- 1986-11-05 JP JP26315586A patent/JPS63116422A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208173A (en) * | 1990-03-20 | 1993-05-04 | Kabushiki Kaisha Toshiba | Method of manufacturing non-volatile semiconductor memory device |
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