JPS63215040A - Method of hardening resist - Google Patents

Method of hardening resist

Info

Publication number
JPS63215040A
JPS63215040A JP4930287A JP4930287A JPS63215040A JP S63215040 A JPS63215040 A JP S63215040A JP 4930287 A JP4930287 A JP 4930287A JP 4930287 A JP4930287 A JP 4930287A JP S63215040 A JPS63215040 A JP S63215040A
Authority
JP
Japan
Prior art keywords
resist
hardening
resist pattern
pattern
treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4930287A
Other languages
Japanese (ja)
Inventor
Makoto Onuma
誠 大沼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP4930287A priority Critical patent/JPS63215040A/en
Publication of JPS63215040A publication Critical patent/JPS63215040A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a stable effect of hardening, and realize a fine resist pattern of high accuracy, by applying a heating process at a temperature lower than the heat resisting temperature of a resist to the resist before the light radiation for hardening the resist. CONSTITUTION:A resist pattern 2 is formed on the main surface of a substrate 1. By applying a baking treatment as a treatment before UV radiation, a resist pattern 3 for which baking is finished is obtained. The above baking treatment is performed so as to heat the whole resist pattern 2 for 15 min at a temperature of 150 deg.C. By radiating UV rays 6 for 1 min, a UV-irradiated resist pattern 4 is obtained. By applying a baking treatment to heat the whole pattern 4 for 30 min at a temperature of 200 deg.C, a resist pattern 5 subjected to a hardening treatment is obtained. Thereby, a fine resist pattern of high accuracy can be realized.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の製造工程で使用されるレジスト
のハードニング方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for hardening resist used in the manufacturing process of semiconductor devices.

従来の技術 半導体装置は、回路の高集積化、微細化の方向へ進展し
ている。それに併って半導体装置の微細構造を形成する
際のリソグラフィ一工程では、レジストパターンの高精
度化が要求され、高解像度の露光技術とともに、耐ドラ
イエツチ性等を考慮したベーキング処理が重要となる。
2. Description of the Related Art Semiconductor devices are progressing toward higher integration and miniaturization of circuits. In line with this, high precision resist patterns are required in the lithography process for forming fine structures of semiconductor devices, and high-resolution exposure techniques and baking treatments that take into account dry etch resistance and the like are important.

そのためにレジストのハードニング技術としてUVハー
ドニングの手法が、近年注目を集めている。
For this reason, UV hardening has been attracting attention in recent years as a resist hardening technique.

f?“  −;り1し    しイe−?)ト”   
/2+L今レイψ−し五“λセ     ハ12−;ス
°。
f? “-;ri1shiie-?)to”
/2+L now Ray ψ-shi five "λ se ha 12-;su°.

of Single 1ayer and multi
layer resist patternsMatt
hews、 John 1.Williott、Jr、
 1984年5PIE)や(UVハードニング装装置9
問 7月 ULSI)等にも記載されている様に、レジスト
のハードニングに効果のあることが、知られている。標
準的なUVハードニングプロセスの例を第2図に従って
説明する。
of Single 1ayer and multi
layer resist patternsMatt
hews, John 1. Williott, Jr.
1984 5PIE) and (UV hardening equipment 9
It is known to be effective in hardening the resist, as described in the ULSI, July 2013. An example of a standard UV hardening process is explained according to FIG.

先ず、第2図aに示すように、周知のリソグラフィー技
術によって基板1の上に、レジストパターン2を形成し
たのち、第2図すに示すように、紫外光(UV光)6を
照射してUV照射レジストパターン4を得る。次いで、
第2図Cに示すように、UV照射後に、レジストパター
ンの全体を加熱するベーキング処理を施すことで、ハー
ドニング処理が施されたレジストパターン5が得られる
First, as shown in FIG. 2a, a resist pattern 2 is formed on a substrate 1 by a well-known lithography technique, and then ultraviolet light (UV light) 6 is irradiated as shown in FIG. A UV irradiation resist pattern 4 is obtained. Then,
As shown in FIG. 2C, after UV irradiation, a baking process is performed to heat the entire resist pattern, thereby obtaining a resist pattern 5 that has been subjected to a hardening process.

発明が解決しようとする問題点 従来の方法によると、レジストのUVハードニングの際
に、レジストのハードニングの効果とともに、レジスト
表面への皺の発生、レジスト中への気泡の発生などレジ
ストにとって好ましくない異常現象の発生する場合があ
る。したがって、従来の方法をそのまま半導体装置の製
造工程に適用した場合、このUVハードニングが不良発
生の原因となる問題点があった。
Problems to be Solved by the Invention According to the conventional method, during UV hardening of the resist, in addition to the effect of hardening the resist, wrinkles are generated on the resist surface, bubbles are generated in the resist, etc., which are undesirable for the resist. Abnormal phenomena may occur. Therefore, when the conventional method is directly applied to the manufacturing process of semiconductor devices, there is a problem that this UV hardening causes defects.

ところで、皺の発生に関しては、前記の文献に記載され
ている装置の様に、UV照射をしながら基板ベークを行
なうことでこれを抑制することが可能であるが、レジス
トに発生する気泡までを抑えることはできなかった。特
に、レジスト膜厚が前記の問題点を排除する目的でなさ
れた本発明のハードニング方法は、レジストのハードニ
ングに用いる光照射の前に、レジストに対してレジスト
の有する耐熱温度よりも低い温度の加熱処理を加える方
法である。
Incidentally, the generation of wrinkles can be suppressed by baking the substrate while applying UV irradiation, as in the apparatus described in the above-mentioned literature, but it is also possible to suppress the formation of bubbles in the resist. I couldn't hold it back. Particularly, in the hardening method of the present invention, which has been made for the purpose of eliminating the above-mentioned problems, the resist film thickness is set at a temperature lower than the heat resistance temperature of the resist before the light irradiation used for hardening the resist. This method involves adding heat treatment.

作用 本発明のハードニング方法によれば、微細レジストパタ
ーンに対して、異常現象を発生さセることな(、安定な
ハードニング処理を施すことができる。
Effect: According to the hardening method of the present invention, a stable hardening process can be performed on a fine resist pattern without causing abnormal phenomena.

実施例 本発明のハードニング方法について第1図を参照して説
明する。先ず、第1図aで示す様に、周知のフォトリソ
グラフィー技術によって基板1の主面上に、レジストパ
ターン2を形成する。次いで、第1図すで示す様にUV
照射前の処理として、レジストパターンの全体に150
℃で15分間加熱するベーキング処理を施すことによっ
て、ベーキング済のレジストパターン3を得る。このの
ち、第1図Cで示すようにUV光6による照射を1分間
にわたって施すことによってUV照射レジストパターン
4を得る。次いで、第1図すで示すようにレジストパタ
ーンの全体を200℃の温度で30分間にわたり加熱す
るベーキング処理を施すことによって、ハードニング処
理が施されたレジストパターン5が得られる。
EXAMPLE The hardening method of the present invention will be explained with reference to FIG. First, as shown in FIG. 1a, a resist pattern 2 is formed on the main surface of a substrate 1 by a well-known photolithography technique. Next, as shown in Figure 1, UV
As a treatment before irradiation, the entire resist pattern is coated with 150%
A baked resist pattern 3 is obtained by performing baking treatment at .degree. C. for 15 minutes. Thereafter, as shown in FIG. 1C, irradiation with UV light 6 is performed for 1 minute to obtain a UV irradiated resist pattern 4. Next, as already shown in FIG. 1, the entire resist pattern is subjected to a baking process in which the resist pattern is heated at a temperature of 200° C. for 30 minutes, thereby obtaining a resist pattern 5 that has been subjected to a hardening process.

ところで、このような方法でハードニング処理を施すこ
とによって抑制がなされるレジスト異常の発生の原因と
しては、次の事が考えられる。先ず、皺の発生であるが
、この皺は、レジストの光透過率が低いと、UV光によ
る照射がレジストの深さ方向に沿って不均一となり、レ
ジスト表面のみが架橋結合反応を起こして表面のみ硬く
なった状態が生じることにより発生する。しかしながら
、本発明のハードニング方法では、UV光照射の前に施
すベーキング処理により、レジストの溶剤等が抜け、レ
ジストの内部で一定の硬化反応が進行しているため、皺
の発生を抑えることができる。
Incidentally, the following may be considered as the cause of the occurrence of resist abnormalities that can be suppressed by performing hardening treatment using such a method. First, wrinkles occur.When the light transmittance of the resist is low, the UV light irradiation becomes uneven along the depth direction of the resist, causing a crosslinking reaction only on the resist surface, causing the surface This occurs due to the formation of a hardened state. However, in the hardening method of the present invention, the baking treatment performed before UV light irradiation removes the solvent, etc. from the resist, and a certain hardening reaction progresses inside the resist, so it is difficult to suppress the generation of wrinkles. can.

次に、レジストの気泡の発生であるが、この気泡はレジ
ストにUV光を照射した際に、架橋結合反応と同時にナ
フトキノンジアザイドの光分解が進行し、チッ素を発生
する事が原因となり発生するものと考えられる。
Next is the generation of bubbles in the resist. These bubbles occur because when the resist is irradiated with UV light, photodecomposition of naphthoquinone diazide proceeds at the same time as the crosslinking reaction, generating nitrogen. It is considered that

しかしながら、本発明のハードニング方法では、UV照
射前にベーキングすることにより、感光基であるナフト
キノンジアザイドが熱分解するために、UV照射時のチ
ッ素の発生が抑えられるところとなり、気泡の発生が抑
えられる。
However, in the hardening method of the present invention, by baking before UV irradiation, naphthoquinone diazide, which is a photosensitive group, is thermally decomposed, so the generation of nitrogen during UV irradiation is suppressed, and the generation of bubbles. can be suppressed.

発明の効果 本発明によれば、各種レジストに対して、UVハードニ
ング処理を施してもレジストへの異常の発生を抑えるこ
とができ、したがって安定したハードニングの効果が得
られるため、微細レジストパターンの高精度化をはかる
ことができる効果が奏される。
Effects of the Invention According to the present invention, even if various resists are subjected to UV hardening treatment, the occurrence of abnormalities in the resist can be suppressed, and a stable hardening effect can therefore be obtained. This has the effect of increasing precision.

【図面の簡単な説明】 第1図は本発明のUVハードニング方法を説明するため
の工程図、第2図はハードニング方法を説明するための
工程図である。 l・・・・・・基板、2・・・・・・リソグラフィーに
より形成されたレジストパターン、3・・・・・・UV
照射前のベーキング処理が施されたレジストパターン、
4・・・・・・UV照射されたレジストパターン、5・
・・・・・UV照射後のベーキング処理が施されたレジ
ストパターン、6・・・・・・UV光。 代理人の氏名 弁理士 中尾敏男 ほか1名l −甚 
 抜 ? −リソグラフィーにより形成2獣だしラストパター
ン 3−UV=、射的のペーキンジ処I!がz7戯たしシス
トパターン 4−’LIV!!、射ざ名だレジストパターン5−uv
=、w渣のベーキング処理が なざ剋たしシストパターン 第2図 (C) い
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a process diagram for explaining the UV hardening method of the present invention, and FIG. 2 is a process diagram for explaining the hardening method. 1...Substrate, 2...Resist pattern formed by lithography, 3...UV
Resist pattern subjected to baking treatment before irradiation,
4...Resist pattern irradiated with UV, 5.
...Resist pattern subjected to baking treatment after UV irradiation, 6...UV light. Name of agent: Patent attorney Toshio Nakao and 1 other person
Without it? - Formed by lithography 2 beasts and last pattern 3 - UV=, Shooting page processing I! But z7 play cyst pattern 4-'LIV! ! , Izanameda resist pattern 5-uv
=、W The baking process of the residue has deteriorated and the cyst pattern is shown in Figure 2 (C).

Claims (1)

【特許請求の範囲】[Claims] 基板上に形成したレジストをパターニングしたのち、同
レジストパターンにその耐熱温度以下の温度でベーキン
グ処理を施し、次いで、遠紫外光および紫外光を含む光
をレジストに照射することを特徴とするレジストのハー
ドニング方法。
After patterning a resist formed on a substrate, the resist pattern is subjected to baking treatment at a temperature below its heat resistance temperature, and then the resist is irradiated with light containing deep ultraviolet light and ultraviolet light. Hardening method.
JP4930287A 1987-03-04 1987-03-04 Method of hardening resist Pending JPS63215040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4930287A JPS63215040A (en) 1987-03-04 1987-03-04 Method of hardening resist

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4930287A JPS63215040A (en) 1987-03-04 1987-03-04 Method of hardening resist

Publications (1)

Publication Number Publication Date
JPS63215040A true JPS63215040A (en) 1988-09-07

Family

ID=12827140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4930287A Pending JPS63215040A (en) 1987-03-04 1987-03-04 Method of hardening resist

Country Status (1)

Country Link
JP (1) JPS63215040A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0669119A (en) * 1992-06-18 1994-03-11 Internatl Business Mach Corp <Ibm> Method for holding of line width of photosensitive polyimide pattern
JP2010113270A (en) * 2008-11-10 2010-05-20 Toppan Printing Co Ltd Method for manufacturing minute three-dimensional structure, and exposure mask used for same
JP2016213438A (en) * 2015-04-30 2016-12-15 東京エレクトロン株式会社 Substrate processing method, substrate processing apparatus, and substrate processing system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0669119A (en) * 1992-06-18 1994-03-11 Internatl Business Mach Corp <Ibm> Method for holding of line width of photosensitive polyimide pattern
JP2010113270A (en) * 2008-11-10 2010-05-20 Toppan Printing Co Ltd Method for manufacturing minute three-dimensional structure, and exposure mask used for same
JP2016213438A (en) * 2015-04-30 2016-12-15 東京エレクトロン株式会社 Substrate processing method, substrate processing apparatus, and substrate processing system

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