JPS63114490A - Rgb signal processing circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit by inputting one analog signal of red, green and blue and one digital signal for controlling a switching or a brightness respectively in a first and a second signal processing circuits and inputting a residual analog signal in a third signal processing circuit and respectively processing. CONSTITUTION:After a red (R) signal is converted into a digital signal by an A/D converter 5 in a signal processing circuit block 21, one bit compressed, LSB1 bit deleted and one bit of a high speed switching YS signal is added. Then, it is selectively written in a memory 26 or 27 by a switch circuit S1, read by a switch circuit S2 to separate the YS signal and transmitted to an output terminal 17. The R signal is transmitted to an output terminal 9 through a D/A converter 8. Then, in a signal processing block 22, a blue (B) signal and a brightness control (YM) signal are similarly processed. In a signal processing block 23, only a green (G) signal is processed. Thereby, a circuit constitution is simplified and a cost can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvement of RGB signal processing circuits, and in particular, R, G, and B analog signals in image processing, YS signals of high-speed switching signals, and luminance signals. This invention relates to a signal processing circuit that simultaneously processes (for example, scan converts) YM multiplied signals in which the signal is set to an intermediate strength.

(Prior art) When superimposing R, G, and B signals, which are analog video signals, on a television (TV) signal,
It is well known that digital signals such as YS and YM are required. YS signals are R and G.

ON of the B signal (hereinafter also referred to as rRGB signal), (a digital signal that controls the FF, and a (control) signal for lowering the luminance (attenuating the luminance signal) other than the YM multiplication signal RGB signal. It is.

First, the principle of doubling the density of these signals will be explained with reference to FIG. FIG. 2 is a block diagram showing the principle of a conventional RGB signal processing circuit 10.

The R signal supplied to the input terminal 4 of the R signal processing circuit block 1 of each signal processing circuit block (scan converter circuit) constituting the RGB signal processing circuit 10 is
The signal is converted into a digital signal by a converter 5, and is alternately supplied to memories (storage units) 6 and 7 via a switch circuit S1 switched in synchronization with a horizontal synchronizing signal, and written at the clock frequency IC. The switch circuit S2 switches complementary to the switch circuit S1, and the memories 6 and 7
The contents stored in the D/A converter 8 are alternately supplied to the D/A converter 8. The D/A converter 8 converts the digitized R signal back into an analog signal and sends it to the output terminal 9. Now, when the switch circuit S1 is connected to the memory 6, the switch circuit S2 is connected to the memory 7 and reads its contents twice at a clock 2/c which is twice the writing frequency.
It has the function of doubling the input signal frequency. Therefore, from the output terminal 9, a signal with a frequency twice that of the R signal on the input side is output. When the switch circuit S1 is connected to the memory 7 side, the switch circuit S2 is connected to the memory 6 side.
The contents are read twice with a clock twice the write frequency /C, and the same zero operation is repeated thereafter. Also, G
Signal processing circuit block 2 and B signal processing circuit block 3
However, the G signal and B signal are supplied from each input terminal 11.13, and the same signal processing as in the R signal processing circuit block 1 is performed, and a signal with twice the frequency is outputted to each output terminal 12.14. do. Note that since the YS signal and the YM multiplied signal are originally digital signals, the YS signal processing circuit block 1
5 and the YM signal processing circuit block 18, the A/D converter 5 and the D/D converter in the R signal processing circuit block 1
The A converter 8 is no longer necessary, and the same signal processing as in the above R signal processing circuit block 1 is performed using only the switch circuits 81 and 82 and the memory 6.7, and the frequency is doubled from the respective output terminals 17°29. Output a signal.

[Problem that the invention seeks to solve]

The above Ys signal and YM double signal are actually ON/(R, G, since they only have 1-bit information of FF).

Signals with a lot of information, such as the B signal, are processed in the same way as in the analogy of "gyutou side horn", and the memory (
Yong Eun) will be wasted. In actual scan converter circuits, signal processing such as line interpolation is often performed in order to improve the image quality, and in this case there is a drawback that there is even more waste.

[Means for solving problems]

Therefore, the RGB signal processing circuit of the present invention has R, G signal processing circuits.

After inputting one of the analog signals of B and one of the digital signals of YS and YM and performing signal processing, the nine signals are individually output from two output terminals. The first signal processing circuit block outputs the signals to the first signal processing circuit block, one of the two analog signals of RlG and B that is not supplied to the first signal processing circuit block, and the digital signals of Ys and YM. a second signal processing circuit block that inputs the remaining one digital signal that was not supplied to the first signal processing circuit block, performs signal processing, and then outputs both signals individually from two output terminals; and a third signal processing circuit block that inputs only one remaining analog signal among the R, G, and B analog signals, performs signal processing, and then outputs the analog signal from one output terminal. Further, the first and second signal processing circuit blocks each input one of the R, G, and B analog signals and convert 1% A into the digital signal.
The output signals of the /D converter and this A/D converter are compressed bit by bit, and the YS signal or YM times signal is added to the compressed remaining 1 bit, respectively, and then the first and second
a first switch circuit selectively supplying the memory to the memory;
Contrary to this first switch circuit, there is a second switch circuit that is connected to the first and second memories and takes out the information stored in each memory, and a second switch circuit that outputs the output signal of this second switch circuit. Of which, R and G converted to digital signals
, B Takes either signal and converts it back to an analog signal D/
In addition, by configuring the input signal to the third Ig processing circuit block as a G analog signal, the drawbacks of the conventional circuit described above are eliminated, and the visual The circuit could be simplified without deteriorating the characteristics (picture T!), thereby reducing the number of parts and power consumption.

(Example) Referring to FIG. 1, an RGB signal processing circuit 20 of the present invention
A specific example will be described. In this figure, the same components as those of the conventional circuit shown in FIG. 2 are given the same reference numerals, and detailed explanation thereof will be omitted. 1st
In the figure, 21 is an R, YS signal processing circuit block;
2 is a B, YM signal processing circuit block, 23 is a G signal processing circuit block, and when compared with the conventional circuit shown in FIG.
The number of signal processing circuit blocks is reduced from five to three, simplifying the circuit.

Next, the configuration and operation of each signal processing circuit block will be explained. First, the R, Ys signal processing circuit block 21 (
The first signal processing circuit block) has an R signal input terminal 4.
Two input terminals, the YS signal input terminal 16 and the R signal output terminal 9. It has two output terminals, a YS signal output terminal 17. Similarly, B, YM signal processing circuit block 22
(second signal processing circuit block) also has two input terminals, a B signal input terminal 13 and a YM signal input terminal 19, and a B signal output terminal 14. The YM signal output terminal 29 has two output terminals. Note that the G signal processing circuit block 23
(Third signal processing circuit block), like the G signal processing circuit block 2 in the conventional circuit 10, has input and output terminals (
11 and 12), and the circuit configuration and operation inside the block are exactly the same as the G signal processing circuit block 2, so a detailed explanation thereof will be omitted.

In the R, YS signal processing circuit block 21, the R signal is converted into a digital signal by the A/D converter 5, and then compressed by 1 bit (or converted into an A/D signal with a lower 1-bit processing ability).
It is convenient to use a D converter because it automatically compresses 1 bit during A/D conversion). In this way LS
The B1 pit is deleted, and 1 bit of the YS signal is added thereto (this signal will be referred to as the "rR, YS composite signal"). The R, YS composite signal is sent to the next stage switch circuit SI.
The horizontal frequency is doubled by being selectively written into the memory 26 or 27 at the clock frequency /C and read out twice by the next stage switch circuit S2 at twice the clock frequency 2/c. It is. Then R
, separates the YS signal from the YS composite signal and outputs it to output terminal 1.
Send on 7. On the other hand, the remaining R signal (component) is converted back to an analog signal by the D/A converter 8 and then sent to the output terminal 9. In this case, the R signal is degraded by 1 bit compression, but since only the SB 1 bit is deleted, there is no problem in practical use.

Next, regarding the B*YM signal processing circuit block 22, in the explanation of the configuration and operation of the R, YS signal processing circuit block 21, 11 RPI, IJ Y S
Since it is sufficient to read N as "B II, lj Y Ml'," detailed explanation thereof will be omitted.

In the above explanation, it was assumed that the R signal and the Ys (No. 5) were combined, and the B signal and the YM multiplied signal were combined and signal processing was performed in one processing circuit block 21 and 22, respectively. Without limitation, the B signal and the Ys multiplied signal may be combined, and the R signal and the YM multiplied signal may be combined to perform signal processing respectively.Also, instead of the R signal or the B signal, the G signal and the Ys multiplied signal may be combined. It may be configured to perform signal processing in combination with either the Ys multiplied signal or the YM multiplied signal, but the R (red) signal and B
Since the (blue) signal is less sensitive to the human eye, it is preferable to process the G signal among the three R, G, and B signals using a single signal processing circuit block, as in the above example. .

In addition, R1 for adding both Y S * Y H signals
It is also possible to perform signal processing for each RGB signal in the same pit without performing compression processing for each B signal, or for general R, G, B, YS.

In the signal processing circuit for each YM signal, the RGB signal and Y
It is of course possible to add the YS and 'YM signals to any of the R, G, and B signals and process them separately in the same way as the processing in the scan converter circuit described above, where the S and YM multiplied signals are commonly used. .

〔Effect of the invention〕

Since the RGB signal processing circuit of the present invention is configured as detailed above, a dedicated signal processing circuit block is not required for YS signal and YM multiplied signal processing, and the circuit configuration can be simplified without deteriorating the characteristics. It has excellent practical effects, such as being able to reduce costs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an RGB signal processing circuit according to the present invention, and FIG. 2 is a block diagram of a conventional circuit. 5... A/D converter, 8... D/A converter, 20.
...RGB signal processing circuit, 21...RI YS signal processing circuit block (first signal processing circuit block), 22
...B, Y, signal processing circuit block (second signal processing circuit block), 23...G signal processing circuit block (
3rd signal processing circuit block), 25... Faith synthesizer, 26.27... Memory (storage unit), S+, S2.
...Switch circuit.

Claims (4)

[Claims] (1) Five input terminals for inputting R (red), G (green), B (blue) analog signals and Y_S, Y_M digital signals, and R, G, B after signal processing. ,Y_S
, Y_M signals, and one of the R, G, and B analog signals and each of the Y_S and Y_M digital signals. A first signal processing circuit block inputs one of the digital signals, performs signal processing, and then outputs both signals individually from two output terminals; 2 of which were not supplied to the first signal processing circuit block.
one of the analog signals and the above Y_S,
A second circuit inputs the remaining one digital signal that was not supplied to the first signal processing circuit block among the Y_M digital signals, performs signal processing, and then outputs both signals individually from two output terminals. a signal processing circuit block,
A third signal processing circuit block inputs only one remaining analog signal among the R, G, and B analog signals, performs signal processing, and then outputs the analog signal from one output terminal. An RGB signal processing circuit characterized by: (2) The first and second signal processing circuit blocks are each an A/D that inputs any one of the R, G, and B analog signals and converts it into a digital signal.
The output signal of the converter and this A/D converter is compressed bit by bit, and the Y_S signal or Y_M signal is added to the compressed and remaining 1 bit, and then selectively supplied to the first and second memories. a second switch circuit that is connected to the first and second memories and retrieves information stored in each memory, which is contradictory to the first switch circuit; Of the output signals of the switch circuit, R converted into the above digital signal
, G, and B signals and a D/A converter for converting the signals back into analog signals. (3) The input signal to the third signal processing circuit block is configured as an analog signal of the above G.
The RGB signal processing circuit described in . (4) The RGB signal processing circuit according to claim 1 or 2, wherein the signals to be compressed bit by bit are R and B signals.