JPS63114195A - Ceramic wiring board and manufacture of the same - Google Patents
Ceramic wiring board and manufacture of the sameInfo
- Publication number
- JPS63114195A JPS63114195A JP6271686A JP6271686A JPS63114195A JP S63114195 A JPS63114195 A JP S63114195A JP 6271686 A JP6271686 A JP 6271686A JP 6271686 A JP6271686 A JP 6271686A JP S63114195 A JPS63114195 A JP S63114195A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- metal plating
- wiring board
- pattern
- resin resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 26
- 239000011347 resin Substances 0.000 claims description 24
- 229920005989 resin Polymers 0.000 claims description 24
- 238000007747 plating Methods 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 6
- 238000012546 transfer Methods 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 claims 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 150000007513 acids Chemical class 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229920000298 Cellophane Polymers 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 235000013405 beer Nutrition 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（産業上の利用の分野）
この発明は、セラミック板面に回路パターンに沿って凹
状部を形成し、この凹状部に金属メッキ被膜層を形成し
たセラミック配線基板とその製法に関する。[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to a ceramic wiring board in which a concave portion is formed on a ceramic board surface along a circuit pattern, and a metal plating layer is formed in the concave portion. Regarding the manufacturing method.
（従来の技術）
従来、電子回路配線基板として基材として、フェノール
樹脂、ガラス、エポキシ樹脂、セラミックス等が用いら
れている．これらの基板の表裏面上に銅、ニッケルの金
属箔又は金、銅、ニッケル、クロム等の金属のメッキを
施すか、これらの金属性薄板を貼着するかしている。(Prior Art) Conventionally, phenol resin, glass, epoxy resin, ceramics, etc. have been used as base materials for electronic circuit wiring boards. The front and back surfaces of these substrates are plated with metal foils of copper or nickel or metals such as gold, copper, nickel, chromium, etc., or thin plates of these metals are pasted.
（発明が解決しようとしている問題点）従来の基板は、
その表裏面に加工を施す方法であり、従って加工された
導体部が全て凸形状になっている、特にセラミックス板
を利用した電子回路配線基板は衝撃には弱いためその板
厚が１ｆｌ〜２ｓｍに限定されそれより薄いものは使用
されていない、従ってこのようなセラミックス板に凸形
状のぷ体部にＩＣチップ、抵抗体を装着すればそれだけ
肉厚になり薄肉傾向の時代の要請に応えられないことに
なる。セラミックス板が特にその放熱効果及びその絶縁
性の故に電子回路配線基板として理想的な特性を有して
いるが加工性及び成形性に難点を有している。一方電子
回路基板は極薄のものが要望されている。この発明は以
上の要望にこたえるものである。(Problem that the invention is trying to solve) The conventional board is
This is a method in which the front and back surfaces are processed, so that all the processed conductor parts have a convex shape.Especially, electronic circuit wiring boards using ceramic boards are weak against shock, so the board thickness is 1 fl to 2 sm. Therefore, if you attach an IC chip or a resistor to the convex body part of a ceramic plate like this, the wall becomes thicker and cannot meet the demands of the times when there is a tendency for thinner walls. It turns out. Ceramic plates have ideal properties as electronic circuit wiring boards, particularly because of their heat dissipation effects and their insulation properties, but they have drawbacks in workability and moldability. On the other hand, electronic circuit boards are required to be extremely thin. This invention meets the above needs.
（問題点を解決するための手段）
以下この発明を添付図面に示す実施例に従って説明する
。(Means for Solving the Problems) The present invention will be described below according to embodiments shown in the accompanying drawings.
その板厚が１）１）１〜２ｍ露程度のセラミックス板ｆ
ｉ１面に以下に述べるエツチング手段にて電気回路配線
パターン（２）に沿う凸面部（３）、凹面部（４）、貫
通部（５）を形成し、更に、この凸面部（３）、凹面部
（３）、貫通部（４）に金属メッキ加工の手段にて金属
メッキ被膜層よりなる回路導体部（６）を形成したセラ
ミック配線基板としたものである。Ceramic plate f whose plate thickness is about 1) 1 to 2 m
A convex part (3), a concave part (4), and a through part (5) along the electric circuit wiring pattern (2) are formed on the i1 surface by the etching method described below, and further, the convex part (3) and the concave part are This is a ceramic wiring board in which a circuit conductor part (6) made of a metal plating film layer is formed in the part (3) and the through part (4) by means of metal plating.
第２図に凹面部（３）、貫通部（４）には例えばＩＣチ
ップ、抵抗体のような電子部品（７）を挿入しである。In FIG. 2, an electronic component (7) such as an IC chip or a resistor is inserted into the concave part (3) and the through part (4).
次ぎに、このセラミック配線基板の製造方法に付いて述
べる。Next, a method for manufacturing this ceramic wiring board will be described.
近年、強力な紫外線の直接照射によってのみ硬化する紫
外線硬化性樹脂レジスト（以下ＵＶ樹脂レジストと称す
る）が半導体素子保護膜、半導体素子間！！ｔ 縁膜及
びイオン注入マスクレジスト等に使用されており、その
優れた特性が注目されている、ＵＶ樹脂レジストは耐薬
品性に優れており、酸性特に強酸性に対して強い耐性が
あるので、本願処理工程のセラミックスエツチング加工
、金属メッキ処理等によっても全く変化することはない
。In recent years, ultraviolet curable resin resists (hereinafter referred to as UV resin resists), which are cured only by direct irradiation with strong ultraviolet rays, have been developed as semiconductor element protective films and between semiconductor elements! ! UV resin resists, which are used in edge films and ion implantation mask resists, and are attracting attention for their excellent properties, have excellent chemical resistance and strong resistance to acids, especially strong acids. There is no change at all even in the ceramic etching process, metal plating process, etc. of the present processing process.
（イ）ＵＶ樹脂レジストの転写工程
上記し■樹脂レジストをセラミックス製品に絵柄、文字
及び電子回路等を転写する。(b) Transfer process of UV resin resist As described above, ■ Transfer patterns, characters, electronic circuits, etc. from the resin resist to ceramic products.
即ち、任意形状のセラミック製品の表裏面にｔＪＶ樹脂
レジストをスピンナ（約３０００回転）で約２０秒間回
転させＵＶ樹脂レジスト層（８）を塗布する。塗布後、
パターンフィルム（９）を前記ＵＶ樹脂レジスト層（８
）に重合してコンタクト方式により既存の露光装置によ
って露光し、上記セラミックス製品の表裏面に任意の絵
柄、文字及び電子回路等のパターン（２）を転写し、紫
外線照射部分のＵｖ樹脂レジスト被膜（８）を硬化した
後、現像処理を施しキニア（摂氏４００度で４０分放置
）後、未照射部分のＵＶ樹脂レジストを剥離液で除去す
る工程である。That is, a UV resin resist layer (8) is applied to the front and back surfaces of a ceramic product having an arbitrary shape by rotating the tJV resin resist with a spinner (about 3000 revolutions) for about 20 seconds. After application,
The pattern film (9) is applied to the UV resin resist layer (8).
) is polymerized and exposed using an existing exposure device using the contact method, patterns (2) such as arbitrary designs, letters, and electronic circuits are transferred to the front and back surfaces of the ceramic product, and a UV resin resist coating ( After curing 8), a development process is performed and the UV resin resist is removed in unirradiated areas using a stripping solution.
エツチング加工工程
即ち、前工程に於けるＵＶ樹脂レジストの任意の絵柄、
文字及び電子回路等を転写部を形成したセラミックス板
にセラミックスエツチング加工を施す。セラミックス板
の一例として、例えばアルミナセラミックスのエツチン
グについて概説すると、約１７０〜３００度に加熱され
たリン酸水溶、′夜にアルミナセラミックス基材を浸漬
するとＵＶ樹脂レジスト層（８）においてはエツチング
現象れず、逆にＵＶ樹脂レジスト除去面０のでは活発な
エツチング現象の発生が見られ、その結果必要とする電
子回路パターン等凸面部、凹面部又は貫通部として形成
されるものである。Any pattern on the UV resin resist in the etching process, that is, the previous process,
A ceramic etching process is applied to a ceramic plate on which characters, electronic circuits, etc. have been transferred. As an example of a ceramic plate, for example, to outline the etching of alumina ceramics, when the alumina ceramic base material is immersed in a phosphoric acid aqueous solution heated to about 170 to 300 degrees at night, no etching phenomenon occurs in the UV resin resist layer (8). On the other hand, on the surface 0 from which the UV resin resist has been removed, an active etching phenomenon is observed, and as a result, necessary electronic circuit patterns are formed as convex, concave, or penetrating portions.
金属メッキ工程
前工程のセラミックス板に対して無電解メッキ（金属メ
ッキ）を施すとＵＶ樹脂レしストＮ（８）には金属被１
）１層が形成されずＵＶ樹脂レしスト除去面α〔即ちセ
ラミック板のエツチング凹面部、または貫通部のみに金
属メッキ被膜層が形成される。When electroless plating (metal plating) is applied to the ceramic plate before the metal plating process, the UV resin rest N (8) has a metal coating 1.
) One layer is not formed and a metal plating layer is formed only on the UV resin rest removal surface α (that is, the etched concave surface portion or the penetration portion of the ceramic plate).
従って、セラミックス板の凸面部に金属メッキ披ＷＸＮ
を形成しようとする場合、露光時に使用するフィルムを
前記とは逆に使用することにより凸３面部に金属メッキ
被膜層を形成され、凸面部による回路導体部が形成され
るものである。Therefore, metal plating is applied to the convex surface of the ceramic plate.
When the film is to be formed, a metal plating film layer is formed on the three convex surfaces by using the film used during exposure in the opposite manner to that described above, and a circuit conductor section is formed by the convex surfaces.
以上の工程によって、セラミックス板の表裏面に描かれ
た絵柄、文字及び電子回路線画以外の面、即ち陽に対し
て金属メッキ被膜層によって描かれた絵柄、文字及び電
子回路線画は陰の画線が描かれたセラミックス配線基板
が得られる。Through the above process, the patterns, characters and electronic circuit line drawings drawn on the front and back surfaces of the ceramic plate are removed from the negative side, i.e., the negative drawings are removed by the metal plating layer. A ceramic wiring board on which is drawn is obtained.
（作用）
セラミックス板面に以下に述べるエツチング手段にて形
成された電気回路配線パターン（２）に沿う凹状部（２
）、貫通部（３）に電気回路配線部、ＩＣチップ、抵抗
体を随意に装着出来ることになる。(Function) A concave portion (2) along the electric circuit wiring pattern (2) formed on the surface of the ceramic plate by the etching method described below.
), an electric circuit wiring part, an IC chip, and a resistor can be attached to the through part (3) at will.
（発明の効果）
セラミック配線基板として、上述のようにセラミックス
仮＋１）面に電気回路配線パターン（２）に沿って凸面
部（３）、凹面部（４）、貫通部（５）を形成し、この
凸面部（３）、凹面部（４）、貫通部（５）によって形
成されるパターンに金属メッキ被膜層よりなる回路導体
部を形成することにより電気回路配線部、ＩＣチップ、
抵抗体等の電子部品がセラミックス板面の凹部に装着さ
れるので、セラミックス基板が平坦となり薄形のセラミ
ック配線基板と出来、必要に応じてセラミック配線基板
の積層化が実現できる。(Effects of the Invention) As described above, as a ceramic wiring board, a convex part (3), a concave part (4), and a through part (5) are formed along the electric circuit wiring pattern (2) on the temporary +1) surface of the ceramic. By forming a circuit conductor portion made of a metal plating film layer in the pattern formed by the convex surface portion (3), concave surface portion (4), and penetration portion (5), an electric circuit wiring portion, an IC chip,
Since electronic components such as resistors are mounted in the recesses on the surface of the ceramic plate, the ceramic substrate becomes flat and a thin ceramic wiring board can be obtained, and ceramic wiring boards can be laminated as required.
又、セラミックス基材を使用しているため放熱効果（熱
伝導率０．２０Ｗ ／ＣＭＫ）及び絶縁抵抗（１０１４
Ωｃｍ）においてセラミックス配線基板として理想的で
ある。 更にセラミック配線基板の製造方法の効果に
ついては以下述べる通りである。In addition, since a ceramic base material is used, the heat dissipation effect (thermal conductivity 0.20W/CMK) and insulation resistance (1014
Ωcm), making it ideal as a ceramic wiring board. Furthermore, the effects of the method for manufacturing a ceramic wiring board will be described below.
セラミック配線基板の製造方法とし、上述のように、セ
ラミックス板の表裏面を紫外線硬化樹脂レジスト層を形
成せしめた後、この紫外線硬化相」旨レジスト層に回路
等のパターンを転写し、このパターンのみを紫外線照射
によって硬化させる転写工程と、上記紫外線硬化樹脂レ
ジスト層以外の部分をセラミックエツチング加工を施し
セラミックス板に凸面部、凹面部、貫通面等を形成した
エツチング工程と、上記紫外線硬化樹脂レジス）ＩＮ以
外の部分に金属メッキを施して金属メッキ被膜層を形成
する金属メッキ工程とからなっているので、平滑なエツ
チング加工面に対する金属メッキの密着強度が良好であ
る。金属メッキの密着強度を検査するため、数社のメー
カーのセロハンテープによるビールテストを行ったとこ
ろ金属メッキは全く剥離しなかった。The method for manufacturing a ceramic wiring board is to form an ultraviolet curable resin resist layer on the front and back surfaces of a ceramic board as described above, and then transfer a pattern such as a circuit to this ultraviolet curable resist layer, and then transfer only this pattern. a transfer process in which the resist layer is cured by ultraviolet irradiation; an etching process in which parts other than the ultraviolet curable resin resist layer are subjected to ceramic etching to form convex surfaces, concave surfaces, penetrating surfaces, etc. on the ceramic plate; and the above ultraviolet curable resin resist). Since the process includes a metal plating process in which parts other than the IN are plated with metal to form a metal plating film layer, the adhesion strength of the metal plating to the smooth etched surface is good. In order to test the adhesion strength of the metal plating, we conducted a beer test using cellophane tape from several manufacturers, and the metal plating did not peel off at all.
回路等のパターン等の形成はアルミナエツチング加工に
よって行うので用途に応じた形状、微細なパターンにも
凹面加工が可能となる。Since patterns such as circuits are formed by alumina etching, it is possible to form concave surfaces into shapes and fine patterns depending on the application.
図面はこの発明の実施例を示すもので、第１図はセラミ
ック配線基板の斜視図、第２図ないし第３図はセラミッ
ク配線基板の実施例を示す拡大断面図、第４図はセラミ
ック配線基板にＵＶレジストを塗布する工程の断面図、
第５図はパターンを転写した後ＵＶレジストを露光した
状態の断面図、第６図はＵＶレジスト部の現像工程の断
面図、第７図はエツチング後のセラミック配線基板の断
面図、第８図はＵＶレジスト部を剥離した後凹部に金属
メッキ被膜層を形成した状態の断面図であるｆｌ＋・・
・セラミックス板
（２）・・・電気回路配線パターン
（３）・・・凸面部 （４）・・・凹面部（５）・
・・貫通部 （６）・・・回路導体部（７）・・・
電子部品
（８）・・・ＬＪＶ樹脂レジスト層
（９）・・・パターンフィルム
αの・・・ＵＶ樹脂レジスト除去面
特許出願人 東洋精密工業株式会社第イ図
第２図
第ｊ図
第り図
１工 Ｌ
昭和６２年ｆ月３つ′日The drawings show an embodiment of the present invention, in which Fig. 1 is a perspective view of a ceramic wiring board, Figs. 2 and 3 are enlarged sectional views showing an embodiment of the ceramic wiring board, and Fig. 4 is a ceramic wiring board. A cross-sectional view of the process of applying UV resist to
Fig. 5 is a cross-sectional view of the UV resist exposed after the pattern has been transferred, Fig. 6 is a cross-sectional view of the developing process of the UV resist portion, Fig. 7 is a cross-sectional view of the ceramic wiring board after etching, and Fig. 8 fl+ is a cross-sectional view of a state in which a metal plating film layer is formed in the recessed part after the UV resist part is peeled off.
・Ceramics board (2)...Electric circuit wiring pattern (3)...Convex surface portion (4)...Concave surface portion (5)・
... Penetration part (6) ... Circuit conductor part (7) ...
Electronic components (8)... LJV resin resist layer (9)... UV resin resist removal surface of pattern film α Patent applicant: Toyo Seimitsu Kogyo Co., Ltd. Figure A, Figure 2, Figure J, Figure 3 1st construction L 1986, f month 3' day
Claims (3)
（２）に沿って凸面部（３）、凹面部（４）、貫通部（
５）を形成し、この凸面部（３）、凹面部（４）、貫通
部（５）によって形成されるパターンに金属メッキ被膜
層よりなる回路導体部を形成したことを特徴とするセラ
ミック配線基板。(1) A convex part (3), a concave part (4), a through part (
5), and a circuit conductor portion made of a metal plating film layer is formed in a pattern formed by the convex surface portion (3), the concave surface portion (4), and the through portion (5). .
を特徴とする上記特許請求の範囲第１項記載のセラミッ
ク配線基板。(2) The ceramic wiring board according to claim 1, characterized in that an electronic component (7) is inserted into the recessed portion or the through portion.
レジスト層を形成せしめた後、この紫外線硬化樹脂レジ
スト層に回路等のパターンを転写し、このパターンのみ
を紫外線照射によって硬化させる転写工程と、上記紫外
線硬化樹脂レジスト層以外の部分をセラミックエッチン
グ加工を施しセラミックス板に凸面部、凹面部、貫通面
等を形成したエッチング工程と、上記紫外線硬化樹脂レ
ジスト層以外の部分に金属メッキを施して金属メッキ被
膜層を形成する金属メッキ工程とからなることを特徴と
するセラミック配線基板の製造方法。(3) A transfer step in which a UV-curable resin resist layer is formed on the front and back surfaces of the ceramic plate (1), a pattern such as a circuit is transferred to this UV-curable resin resist layer, and only this pattern is cured by UV irradiation. , an etching process in which a portion other than the ultraviolet curable resin resist layer is subjected to a ceramic etching process to form a convex surface, a concave surface, a penetrating surface, etc. on the ceramic plate, and a metal plating is applied to the portion other than the ultraviolet curable resin resist layer. A method for manufacturing a ceramic wiring board, comprising a metal plating step of forming a metal plating film layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6271686A JPS63114195A (en) | 1986-03-19 | 1986-03-19 | Ceramic wiring board and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6271686A JPS63114195A (en) | 1986-03-19 | 1986-03-19 | Ceramic wiring board and manufacture of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63114195A true JPS63114195A (en) | 1988-05-19 |
Family
ID=13208338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6271686A Pending JPS63114195A (en) | 1986-03-19 | 1986-03-19 | Ceramic wiring board and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63114195A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54106164A (en) * | 1978-02-09 | 1979-08-20 | Toppan Printing Co Ltd | Method of fabricating plasma display panel electrode plate |
| JPS566497A (en) * | 1979-06-27 | 1981-01-23 | Sumitomo Electric Industries | Method of manufacturing integrated circuit |
-
1986
- 1986-03-19 JP JP6271686A patent/JPS63114195A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54106164A (en) * | 1978-02-09 | 1979-08-20 | Toppan Printing Co Ltd | Method of fabricating plasma display panel electrode plate |
| JPS566497A (en) * | 1979-06-27 | 1981-01-23 | Sumitomo Electric Industries | Method of manufacturing integrated circuit |
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