JPS63111682A - Submount for optical semiconductor element - Google Patents
Submount for optical semiconductor elementInfo
- Publication number
- JPS63111682A JPS63111682A JP61259023A JP25902386A JPS63111682A JP S63111682 A JPS63111682 A JP S63111682A JP 61259023 A JP61259023 A JP 61259023A JP 25902386 A JP25902386 A JP 25902386A JP S63111682 A JPS63111682 A JP S63111682A
- Authority
- JP
- Japan
- Prior art keywords
- optical semiconductor
- submount
- semiconductor element
- wire
- bonding part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 230000003287 optical effect Effects 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000000853 adhesive Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 238000010348 incorporation Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
Landscapes
- Led Device Packages (AREA)
- Semiconductor Lasers (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業−１この利用分野〕
この発明は、光半導体素子をマウントするのに用いる光
半導体素子用サブマウントに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industry-1 Field of Application] The present invention relates to a submount for an optical semiconductor element used for mounting an optical semiconductor element.
第３図は、例えば特開昭５７−９３５９１号公報に示さ
れた従来のサブマウントを用いた光半導体装置を示す断
面図で゛あり、また、第４図は特開昭５８−５８７８５
号公報に示された従来のサブマウントを用いた光半導体
装置を示す断面図である。第３図において、１はステム
、２は前記ステム１上に接着されたサブマウント、３は
前記サブマウント２」二に接着された光半導体素子、４
は同じくサブマウント２上に接着された保護回路、８は
前記光半導体素子３と保護回路４とを接続するワイヤで
ある。FIG. 3 is a sectional view showing an optical semiconductor device using a conventional submount disclosed in, for example, Japanese Patent Laid-Open No. 57-93591, and FIG.
1 is a cross-sectional view showing an optical semiconductor device using a conventional submount disclosed in the publication. In FIG. 3, 1 is a stem, 2 is a submount bonded on the stem 1, 3 is an optical semiconductor element bonded to the submount 2'', and 4
Similarly, numeral 8 represents a protection circuit bonded on the submount 2, and 8 represents a wire connecting the optical semiconductor element 3 and the protection circuit 4.
また、第４図におけるサブマウント２は、Ｐ型領域５．
Ｎ型領域６を有し、ＰＮ接合７を形成している。Further, the submount 2 in FIG. 4 has a P-type region 5.
It has an N-type region 6 and forms a PN junction 7.
半導体レーザダイオード（ＬＤ）や発光ダイオード（Ｌ
ＥＤ）あるいはフォトダイオード（ＰＤ）等の光半導体
素子３はサブマウント２に接着され、さらに、サブマウ
ント２がステム］に接着される。また、光半導体素子３
に電流が流れるようにワイヤ８が接着され、ステム１本
体の電気的特性が■となる。第３図に示した例はサブマ
ウント２に保護回路４を接着し、光半導体素子３と保護
回路４をワイヤ８で接着して、電流が保護回路４を通っ
て光半導体素子３に流れるようになっている。Semiconductor laser diode (LD) and light emitting diode (L)
An optical semiconductor element 3 such as an optical diode (ED) or a photodiode (PD) is bonded to a submount 2, and the submount 2 is further bonded to a stem. In addition, the optical semiconductor element 3
The wire 8 is bonded so that a current flows through the stem 1, and the electrical characteristics of the stem 1 body become ■. In the example shown in FIG. 3, a protection circuit 4 is bonded to the submount 2, and the optical semiconductor element 3 and the protection circuit 4 are bonded with a wire 8, so that current flows through the protection circuit 4 to the optical semiconductor element 3. It has become.
また、第４図に示した例は、ＰＮ接合７を有したサブマ
ウント２に光半導体素子３を接着し、電流を光半導体素
子３に流して動作させるとともに、独立にサブマウント
２のＰＮ接合７にも電流を流して、ベルチェ効果を利用
して放熱効果を高めている。第３図に示した例では、サ
ブマウント２には主に熱伝導性の良い絶縁材料（Ｓｉ、
ＢｅＯ，ＳｉＣ，ダイヤモンド等）が用いられている。In addition, in the example shown in FIG. 4, an optical semiconductor element 3 is bonded to a submount 2 having a PN junction 7, a current is applied to the optical semiconductor element 3 to operate it, and the PN junction of the submount 2 is independently connected. A current is also passed through 7 to enhance the heat dissipation effect by utilizing the Beltier effect. In the example shown in Fig. 3, the submount 2 is mainly made of an insulating material (Si,
BeO, SiC, diamond, etc.) are used.
〔発明が解決しようとする問題点〕
上記のように構成された従来のサブマウントは、光半導
体素子３から生じる熱を放出させることにより熱抵抗を
下げるのと、接着部に生じる線膨張係数のずれからの機
械的歪を緩和する目的で用いている。光半導体素子３を
動作させるために、駆動回路（図示せず）をパッケージ
の外部もしくは内部に設ける必要がある。外部に設けた
場合、システム全体が大きくなってしまう。駆動回路を
モノリシックに集積して第３図においてサブマウント２
」二に接着した場合、パッケージが大型化する。また、
第４図のように、サブマウント２にＰＮ接合７を設けた
ものもあるが、これは駆動回路ではなく、光半導体素子
３の放熱効果を図るために用いられているものであり、
光半導体素子３とは独立に動作される。したがって、こ
の例においてもパッケージが大型化するという問題点が
あった。[Problems to be Solved by the Invention] The conventional submount configured as described above lowers thermal resistance by releasing heat generated from the optical semiconductor element 3, and lowers the coefficient of linear expansion generated at the adhesive part. It is used to alleviate mechanical strain caused by misalignment. In order to operate the optical semiconductor element 3, it is necessary to provide a drive circuit (not shown) outside or inside the package. If it is provided externally, the entire system will become larger. The drive circuit is monolithically integrated into the submount 2 in Figure 3.
” If it is glued to the second layer, the package will become larger. Also,
As shown in FIG. 4, there is a submount 2 with a PN junction 7, but this is used not for the drive circuit but for the purpose of improving the heat dissipation effect of the optical semiconductor element 3.
It is operated independently of the optical semiconductor element 3. Therefore, this example also has the problem that the package becomes large.
この発明は、上記のような問題点を解消するためになさ
れたもので、光半導体素子が安定に動作するとともに、
小型化が実現できる光半導体素子用サブマウントを得る
ことを目的とする。This invention was made to solve the above-mentioned problems, and allows the optical semiconductor device to operate stably, and
The purpose of this invention is to obtain a submount for optical semiconductor devices that can be miniaturized.
この発明に係る光半導体素子用サブマウントは、半導体
絶縁基板に光半導体素子を駆動する駆動回路を形成し、
その面上に光半導体素子を接着する導電性の素子接着部
と、ワイヤを接着する導電性のワイヤ接着部を備えたも
のである。A submount for an optical semiconductor element according to the present invention forms a drive circuit for driving an optical semiconductor element on a semiconductor insulating substrate,
It is provided with a conductive element bonding part for bonding an optical semiconductor element on the surface and a conductive wire bonding part for bonding a wire.
この発明においては、半導体絶縁基板に光半導体素子を
駆動するための駆動回路を集積化してサブマウントを形
成したことから、素子接着部に接着された光半導体素子
は、ワイヤが接続されていない状態では、絶縁された状
態である。これに、適当にワイヤを接続することにより
、光半導体素子および駆動回路を直列および並列、さら
に個々に独立に動作させることが可能となる。また、外
部に駆動回路を設けなくてもよいことから、小型化でき
る。In this invention, since a submount is formed by integrating a drive circuit for driving an optical semiconductor element on a semiconductor insulating substrate, the optical semiconductor element bonded to the element adhesive part is in a state where no wire is connected. Now, it is in an insulated state. By appropriately connecting wires to this, it becomes possible to operate the optical semiconductor element and the drive circuit in series, in parallel, and even independently. Further, since there is no need to provide an external drive circuit, the size can be reduced.
第１図（ａ）、（ｂ）はこの発明の一実施例を示す図で
、第１図（ａ）はサブマウントの斜視図であり、第１図
（ｂ）は第１図（ａ）のサブマウント上に光半導体素子
を組み立てた状態を示す正面図である。FIGS. 1(a) and 1(b) are views showing one embodiment of the present invention, FIG. 1(a) is a perspective view of a submount, and FIG. 1(b) is a perspective view of a submount. FIG. 3 is a front view showing a state in which the optical semiconductor device is assembled on the submount of the device.
これらの図において、第３図と同一符号は同一部分を示
し、１ｏは半導体絶縁基板、１１は素子接着部、１２は
ワイヤ接着部、１３は前記半導体絶縁基板１０に拡散、
イオン注入、エピタキシャル成長等の技術を用いてモノ
リシックに集積化された光半導体素子３を駆動するため
の駆動回路である。以上でこの発明のサブマウント２０
が構成される。このサブマウント２０上に第１図（ｂ）
のように、光半導体素子３を素子接着部１１に接着し、
ワイヤ８により光半導体素子３と駆動回路１３とをワイ
ヤ接着部１２を用いて接着し、゛さらに、このサブマウ
ント２０をステム１上に接着し、組立てが行われる。In these figures, the same reference numerals as in FIG. 3 indicate the same parts, 1o is the semiconductor insulating substrate, 11 is the element bonding part, 12 is the wire bonding part, 13 is the diffusion into the semiconductor insulating substrate 10,
This is a drive circuit for driving an optical semiconductor element 3 monolithically integrated using techniques such as ion implantation and epitaxial growth. This concludes the submount 20 of this invention.
is configured. On this submount 20, as shown in FIG.
The optical semiconductor element 3 is adhered to the element adhesive part 11 as shown in FIG.
The optical semiconductor element 3 and the drive circuit 13 are bonded together using the wire bonding portion 12 using the wire 8, and then the submount 20 is bonded onto the stem 1 to complete the assembly.
駆動回路１３としては、光半導体素子３がＬＤの場合、
変調回路、バイアス回路、ＡＰＣ回路など、ＬＥＤの場
合、変調回路、バイアス回路。As the drive circuit 13, when the optical semiconductor element 3 is an LD,
For LEDs, modulation circuits, bias circuits, APC circuits, etc.
ＡＣＣ回路など、ＰＤの場合、バイアス回路などが用い
られるが、一般に使用する光半導体素子３により駆動回
路１３が異なるため、特に限定しない。In the case of a PD such as an ACC circuit, a bias circuit or the like is used, but since the drive circuit 13 generally differs depending on the optical semiconductor element 3 used, it is not particularly limited.
また、第１図（ｂ）に示すように、光半導体素子３は半
導体絶縁基板１ｏ上にモノリシックに集積化された駆動
回路１３とワイヤ接着部１２および素子接着部１１から
なるサブマウント２０の素子接着部１１に接着され、さ
らにステム（またはパッケージ）１に接着される。光半
導体素子３に駆動回路１３を通して電流が流れるように
ワイヤ８が接着される。駆動回路］３にバイアスをかけ
ることにより駆動回路１３が動作し、駆動回路１３のも
つ機能に応じて光半導体素子３が動作する。サブマウン
）２０本体は半導体絶縁基板１０からなり、光半導体素
子３に用いられている半導体基板と同一材料を用いるこ
とにより熱伝導性が良くなり、光半導体素子３の放熱性
が良くなる。Further, as shown in FIG. 1(b), the optical semiconductor element 3 is an element of a submount 20 consisting of a drive circuit 13 monolithically integrated on a semiconductor insulating substrate 1o, a wire bonding part 12, and an element bonding part 11. It is adhered to the adhesive part 11 and further to the stem (or package) 1. A wire 8 is bonded to the optical semiconductor element 3 so that a current flows through the drive circuit 13. The drive circuit 13 operates by applying a bias to the drive circuit 3, and the optical semiconductor element 3 operates according to the function of the drive circuit 13. The main body of the sub-mount) 20 is made of a semiconductor insulating substrate 10, and by using the same material as the semiconductor substrate used for the optical semiconductor element 3, thermal conductivity is improved, and the heat dissipation of the optical semiconductor element 3 is improved.
なお、上記実施例においては、素子接着部１１が光半導
体素子３を駆動するための駆動回路１３とは独立して形
成されているが、第２図に示すように、あらかじめ駆動
回路１３の領域上の一部に素子接着部１１を設けてもよ
い。In the above embodiment, the element adhesive part 11 is formed independently of the drive circuit 13 for driving the optical semiconductor element 3, but as shown in FIG. The element adhesive part 11 may be provided in a part of the upper part.
この発明は以上説明したとおり、半導体絶縁基板に光半
導体素子を駆動する駆動回路を形成し、その面上に光半
導体素子を接着する導電性の素子接着部と、ワイヤを接
着する導電性のワイヤ接着部を形成してサブマウントを
構成したので、このサブマウントを用いることにより内
蔵された駆動回路により光半導体素子が安定に動作する
とともに、駆動回路をパッケージ内に内蔵していること
により小型化できる。さらに、光半導体素子と駆動回路
とをモノリシックに集積化した０ＥＩＣと同等の性能が
得られるハイブリッドタイプの０ＥＩＣが可能となるた
め、光半導体素子と駆動回路とをモノリシックに集積化
した０ＥＩＣに比べ安価にできる等の利点がある。As explained above, the present invention includes a drive circuit for driving an optical semiconductor element formed on a semiconductor insulating substrate, a conductive element bonding part for bonding the optical semiconductor element on the surface thereof, and a conductive wire for bonding the wire. Since the submount is constructed by forming an adhesive part, by using this submount, the optical semiconductor element can operate stably due to the built-in drive circuit, and it can also be miniaturized by incorporating the drive circuit inside the package. can. Furthermore, it is possible to create a hybrid type 0EIC that can achieve the same performance as an 0EIC that monolithically integrates an optical semiconductor element and a drive circuit, which is cheaper than an 0EIC that monolithically integrates an optical semiconductor element and a drive circuit. There are advantages such as being able to
第１図（ａ）、（ｂ）はこの発明の一実施例を示す図で
あり、第１図（ａ）はサブマウントの斜視図、第１図（
ｂ）は第１図（ａ）のサブマウントを用いた組立て状態
を示す正面図、第２図はこの発明の他の実施例を示す斜
視図、第３図および第４図は従来のサブマウントとその
サブマウントを用いた組立て状態を示す正面図である。
図において、１はステム、３は光半導体素子、８はワイ
ヤ、１０は半導体絶縁基板、１１は素子接着部、１２は
ワイヤ接着部、１３は駆動回路である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第１図
Ｑ 〜
手続補正書（自発）
］
日
３、補正をする者
３号
３号
５、補正の対象
明細書の発明の詳細な説明の欄および図面６、補正の内
容
（１）明細書第４頁３行の「サブマウント」を、「サブ
マウント２」と補正する。
（２）第１図（ｂ）、第２図を別紙のように補正する。
以」ニFIGS. 1(a) and 1(b) are views showing one embodiment of the present invention, FIG. 1(a) is a perspective view of a submount, and FIG.
b) is a front view showing an assembled state using the submount of Fig. 1(a), Fig. 2 is a perspective view showing another embodiment of the present invention, and Figs. 3 and 4 are conventional submounts. FIG. 3 is a front view showing an assembled state using a submount and a submount thereof. In the figure, 1 is a stem, 3 is an optical semiconductor element, 8 is a wire, 10 is a semiconductor insulating substrate, 11 is an element bonding part, 12 is a wire bonding part, and 13 is a drive circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Q - Procedural amendment (voluntary)] Day 3, person making the amendment No. 3, No. 3, No. 5, column for detailed explanation of the invention in the specification to be amended, and Drawing 6, Contents of correction (1) "Submount" on page 4, line 3 of the specification is corrected to "submount 2." (2) Correct Fig. 1(b) and Fig. 2 as shown in the attached sheet. I”d
Claims (4)
路を形成し、その面上に前記光半導体素子を接着する導
電性の素子接着部と、ワイヤを接着する導電性のワイヤ
接着部を備えたことを特徴とする光半導体素子用サブマ
ウント。(1) A drive circuit for driving an optical semiconductor element is formed on a semiconductor insulating substrate, and a conductive element bonding part for bonding the optical semiconductor element and a conductive wire bonding part for bonding a wire are provided on the surface of the drive circuit. A submount for optical semiconductor devices characterized by:
る半導体基板と同一材料であることを特徴とする特許請
求の範囲第（１）項記載の光半導体素子用サブマウント
。(2) The submount for an optical semiconductor device according to claim (1), wherein the semiconductor insulating substrate is made of the same material as the semiconductor substrate used in the optical semiconductor device.
形成されていることを特徴とする特許請求の範囲第（１
）項記載の光半導体素子用サブマウント。(3) The drive circuit is monolithically formed on a semiconductor insulating substrate.
) A submount for optical semiconductor devices as described in item 2.
に設けられていることを特徴とする特許請求の範囲第（
１）項記載の光半導体素子用サブマウント。(4) The conductive element adhesive portion is provided in a part of the region of the drive circuit,
1) Submount for optical semiconductor devices as described in item 1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61259023A JPS63111682A (en) | 1986-10-29 | 1986-10-29 | Submount for optical semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61259023A JPS63111682A (en) | 1986-10-29 | 1986-10-29 | Submount for optical semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63111682A true JPS63111682A (en) | 1988-05-16 |
| JPH0459791B2 JPH0459791B2 (en) | 1992-09-24 |
Family
ID=17328273
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61259023A Granted JPS63111682A (en) | 1986-10-29 | 1986-10-29 | Submount for optical semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63111682A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007129188A (en) * | 2005-10-07 | 2007-05-24 | Hitachi Maxell Ltd | Semiconductor device, semiconductor module, and method of manufacturing the semiconductor module |
| JP2009510732A (en) * | 2005-09-30 | 2009-03-12 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Detector device and detector element |
| JP2010533975A (en) * | 2007-07-17 | 2010-10-28 | クリー インコーポレイテッド | LED with integrated constant current drive circuit |
| JP2012060133A (en) * | 2010-09-10 | 2012-03-22 | Samsung Led Co Ltd | Light-emitting device, illumination apparatus, and backlight |
| US8791645B2 (en) | 2006-02-10 | 2014-07-29 | Honeywell International Inc. | Systems and methods for controlling light sources |
| US8803313B2 (en) | 2003-01-02 | 2014-08-12 | Cree, Inc. | Group III nitride based flip-chip integrated circuit and method for fabricating |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58158459U (en) * | 1982-04-16 | 1983-10-22 | 三洋電機株式会社 | light emitting diode |
-
1986
- 1986-10-29 JP JP61259023A patent/JPS63111682A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58158459U (en) * | 1982-04-16 | 1983-10-22 | 三洋電機株式会社 | light emitting diode |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8803313B2 (en) | 2003-01-02 | 2014-08-12 | Cree, Inc. | Group III nitride based flip-chip integrated circuit and method for fabricating |
| US9226383B2 (en) | 2003-01-02 | 2015-12-29 | Cree, Inc. | Group III nitride based flip-chip integrated circuit and method for fabricating |
| JP2009510732A (en) * | 2005-09-30 | 2009-03-12 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Detector device and detector element |
| DE102005061206B4 (en) | 2005-09-30 | 2019-10-17 | Osram Opto Semiconductors Gmbh | Use of a detector arrangement as ambient light sensor |
| JP2007129188A (en) * | 2005-10-07 | 2007-05-24 | Hitachi Maxell Ltd | Semiconductor device, semiconductor module, and method of manufacturing the semiconductor module |
| US8791645B2 (en) | 2006-02-10 | 2014-07-29 | Honeywell International Inc. | Systems and methods for controlling light sources |
| US8937443B2 (en) | 2006-02-10 | 2015-01-20 | Honeywell International Inc. | Systems and methods for controlling light sources |
| JP2010533975A (en) * | 2007-07-17 | 2010-10-28 | クリー インコーポレイテッド | LED with integrated constant current drive circuit |
| US8569970B2 (en) | 2007-07-17 | 2013-10-29 | Cree, Inc. | LED with integrated constant current driver |
| US8810151B2 (en) | 2007-07-17 | 2014-08-19 | Cree, Inc. | LED with integrated constant current driver |
| JP2012060133A (en) * | 2010-09-10 | 2012-03-22 | Samsung Led Co Ltd | Light-emitting device, illumination apparatus, and backlight |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0459791B2 (en) | 1992-09-24 |
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