JPS63110920U

JPS63110920U -

Info

Publication number: JPS63110920U
Application number: JP19966186U
Authority: JP
Priority date: 1986-12-30
Filing date: 1986-12-30
Publication date: 1988-07-16

Description

[Brief explanation of the drawing]

第１図は本考案の実施例にかかる定電圧直流電
源回路図、第２図は遅延時間設定回路及びスイツ
チング回路の具体的な回路図、第３図は波形図、
第４は従来例の定電圧直流電源回路図である。１６，２２…整流平滑回路、１８，２０，２４
…定電圧回路、４４，５８，７６…電圧制御回路
、８０…遅延時間設定回路、６…スイツチング回
路、９０，９８…微分回路、９２，１００，１１
０，１１４…可変モノマルチバイブレータ、１１
７…リツセト回路。 FIG. 1 is a constant voltage DC power supply circuit diagram according to an embodiment of the present invention, FIG. 2 is a specific circuit diagram of a delay time setting circuit and a switching circuit, and FIG. 3 is a waveform diagram.
The fourth is a conventional constant voltage DC power supply circuit diagram. 16, 22... Rectifier smoothing circuit, 18, 20, 24
... Constant voltage circuit, 44, 58, 76... Voltage control circuit, 80... Delay time setting circuit, 6... Switching circuit, 90, 98... Differentiating circuit, 92, 100, 11
0,114...Variable mono multivibrator, 11
7...Retset circuit.

補正昭６２．４．１７図面の簡単な説明を次のように補正する。明細書の第１８頁第１７行目の「第４は従来例
」を「第４図は従来例」と訂正する。Amendment April 17, 1982 The brief description of the drawing is amended as follows. "The fourth is a conventional example" on page 18, line 17 of the specification is corrected to "FIG. 4 is a conventional example."

Claims

[Claims for Utility Model Registration] Comparing each divided voltage of a plurality of output voltages with a reference voltage and applying a voltage corresponding to the difference between the input and output terminals of each voltage control circuit to the control terminal of each voltage control circuit. A constant voltage DC power supply circuit that keeps the voltage at the output terminal constant by changing the resistance value of the control terminal includes a variable setting circuit that variably sets each delay time, and an output switch that controls the voltage applied to the control terminal. a switching circuit that turns on and off the output terminal voltage of the voltage control circuit after each delay time of each of the set outputs has elapsed after turning on and off the output terminal of the voltage control circuit.