JPS61170097U - - Google Patents

Info

Publication number
JPS61170097U
JPS61170097U JP5406585U JP5406585U JPS61170097U JP S61170097 U JPS61170097 U JP S61170097U JP 5406585 U JP5406585 U JP 5406585U JP 5406585 U JP5406585 U JP 5406585U JP S61170097 U JPS61170097 U JP S61170097U
Authority
JP
Japan
Prior art keywords
trimming
adjustment
decoder circuit
terminals
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5406585U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5406585U priority Critical patent/JPS61170097U/ja
Publication of JPS61170097U publication Critical patent/JPS61170097U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Electric Clocks (AREA)
  • Testing Or Calibration Of Command Recording Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のトリミング回路図、第2図は
従来の分周比制御の場合の回路図、第3図は本考
案の設定電圧の関係図、第4図は本考案のトリミ
ング用端子が少ない場合の回路図。 4……トリミング用端子、5……入力プルダウ
ン回路、6……入力インバータ、7……PLA、
8……プログラマブル定電圧回路、13……トリ
ミング用端子、14……プルダウン回路、15…
…PLA。
Figure 1 is a trimming circuit diagram of the present invention, Figure 2 is a circuit diagram for conventional frequency division ratio control, Figure 3 is a relationship diagram of setting voltages of the present invention, and Figure 4 is the trimming terminal of the present invention. Circuit diagram when there are few. 4...Trimming terminal, 5...Input pull-down circuit, 6...Input inverter, 7...PLA,
8...Programmable constant voltage circuit, 13...Trimming terminal, 14...Pull-down circuit, 15...
...P.L.A.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のトリミング端子と、このトリミング端子
が接続され無調整時には調整範囲の中間値を出力
するデコーダ回路と、このデコーダ回路の出力が
入力される調整用入力端子とを具備したことを特
徴とするトリミング機能付電子機器。
A trimming device comprising a plurality of trimming terminals, a decoder circuit to which the trimming terminals are connected and outputs an intermediate value of the adjustment range when no adjustment is made, and an adjustment input terminal to which the output of the decoder circuit is input. Electronic equipment with functions.
JP5406585U 1985-04-10 1985-04-10 Pending JPS61170097U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5406585U JPS61170097U (en) 1985-04-10 1985-04-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5406585U JPS61170097U (en) 1985-04-10 1985-04-10

Publications (1)

Publication Number Publication Date
JPS61170097U true JPS61170097U (en) 1986-10-22

Family

ID=30575495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5406585U Pending JPS61170097U (en) 1985-04-10 1985-04-10

Country Status (1)

Country Link
JP (1) JPS61170097U (en)

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