JPS63110749A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63110749A
JPS63110749A JP25565486A JP25565486A JPS63110749A JP S63110749 A JPS63110749 A JP S63110749A JP 25565486 A JP25565486 A JP 25565486A JP 25565486 A JP25565486 A JP 25565486A JP S63110749 A JPS63110749 A JP S63110749A
Authority
JP
Japan
Prior art keywords
layer
silicide
alloy
semiconductor device
refractory metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25565486A
Other languages
Japanese (ja)
Inventor
Kenji Hinode
憲治 日野出
Naoki Yamamoto
直樹 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP25565486A priority Critical patent/JPS63110749A/en
Publication of JPS63110749A publication Critical patent/JPS63110749A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To maintain an electrically stable connection by a method wherein a reaction between a silicide layer and an Al alloy layer is suppressed in such a way that a reaction-suppressing layer is formed between the Al alloy layer and the silicide layer. CONSTITUTION:After a silicon oxide film 4 is formed on an Si substrate 5, a refractory metal silicide 3 is coated and is processed so that a desired pattern 3 as an under-layer wiring part can be obtained by photoetching. In addition, after an insulating film 4' is coated and formed, an opening 6 is made. Then, a retractory metal nitride layer 2 and an Al alloy layer 1 are piled up as an upper-layer wiring part, and these are processed to form a prescribed pattern. Because the refractory metal nitride is an electric conductor and a very stable compound, it does hardly react with an Al alloy and a refractory metal silicide during a heat-treatment process which is required for the manufacture of a semiconductor device, and its stable structure can be maintained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特に高信頼度。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device, and particularly to a semiconductor device with high reliability.

高集積度の半導体装置に関する。The present invention relates to highly integrated semiconductor devices.

〔従来の技術〕[Conventional technology]

従来、シリサイドとktとの接続について「シリサイド
・7オー・ブイエルニスアイ・アプリケーションズ」ム
ラルカ著(1983年)、第156頁から第161頁(
” 5ilicides for VLSIAppli
cations ” ed by S、P、 Mura
rka(1983)pp、 156−161 )に述べ
られているように、約500Cまでは両者の接続は安定
でVLS I応用上問題はないと考えられてきた。
Conventionally, regarding the connection between silicide and kt, ``Silicide 7 O Buyernis Eye Applications'' by Murarka (1983), pp. 156 to 161 (
” 5 ilicides for VLSI Appli
cations” ed by S, P, Mura
rka (1983) pp. 156-161), it has been thought that the connection between the two is stable up to about 500C and poses no problem in VLSI applications.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来技術では、AlもしくはAl合金とシリサイドが直
接に接触しており、接続部の面積が大きい場合は十分低
い抵抗値を得られるが、1μm程度以下の微細な接続部
においては1両者の反応により高抵抗化するという問題
が生じることが本発明者の検討で明らかとなった。本発
明の目的は。
In the conventional technology, Al or Al alloy and silicide are in direct contact, and if the area of the connection is large, a sufficiently low resistance value can be obtained, but in a minute connection of about 1 μm or less, a reaction between the two The inventor's studies have revealed that the problem of high resistance occurs. The purpose of the present invention is to:

シリサイド層とAl合金層との反応を抑制し、電気的に
安定な接続を維持することにある。
The purpose is to suppress the reaction between the silicide layer and the Al alloy layer and maintain an electrically stable connection.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、Al合金層とシリサイド層との直接の接触
を避け、両者間に反応抑止層を設けることにより達成さ
れる。
The above object is achieved by avoiding direct contact between the Al alloy layer and the silicide layer and providing a reaction inhibiting layer between them.

〔作用〕[Effect]

高融点金属窒化物は、導電体でありかつ非常に安定な化
合物であるため、半導体装置製造工程で必要な熱処理で
は、Al合金、高融点金属シリサイドとほとんど反応せ
ず1安定な構造を保つことができるので、上記反応抑止
層として極めて好適である。
High melting point metal nitride is a conductor and a very stable compound, so it hardly reacts with Al alloys and high melting point metal silicides during the heat treatment required in the semiconductor device manufacturing process, and maintains a stable structure. Therefore, it is extremely suitable as the reaction inhibiting layer.

〔実施例〕〔Example〕

本発明を以下、実施例をもって説明する。 The present invention will be explained below with reference to Examples.

第1図に示すように、Si基板5上に酸化シリコン膜4
を形成後、WSizをCVD法にて被潰し、通常のフォ
トエツチング工程を経て下層配線として所望のパターン
3に加工した。更に絶縁膜4′を被着形成後、開孔部6
を形成した。次に上層配線としテ、 ’I’ i Nノ
ミ 2 、 Al合金(Al1%Si)層1を積層し、
所定のパターンに加工した。Al層1.’rrN層2は
それぞれ、スパッタ法1反応性スパッタ法で形成したが
、製造工程での500C程度の熱処理に耐えるためには
、TiN層2として、膜質に依存するが50〜2000
m程度の膜厚が必要であった。本実施例では、TiN/
12の厚さが* 50nm、200nmのもの2種類と
As shown in FIG. 1, a silicon oxide film 4 is formed on a Si substrate 5.
After forming WSiz, the WSiz was crushed by CVD and processed into a desired pattern 3 as a lower layer wiring through a normal photoetching process. Furthermore, after forming the insulating film 4', the opening 6 is
was formed. Next, as the upper layer wiring, 'I' iN chisel 2 and Al alloy (Al1%Si) layer 1 are laminated,
Processed into a predetermined pattern. Al layer 1. 'rrN layer 2 was formed by sputtering method 1 reactive sputtering method, but in order to withstand heat treatment of about 500C in the manufacturing process, as TiN layer 2, it is necessary to
A film thickness of about 1.0 m was required. In this example, TiN/
12 with two types of thickness: 50nm and 200nm.

TiN層2のない従来構造の試料を炸裂した。第1図に
示す接続部を100個、直列接続したパターンに対し熱
処理を追加しながら、抵抗値を測定した。不良モードは
接触抵抗値の増加であるため初期正常抵抗値(故Ω/個
以下)の2倍以上の抵抗のものを不良とし、各々約10
0個の試料の測定から不良率を算出した。結果を第1表
に示す。
A sample with a conventional structure without the TiN layer 2 was exploded. The resistance value was measured while additional heat treatment was applied to the pattern in which 100 connection parts shown in FIG. 1 were connected in series. Since the failure mode is an increase in contact resistance value, those with a resistance more than twice the initial normal resistance value (less than Ω/piece) are considered failures, and each approximately 10
The defect rate was calculated from the measurement of 0 samples. The results are shown in Table 1.

第1表 !11g19から明らかなように、TiN層を設けるこ
とによって、抵抗値の増加が有効に防止できることが確
認された。
Table 1! As is clear from 11g19, it was confirmed that an increase in resistance value can be effectively prevented by providing a TiN layer.

〔発明の効果〕〔Effect of the invention〕

不発明によれば、製造工程で必要な熱処理を経てもSi
素子と配線との接続部での抵抗値は増加せず安定に保た
nるため、高性能、高信頼度の素子を製造できる利点が
ある。
According to the invention, even after the heat treatment required in the manufacturing process, Si
Since the resistance value at the connection between the element and the wiring does not increase and is kept stable, there is an advantage that high performance and highly reliable elements can be manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の断面図である。 1−Al合金層+ 2・’riN層、 3 =W S 
i * /ilj 。 二き 1.1 第1 凹 / A18金漫 5Sカ基詣、
FIG. 1 is a sectional view of an embodiment of the present invention. 1-Al alloy layer + 2・'riN layer, 3 = W S
i*/ilj. 2.1.1 1st concave / A18 Kinman 5S Ka-Pilgrimage,

Claims (1)

【特許請求の範囲】 1、高融点金属シリサイドとAl合金との接続部を有す
る半導体装置において、少なくとも上記接続部の高融点
金属シリサイドとAl合金の間に、高融点金属の窒化物
層を有することを特徴とする半導体装置。 2、上記高融点金属シリサイドがタングステンシリサイ
ド又はモリブデンシリサイド又はチタンシリサイド又は
タンタルシリサイドであり、上記高融点金属の窒化物が
、窒化チタン又は窒化タングステンである特許請求の範
囲第1項記載の半導体装置。
[Scope of Claims] 1. A semiconductor device having a connection portion between a high melting point metal silicide and an Al alloy, including a nitride layer of a high melting point metal at least between the high melting point metal silicide and the Al alloy in the connection portion. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the high melting point metal silicide is tungsten silicide, molybdenum silicide, titanium silicide, or tantalum silicide, and the high melting point metal nitride is titanium nitride or tungsten nitride.
JP25565486A 1986-10-29 1986-10-29 Semiconductor device Pending JPS63110749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25565486A JPS63110749A (en) 1986-10-29 1986-10-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25565486A JPS63110749A (en) 1986-10-29 1986-10-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63110749A true JPS63110749A (en) 1988-05-16

Family

ID=17281755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25565486A Pending JPS63110749A (en) 1986-10-29 1986-10-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63110749A (en)

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